1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
32 def tocentry : Operand<iPTR> {
33 let MIOperandInfo = (ops i64imm:$imm);
35 def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64
36 let PrintMethod = "printMemRegImm";
37 let EncoderMethod = "getMemRIXEncoding";
38 let MIOperandInfo = (ops symbolLo64:$off, ptr_rc_nor0:$reg);
40 def tlsreg : Operand<i64> {
41 let EncoderMethod = "getTLSRegEncoding";
43 def tlsgd : Operand<i64> {}
45 //===----------------------------------------------------------------------===//
46 // 64-bit transformation functions.
49 def SHL64 : SDNodeXForm<imm, [{
50 // Transformation function: 63 - imm
51 return getI32Imm(63 - N->getZExtValue());
54 def SRL64 : SDNodeXForm<imm, [{
55 // Transformation function: 64 - imm
56 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
59 def HI32_48 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
64 def HI48_64 : SDNodeXForm<imm, [{
65 // Transformation function: shift the immediate value down into the low bits.
66 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
70 //===----------------------------------------------------------------------===//
75 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
78 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
79 // Convenient aliases for call instructions
81 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
82 "bl $func", BrB, []>; // See Pat patterns below.
84 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func),
85 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
87 let Uses = [RM], isCodeGenOnly = 1 in {
88 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
89 (outs), (ins calltarget:$func),
90 "bl $func\n\tnop", BrB, []>;
92 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
93 (outs), (ins calltarget:$func, tlsgd:$sym),
94 "bl $func($sym)\n\tnop", BrB, []>;
96 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
97 (outs), (ins calltarget:$func, tlsgd:$sym),
98 "bl $func($sym)\n\tnop", BrB, []>;
100 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
101 (outs), (ins aaddr:$func),
102 "bla $func\n\tnop", BrB,
103 [(PPCcall_nop (i64 imm:$func))]>;
105 let Uses = [CTR8, RM] in {
106 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
107 "bctrl", BrB, [(PPCbctrl)]>,
108 Requires<[In64BitMode]>;
114 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
115 (BL8 tglobaladdr:$dst)>;
116 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
117 (BL8_NOP tglobaladdr:$dst)>;
119 def : Pat<(PPCcall (i64 texternalsym:$dst)),
120 (BL8 texternalsym:$dst)>;
121 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
122 (BL8_NOP texternalsym:$dst)>;
125 let usesCustomInserter = 1 in {
126 let Defs = [CR0] in {
127 def ATOMIC_LOAD_ADD_I64 : Pseudo<
128 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
129 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
130 def ATOMIC_LOAD_SUB_I64 : Pseudo<
131 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
132 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
133 def ATOMIC_LOAD_OR_I64 : Pseudo<
134 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
135 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
136 def ATOMIC_LOAD_XOR_I64 : Pseudo<
137 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
138 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
139 def ATOMIC_LOAD_AND_I64 : Pseudo<
140 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
141 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
142 def ATOMIC_LOAD_NAND_I64 : Pseudo<
143 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
144 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
146 def ATOMIC_CMP_SWAP_I64 : Pseudo<
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
149 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
151 def ATOMIC_SWAP_I64 : Pseudo<
152 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
153 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
157 // Instructions to support atomic operations
158 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
159 "ldarx $rD, $ptr", LdStLDARX,
160 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
163 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
164 "stdcx. $rS, $dst", LdStSTDCX,
165 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
168 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
169 def TCRETURNdi8 :Pseudo< (outs),
170 (ins calltarget:$dst, i32imm:$offset),
171 "#TC_RETURNd8 $dst $offset",
174 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
175 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
176 "#TC_RETURNa8 $func $offset",
177 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
179 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
180 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
181 "#TC_RETURNr8 $dst $offset",
185 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
186 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in {
187 let isReturn = 1 in {
188 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
189 Requires<[In64BitMode]>;
192 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
193 Requires<[In64BitMode]>;
197 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
198 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
199 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
204 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
205 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
206 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
210 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
211 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
213 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
214 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
216 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
217 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
219 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
220 let Defs = [CTR8], Uses = [CTR8] in {
221 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
223 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
228 // 64-but CR instructions
229 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
230 "mtcrf $FXM, $rS", BrMCRX>,
231 PPC970_MicroCode, PPC970_Unit_CRU;
233 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
234 "#MFCR8pseud", SprMFCR>,
235 PPC970_MicroCode, PPC970_Unit_CRU;
237 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
238 "mfcr $rT", SprMFCR>,
239 PPC970_MicroCode, PPC970_Unit_CRU;
241 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
242 usesCustomInserter = 1 in {
243 def EH_SjLj_SetJmp64 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
245 [(set GPRC:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
246 Requires<[In64BitMode]>;
247 let isTerminator = 1 in
248 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
249 "#EH_SJLJ_LONGJMP64",
250 [(PPCeh_sjlj_longjmp addr:$buf)]>,
251 Requires<[In64BitMode]>;
254 //===----------------------------------------------------------------------===//
255 // 64-bit SPR manipulation instrs.
257 let Uses = [CTR8] in {
258 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
259 "mfctr $rT", SprMFSPR>,
260 PPC970_DGroup_First, PPC970_Unit_FXU;
262 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in {
263 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
264 "mtctr $rS", SprMTSPR>,
265 PPC970_DGroup_First, PPC970_Unit_FXU;
268 let Pattern = [(set G8RC:$rT, readcyclecounter)] in
269 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
270 "mfspr $rT, 268", SprMFTB>,
271 PPC970_DGroup_First, PPC970_Unit_FXU;
272 // Note that encoding mftb using mfspr is now the preferred form,
273 // and has been since at least ISA v2.03. The mftb instruction has
274 // now been phased out. Using mfspr, however, is known not to work on
277 let Defs = [X1], Uses = [X1] in
278 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
280 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
282 let Defs = [LR8] in {
283 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
284 "mtlr $rS", SprMTSPR>,
285 PPC970_DGroup_First, PPC970_Unit_FXU;
287 let Uses = [LR8] in {
288 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
289 "mflr $rT", SprMFSPR>,
290 PPC970_DGroup_First, PPC970_Unit_FXU;
293 //===----------------------------------------------------------------------===//
294 // Fixed point instructions.
297 let PPC970_Unit = 1 in { // FXU Operations.
299 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
300 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
301 "li $rD, $imm", IntSimple,
302 [(set G8RC:$rD, immSExt16:$imm)]>;
303 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
304 "lis $rD, $imm", IntSimple,
305 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
309 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
310 "nand $rA, $rS, $rB", IntSimple,
311 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
312 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
313 "and $rA, $rS, $rB", IntSimple,
314 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
315 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
316 "andc $rA, $rS, $rB", IntSimple,
317 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
318 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
319 "or $rA, $rS, $rB", IntSimple,
320 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
321 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
322 "nor $rA, $rS, $rB", IntSimple,
323 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
324 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
325 "orc $rA, $rS, $rB", IntSimple,
326 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
327 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
328 "eqv $rA, $rS, $rB", IntSimple,
329 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
330 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
331 "xor $rA, $rS, $rB", IntSimple,
332 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
334 // Logical ops with immediate.
335 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
336 "andi. $dst, $src1, $src2", IntGeneral,
337 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
339 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
340 "andis. $dst, $src1, $src2", IntGeneral,
341 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
343 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
344 "ori $dst, $src1, $src2", IntSimple,
345 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
346 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
347 "oris $dst, $src1, $src2", IntSimple,
348 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
349 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
350 "xori $dst, $src1, $src2", IntSimple,
351 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
352 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
353 "xoris $dst, $src1, $src2", IntSimple,
354 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
356 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
357 "add $rT, $rA, $rB", IntSimple,
358 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
359 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
360 // initial-exec thread-local storage model.
361 def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB),
362 "add $rT, $rA, $rB@tls", IntSimple,
363 [(set G8RC:$rT, (add G8RC:$rA, tglobaltlsaddr:$rB))]>;
365 let Defs = [CARRY] in {
366 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
367 "addc $rT, $rA, $rB", IntGeneral,
368 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
369 PPC970_DGroup_Cracked;
370 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
371 "addic $rD, $rA, $imm", IntGeneral,
372 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
374 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, s16imm64:$imm),
375 "addi $rD, $rA, $imm", IntSimple,
376 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>;
377 def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm),
378 "addi $rD, $rA, $imm", IntSimple,
379 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>;
380 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm),
381 "addis $rD, $rA, $imm", IntSimple,
382 [(set G8RC:$rD, (add G8RC_NOX0:$rA,
383 imm16ShiftedSExt:$imm))]>;
385 let Defs = [CARRY] in {
386 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
387 "subfic $rD, $rA, $imm", IntGeneral,
388 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
389 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
390 "subfc $rT, $rA, $rB", IntGeneral,
391 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
392 PPC970_DGroup_Cracked;
394 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
395 "subf $rT, $rA, $rB", IntGeneral,
396 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
397 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
398 "neg $rT, $rA", IntSimple,
399 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
400 let Uses = [CARRY], Defs = [CARRY] in {
401 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
402 "adde $rT, $rA, $rB", IntGeneral,
403 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
404 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
405 "addme $rT, $rA", IntGeneral,
406 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>;
407 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
408 "addze $rT, $rA", IntGeneral,
409 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
410 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
411 "subfe $rT, $rA, $rB", IntGeneral,
412 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
413 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
414 "subfme $rT, $rA", IntGeneral,
415 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>;
416 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
417 "subfze $rT, $rA", IntGeneral,
418 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
422 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
423 "mulhd $rT, $rA, $rB", IntMulHW,
424 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
425 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
426 "mulhdu $rT, $rA, $rB", IntMulHWU,
427 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
429 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
430 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
431 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
432 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
433 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
434 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
435 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
436 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
438 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
439 "sld $rA, $rS, $rB", IntRotateD,
440 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
441 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
442 "srd $rA, $rS, $rB", IntRotateD,
443 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
444 let Defs = [CARRY] in {
445 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
446 "srad $rA, $rS, $rB", IntRotateD,
447 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
450 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
451 "extsb $rA, $rS", IntSimple,
452 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
453 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
454 "extsh $rA, $rS", IntSimple,
455 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
457 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
458 "extsw $rA, $rS", IntSimple,
459 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
460 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
461 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
462 "extsw $rA, $rS", IntSimple,
463 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
464 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
465 "extsw $rA, $rS", IntSimple,
466 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
468 let Defs = [CARRY] in {
469 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
470 "sradi $rA, $rS, $SH", IntRotateDI,
471 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
473 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
474 "cntlzd $rA, $rS", IntGeneral,
475 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
477 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
478 "divd $rT, $rA, $rB", IntDivD,
479 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
480 PPC970_DGroup_First, PPC970_DGroup_Cracked;
481 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
482 "divdu $rT, $rA, $rB", IntDivD,
483 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
484 PPC970_DGroup_First, PPC970_DGroup_Cracked;
485 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
486 "mulld $rT, $rA, $rB", IntMulHD,
487 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
490 let isCommutable = 1 in {
491 def RLDIMI : MDForm_1<30, 3,
492 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
493 "rldimi $rA, $rS, $SH, $MB", IntRotateDI,
494 []>, isPPC64, RegConstraint<"$rSi = $rA">,
498 // Rotate instructions.
499 def RLDCL : MDForm_1<30, 0,
500 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
501 "rldcl $rA, $rS, $rB, $MBE", IntRotateD,
503 def RLDICL : MDForm_1<30, 0,
504 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
505 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
507 def RLDICR : MDForm_1<30, 1,
508 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
509 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI,
512 def RLWINM8 : MForm_2<21,
513 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
514 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
517 def ISEL8 : AForm_4<31, 15,
518 (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, pred:$cond),
519 "isel $rT, $rA, $rB, $cond", IntGeneral,
521 } // End FXU Operations.
524 //===----------------------------------------------------------------------===//
525 // Load/Store instructions.
529 // Sign extending loads.
530 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
531 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
532 "lha $rD, $src", LdStLHA,
533 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
534 PPC970_DGroup_Cracked;
535 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
536 "lwa $rD, $src", LdStLWA,
538 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
539 PPC970_DGroup_Cracked;
540 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
541 "lhax $rD, $src", LdStLHA,
542 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
543 PPC970_DGroup_Cracked;
544 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
545 "lwax $rD, $src", LdStLHA,
546 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
547 PPC970_DGroup_Cracked;
551 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
553 "lhau $rD, $addr", LdStLHAU,
554 []>, RegConstraint<"$addr.reg = $ea_result">,
555 NoEncode<"$ea_result">;
558 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
560 "lhaux $rD, $addr", LdStLHAU,
561 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
562 NoEncode<"$ea_result">;
563 def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
565 "lwaux $rD, $addr", LdStLHAU,
566 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
567 NoEncode<"$ea_result">, isPPC64;
571 // Zero extending loads.
572 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
573 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
574 "lbz $rD, $src", LdStLoad,
575 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
576 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
577 "lhz $rD, $src", LdStLoad,
578 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
579 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
580 "lwz $rD, $src", LdStLoad,
581 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
583 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
584 "lbzx $rD, $src", LdStLoad,
585 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
586 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
587 "lhzx $rD, $src", LdStLoad,
588 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
589 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
590 "lwzx $rD, $src", LdStLoad,
591 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
596 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
597 "lbzu $rD, $addr", LdStLoadUpd,
598 []>, RegConstraint<"$addr.reg = $ea_result">,
599 NoEncode<"$ea_result">;
600 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
601 "lhzu $rD, $addr", LdStLoadUpd,
602 []>, RegConstraint<"$addr.reg = $ea_result">,
603 NoEncode<"$ea_result">;
604 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
605 "lwzu $rD, $addr", LdStLoadUpd,
606 []>, RegConstraint<"$addr.reg = $ea_result">,
607 NoEncode<"$ea_result">;
609 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
611 "lbzux $rD, $addr", LdStLoadUpd,
612 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
613 NoEncode<"$ea_result">;
614 def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
616 "lhzux $rD, $addr", LdStLoadUpd,
617 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
618 NoEncode<"$ea_result">;
619 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
621 "lwzux $rD, $addr", LdStLoadUpd,
622 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
623 NoEncode<"$ea_result">;
628 // Full 8-byte loads.
629 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
630 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
631 "ld $rD, $src", LdStLD,
632 [(set G8RC:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
633 def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src),
634 "ld $rD, $src", LdStLD,
636 // The following three definitions are selected for small code model only.
637 // Otherwise, we need to create two instructions to form a 32-bit offset,
638 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
639 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
642 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
643 def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
646 (PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64;
647 def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
650 (PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64;
652 let hasSideEffects = 1 in {
653 let RST = 2, DS = 2 in
654 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
655 "ld 2, 8($reg)", LdStLD,
656 [(PPCload_toc G8RC:$reg)]>, isPPC64;
658 let RST = 2, DS = 10, RA = 1 in
659 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
660 "ld 2, 40(1)", LdStLD,
661 [(PPCtoc_restore)]>, isPPC64;
663 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
664 "ldx $rD, $src", LdStLD,
665 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
668 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
669 "ldu $rD, $addr", LdStLDU,
670 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
671 NoEncode<"$ea_result">;
673 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
675 "ldux $rD, $addr", LdStLDU,
676 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
677 NoEncode<"$ea_result">, isPPC64;
680 def : Pat<(PPCload ixaddr:$src),
682 def : Pat<(PPCload xaddr:$src),
685 // Support for medium and large code model.
686 def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
689 (PPCaddisTocHA G8RC:$reg, tglobaladdr:$disp))]>,
691 def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
694 (PPCldTocL tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
695 def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
698 (PPCaddiTocL G8RC:$reg, tglobaladdr:$disp))]>, isPPC64;
700 // Support for thread-local storage.
701 def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
704 (PPCaddisGotTprelHA G8RC:$reg,
705 tglobaltlsaddr:$disp))]>,
707 def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg),
710 (PPCldGotTprelL tglobaltlsaddr:$disp, G8RC:$reg))]>,
712 def : Pat<(PPCaddTls G8RC:$in, tglobaltlsaddr:$g),
713 (ADD8TLS G8RC:$in, tglobaltlsaddr:$g)>;
714 def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
717 (PPCaddisTlsgdHA G8RC:$reg, tglobaltlsaddr:$disp))]>,
719 def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
722 (PPCaddiTlsgdL G8RC:$reg, tglobaltlsaddr:$disp))]>,
724 def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
727 (PPCgetTlsAddr G8RC:$reg, tglobaltlsaddr:$sym))]>,
729 def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
732 (PPCaddisTlsldHA G8RC:$reg, tglobaltlsaddr:$disp))]>,
734 def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
737 (PPCaddiTlsldL G8RC:$reg, tglobaltlsaddr:$disp))]>,
739 def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
742 (PPCgetTlsldAddr G8RC:$reg, tglobaltlsaddr:$sym))]>,
744 def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
747 (PPCaddisDtprelHA G8RC:$reg,
748 tglobaltlsaddr:$disp))]>,
750 def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
753 (PPCaddiDtprelL G8RC:$reg, tglobaltlsaddr:$disp))]>,
756 let PPC970_Unit = 2 in {
757 // Truncating stores.
758 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
759 "stb $rS, $src", LdStStore,
760 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
761 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
762 "sth $rS, $src", LdStStore,
763 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
764 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
765 "stw $rS, $src", LdStStore,
766 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
767 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
768 "stbx $rS, $dst", LdStStore,
769 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
770 PPC970_DGroup_Cracked;
771 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
772 "sthx $rS, $dst", LdStStore,
773 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
774 PPC970_DGroup_Cracked;
775 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
776 "stwx $rS, $dst", LdStStore,
777 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
778 PPC970_DGroup_Cracked;
779 // Normal 8-byte stores.
780 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
781 "std $rS, $dst", LdStSTD,
782 [(aligned4store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
783 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
784 "stdx $rS, $dst", LdStSTD,
785 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
786 PPC970_DGroup_Cracked;
787 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
788 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
789 "std $rT, $dst", LdStSTD,
790 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
791 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
792 "stdx $rT, $dst", LdStSTD,
793 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
794 PPC970_DGroup_Cracked;
797 // Stores with Update (pre-inc).
798 let PPC970_Unit = 2, mayStore = 1 in {
799 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
800 "stbu $rS, $dst", LdStStoreUpd, []>,
801 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
802 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
803 "sthu $rS, $dst", LdStStoreUpd, []>,
804 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
805 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
806 "stwu $rS, $dst", LdStStoreUpd, []>,
807 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
808 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst),
809 "stdu $rS, $dst", LdStSTDU, []>,
810 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
813 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
814 "stbux $rS, $dst", LdStStoreUpd, []>,
815 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
816 PPC970_DGroup_Cracked;
817 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
818 "sthux $rS, $dst", LdStStoreUpd, []>,
819 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
820 PPC970_DGroup_Cracked;
821 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
822 "stwux $rS, $dst", LdStStoreUpd, []>,
823 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
824 PPC970_DGroup_Cracked;
825 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
826 "stdux $rS, $dst", LdStSTDU, []>,
827 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
828 PPC970_DGroup_Cracked, isPPC64;
831 // Patterns to match the pre-inc stores. We can't put the patterns on
832 // the instruction definitions directly as ISel wants the address base
833 // and offset to be separate operands, not a single complex operand.
834 def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
835 (STBU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
836 def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
837 (STHU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
838 def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
839 (STWU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
840 def : Pat<(aligned4pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
841 (STDU G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
843 def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
844 (STBUX8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
845 def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
846 (STHUX8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
847 def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
848 (STWUX8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
849 def : Pat<(pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
850 (STDUX G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
853 //===----------------------------------------------------------------------===//
854 // Floating point instructions.
858 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
859 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
860 "fcfid $frD, $frB", FPGeneral,
861 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
862 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
863 "fctidz $frD, $frB", FPGeneral,
864 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
868 //===----------------------------------------------------------------------===//
869 // Instruction Patterns
872 // Extensions and truncates to/from 32-bit regs.
873 def : Pat<(i64 (zext GPRC:$in)),
874 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32),
876 def : Pat<(i64 (anyext GPRC:$in)),
877 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>;
878 def : Pat<(i32 (trunc G8RC:$in)),
879 (EXTRACT_SUBREG G8RC:$in, sub_32)>;
881 // Extending loads with i64 targets.
882 def : Pat<(zextloadi1 iaddr:$src),
884 def : Pat<(zextloadi1 xaddr:$src),
886 def : Pat<(extloadi1 iaddr:$src),
888 def : Pat<(extloadi1 xaddr:$src),
890 def : Pat<(extloadi8 iaddr:$src),
892 def : Pat<(extloadi8 xaddr:$src),
894 def : Pat<(extloadi16 iaddr:$src),
896 def : Pat<(extloadi16 xaddr:$src),
898 def : Pat<(extloadi32 iaddr:$src),
900 def : Pat<(extloadi32 xaddr:$src),
903 // Standard shifts. These are represented separately from the real shifts above
904 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
906 def : Pat<(sra G8RC:$rS, GPRC:$rB),
907 (SRAD G8RC:$rS, GPRC:$rB)>;
908 def : Pat<(srl G8RC:$rS, GPRC:$rB),
909 (SRD G8RC:$rS, GPRC:$rB)>;
910 def : Pat<(shl G8RC:$rS, GPRC:$rB),
911 (SLD G8RC:$rS, GPRC:$rB)>;
914 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
915 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
916 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
917 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
920 def : Pat<(rotl G8RC:$in, GPRC:$sh),
921 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
922 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
923 (RLDICL G8RC:$in, imm:$imm, 0)>;
925 // Hi and Lo for Darwin Global Addresses.
926 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
927 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
928 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
929 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
930 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
931 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
932 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
933 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
934 def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in),
935 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>;
936 def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in),
937 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>;
938 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
939 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
940 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
941 (ADDIS8 G8RC:$in, tconstpool:$g)>;
942 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
943 (ADDIS8 G8RC:$in, tjumptable:$g)>;
944 def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
945 (ADDIS8 G8RC:$in, tblockaddress:$g)>;
947 // Patterns to match r+r indexed loads and stores for
948 // addresses without at least 4-byte alignment.
949 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
951 def : Pat<(i64 (unaligned4load xoaddr:$src)),
953 def : Pat<(unaligned4store G8RC:$rS, xoaddr:$dst),
954 (STDX G8RC:$rS, xoaddr:$dst)>;