1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
32 def tocentry : Operand<iPTR> {
33 let MIOperandInfo = (ops i64imm:$imm);
35 def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64
36 let PrintMethod = "printMemRegImm";
37 let EncoderMethod = "getMemRIXEncoding";
38 let MIOperandInfo = (ops symbolLo64:$off, ptr_rc_nor0:$reg);
40 def tlsreg : Operand<i64> {
41 let EncoderMethod = "getTLSRegEncoding";
43 def tlsgd : Operand<i64> {}
45 //===----------------------------------------------------------------------===//
46 // 64-bit transformation functions.
49 def SHL64 : SDNodeXForm<imm, [{
50 // Transformation function: 63 - imm
51 return getI32Imm(63 - N->getZExtValue());
54 def SRL64 : SDNodeXForm<imm, [{
55 // Transformation function: 64 - imm
56 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
59 def HI32_48 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
64 def HI48_64 : SDNodeXForm<imm, [{
65 // Transformation function: shift the immediate value down into the low bits.
66 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
70 //===----------------------------------------------------------------------===//
75 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
79 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
80 // Convenient aliases for call instructions
82 def BL8_Darwin : IForm<18, 0, 1,
83 (outs), (ins calltarget:$func),
84 "bl $func", BrB, []>; // See Pat patterns below.
85 def BLA8_Darwin : IForm<18, 1, 1,
86 (outs), (ins aaddr:$func),
87 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>;
89 let Uses = [CTR8, RM] in {
90 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
93 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>;
97 // ELF 64 ABI Calls = Darwin ABI Calls
98 // Used to define BL8_ELF and BLA8_ELF
99 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
100 // Convenient aliases for call instructions
102 def BL8_ELF : IForm<18, 0, 1,
103 (outs), (ins calltarget:$func),
104 "bl $func", BrB, []>; // See Pat patterns below.
106 let isCodeGenOnly = 1 in
107 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24,
108 (outs), (ins calltarget:$func),
109 "bl $func\n\tnop", BrB, []>;
111 let isCodeGenOnly = 1 in
112 def BL8_NOP_ELF_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
113 (outs), (ins calltarget:$func, tlsgd:$sym),
114 "bl $func($sym)\n\tnop", BrB, []>;
116 let isCodeGenOnly = 1 in
117 def BL8_NOP_ELF_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
118 (outs), (ins calltarget:$func, tlsgd:$sym),
119 "bl $func($sym)\n\tnop", BrB, []>;
121 def BLA8_ELF : IForm<18, 1, 1,
122 (outs), (ins aaddr:$func),
123 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>;
125 let isCodeGenOnly = 1 in
126 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24,
127 (outs), (ins aaddr:$func),
128 "bla $func\n\tnop", BrB,
129 [(PPCcall_nop_SVR4 (i64 imm:$func))]>;
131 let Uses = [X11, CTR8, RM] in {
132 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
135 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>;
141 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
142 (BL8_Darwin tglobaladdr:$dst)>;
143 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
144 (BL8_Darwin texternalsym:$dst)>;
146 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
147 (BL8_ELF tglobaladdr:$dst)>;
148 def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)),
149 (BL8_NOP_ELF tglobaladdr:$dst)>;
151 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
152 (BL8_ELF texternalsym:$dst)>;
153 def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)),
154 (BL8_NOP_ELF texternalsym:$dst)>;
160 let usesCustomInserter = 1 in {
161 let Defs = [CR0] in {
162 def ATOMIC_LOAD_ADD_I64 : Pseudo<
163 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
164 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
165 def ATOMIC_LOAD_SUB_I64 : Pseudo<
166 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
167 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
168 def ATOMIC_LOAD_OR_I64 : Pseudo<
169 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
170 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
171 def ATOMIC_LOAD_XOR_I64 : Pseudo<
172 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
173 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
174 def ATOMIC_LOAD_AND_I64 : Pseudo<
175 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
176 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
177 def ATOMIC_LOAD_NAND_I64 : Pseudo<
178 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
179 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
181 def ATOMIC_CMP_SWAP_I64 : Pseudo<
182 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
184 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
186 def ATOMIC_SWAP_I64 : Pseudo<
187 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
188 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
192 // Instructions to support atomic operations
193 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
194 "ldarx $rD, $ptr", LdStLDARX,
195 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
198 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
199 "stdcx. $rS, $dst", LdStSTDCX,
200 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
203 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
204 def TCRETURNdi8 :Pseudo< (outs),
205 (ins calltarget:$dst, i32imm:$offset),
206 "#TC_RETURNd8 $dst $offset",
209 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
210 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
211 "#TC_RETURNa8 $func $offset",
212 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
214 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
215 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
216 "#TC_RETURNr8 $dst $offset",
220 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
221 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in {
222 let isReturn = 1 in {
223 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
224 Requires<[In64BitMode]>;
227 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
228 Requires<[In64BitMode]>;
232 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
233 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
234 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
239 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
240 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
241 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
245 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
246 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
248 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
249 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
251 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
252 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
254 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
255 let Defs = [CTR8], Uses = [CTR8] in {
256 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
258 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
263 // 64-but CR instructions
264 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
265 "mtcrf $FXM, $rS", BrMCRX>,
266 PPC970_MicroCode, PPC970_Unit_CRU;
268 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
269 "#MFCR8pseud", SprMFCR>,
270 PPC970_MicroCode, PPC970_Unit_CRU;
272 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
273 "mfcr $rT", SprMFCR>,
274 PPC970_MicroCode, PPC970_Unit_CRU;
276 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
277 usesCustomInserter = 1 in {
278 def EH_SjLj_SetJmp64 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
280 [(set GPRC:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
281 Requires<[In64BitMode]>;
282 let isTerminator = 1 in
283 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
284 "#EH_SJLJ_LONGJMP64",
285 [(PPCeh_sjlj_longjmp addr:$buf)]>,
286 Requires<[In64BitMode]>;
289 //===----------------------------------------------------------------------===//
290 // 64-bit SPR manipulation instrs.
292 let Uses = [CTR8] in {
293 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
294 "mfctr $rT", SprMFSPR>,
295 PPC970_DGroup_First, PPC970_Unit_FXU;
297 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in {
298 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
299 "mtctr $rS", SprMTSPR>,
300 PPC970_DGroup_First, PPC970_Unit_FXU;
303 let Pattern = [(set G8RC:$rT, readcyclecounter)] in
304 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
305 "mfspr $rT, 268", SprMFTB>,
306 PPC970_DGroup_First, PPC970_Unit_FXU;
307 // Note that encoding mftb using mfspr is now the preferred form,
308 // and has been since at least ISA v2.03. The mftb instruction has
309 // now been phased out. Using mfspr, however, is known not to work on
312 let Defs = [X1], Uses = [X1] in
313 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
315 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
317 let Defs = [LR8] in {
318 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
319 "mtlr $rS", SprMTSPR>,
320 PPC970_DGroup_First, PPC970_Unit_FXU;
322 let Uses = [LR8] in {
323 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
324 "mflr $rT", SprMFSPR>,
325 PPC970_DGroup_First, PPC970_Unit_FXU;
328 //===----------------------------------------------------------------------===//
329 // Fixed point instructions.
332 let PPC970_Unit = 1 in { // FXU Operations.
334 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
335 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
336 "li $rD, $imm", IntSimple,
337 [(set G8RC:$rD, immSExt16:$imm)]>;
338 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
339 "lis $rD, $imm", IntSimple,
340 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
344 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
345 "nand $rA, $rS, $rB", IntSimple,
346 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
347 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
348 "and $rA, $rS, $rB", IntSimple,
349 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
350 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
351 "andc $rA, $rS, $rB", IntSimple,
352 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
353 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
354 "or $rA, $rS, $rB", IntSimple,
355 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
356 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
357 "nor $rA, $rS, $rB", IntSimple,
358 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
359 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
360 "orc $rA, $rS, $rB", IntSimple,
361 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
362 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
363 "eqv $rA, $rS, $rB", IntSimple,
364 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
365 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
366 "xor $rA, $rS, $rB", IntSimple,
367 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
369 // Logical ops with immediate.
370 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
371 "andi. $dst, $src1, $src2", IntGeneral,
372 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
374 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
375 "andis. $dst, $src1, $src2", IntGeneral,
376 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
378 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
379 "ori $dst, $src1, $src2", IntSimple,
380 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
381 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
382 "oris $dst, $src1, $src2", IntSimple,
383 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
384 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
385 "xori $dst, $src1, $src2", IntSimple,
386 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
387 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
388 "xoris $dst, $src1, $src2", IntSimple,
389 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
391 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
392 "add $rT, $rA, $rB", IntSimple,
393 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
394 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
395 // initial-exec thread-local storage model.
396 def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB),
397 "add $rT, $rA, $rB@tls", IntSimple,
398 [(set G8RC:$rT, (add G8RC:$rA, tglobaltlsaddr:$rB))]>;
400 let Defs = [CARRY] in {
401 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
402 "addc $rT, $rA, $rB", IntGeneral,
403 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
404 PPC970_DGroup_Cracked;
405 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
406 "addic $rD, $rA, $imm", IntGeneral,
407 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
409 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, s16imm64:$imm),
410 "addi $rD, $rA, $imm", IntSimple,
411 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>;
412 def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm),
413 "addi $rD, $rA, $imm", IntSimple,
414 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>;
415 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm),
416 "addis $rD, $rA, $imm", IntSimple,
417 [(set G8RC:$rD, (add G8RC_NOX0:$rA,
418 imm16ShiftedSExt:$imm))]>;
420 let Defs = [CARRY] in {
421 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
422 "subfic $rD, $rA, $imm", IntGeneral,
423 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
424 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
425 "subfc $rT, $rA, $rB", IntGeneral,
426 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
427 PPC970_DGroup_Cracked;
429 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
430 "subf $rT, $rA, $rB", IntGeneral,
431 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
432 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
433 "neg $rT, $rA", IntSimple,
434 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
435 let Uses = [CARRY], Defs = [CARRY] in {
436 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
437 "adde $rT, $rA, $rB", IntGeneral,
438 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
439 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
440 "addme $rT, $rA", IntGeneral,
441 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>;
442 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
443 "addze $rT, $rA", IntGeneral,
444 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
445 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
446 "subfe $rT, $rA, $rB", IntGeneral,
447 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
448 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
449 "subfme $rT, $rA", IntGeneral,
450 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>;
451 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
452 "subfze $rT, $rA", IntGeneral,
453 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
457 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
458 "mulhd $rT, $rA, $rB", IntMulHW,
459 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
460 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
461 "mulhdu $rT, $rA, $rB", IntMulHWU,
462 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
464 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
465 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
466 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
467 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
468 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
469 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
470 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
471 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
473 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
474 "sld $rA, $rS, $rB", IntRotateD,
475 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
476 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
477 "srd $rA, $rS, $rB", IntRotateD,
478 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
479 let Defs = [CARRY] in {
480 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
481 "srad $rA, $rS, $rB", IntRotateD,
482 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
485 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
486 "extsb $rA, $rS", IntSimple,
487 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
488 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
489 "extsh $rA, $rS", IntSimple,
490 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
492 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
493 "extsw $rA, $rS", IntSimple,
494 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
495 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
496 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
497 "extsw $rA, $rS", IntSimple,
498 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
499 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
500 "extsw $rA, $rS", IntSimple,
501 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
503 let Defs = [CARRY] in {
504 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
505 "sradi $rA, $rS, $SH", IntRotateDI,
506 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
508 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
509 "cntlzd $rA, $rS", IntGeneral,
510 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
512 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
513 "divd $rT, $rA, $rB", IntDivD,
514 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
515 PPC970_DGroup_First, PPC970_DGroup_Cracked;
516 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
517 "divdu $rT, $rA, $rB", IntDivD,
518 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
519 PPC970_DGroup_First, PPC970_DGroup_Cracked;
520 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
521 "mulld $rT, $rA, $rB", IntMulHD,
522 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
525 let isCommutable = 1 in {
526 def RLDIMI : MDForm_1<30, 3,
527 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
528 "rldimi $rA, $rS, $SH, $MB", IntRotateDI,
529 []>, isPPC64, RegConstraint<"$rSi = $rA">,
533 // Rotate instructions.
534 def RLDCL : MDForm_1<30, 0,
535 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
536 "rldcl $rA, $rS, $rB, $MBE", IntRotateD,
538 def RLDICL : MDForm_1<30, 0,
539 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
540 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
542 def RLDICR : MDForm_1<30, 1,
543 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
544 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI,
547 def RLWINM8 : MForm_2<21,
548 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
549 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
552 def ISEL8 : AForm_4<31, 15,
553 (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, pred:$cond),
554 "isel $rT, $rA, $rB, $cond", IntGeneral,
556 } // End FXU Operations.
559 //===----------------------------------------------------------------------===//
560 // Load/Store instructions.
564 // Sign extending loads.
565 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
566 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
567 "lha $rD, $src", LdStLHA,
568 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
569 PPC970_DGroup_Cracked;
570 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
571 "lwa $rD, $src", LdStLWA,
573 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
574 PPC970_DGroup_Cracked;
575 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
576 "lhax $rD, $src", LdStLHA,
577 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
578 PPC970_DGroup_Cracked;
579 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
580 "lwax $rD, $src", LdStLHA,
581 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
582 PPC970_DGroup_Cracked;
586 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
588 "lhau $rD, $addr", LdStLHAU,
589 []>, RegConstraint<"$addr.reg = $ea_result">,
590 NoEncode<"$ea_result">;
593 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
595 "lhaux $rD, $addr", LdStLHAU,
596 []>, RegConstraint<"$addr.offreg = $ea_result">,
597 NoEncode<"$ea_result">;
598 def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
600 "lwaux $rD, $addr", LdStLHAU,
601 []>, RegConstraint<"$addr.offreg = $ea_result">,
602 NoEncode<"$ea_result">, isPPC64;
606 // Zero extending loads.
607 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
608 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
609 "lbz $rD, $src", LdStLoad,
610 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
611 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
612 "lhz $rD, $src", LdStLoad,
613 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
614 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
615 "lwz $rD, $src", LdStLoad,
616 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
618 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
619 "lbzx $rD, $src", LdStLoad,
620 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
621 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
622 "lhzx $rD, $src", LdStLoad,
623 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
624 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
625 "lwzx $rD, $src", LdStLoad,
626 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
631 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
632 "lbzu $rD, $addr", LdStLoadUpd,
633 []>, RegConstraint<"$addr.reg = $ea_result">,
634 NoEncode<"$ea_result">;
635 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
636 "lhzu $rD, $addr", LdStLoadUpd,
637 []>, RegConstraint<"$addr.reg = $ea_result">,
638 NoEncode<"$ea_result">;
639 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
640 "lwzu $rD, $addr", LdStLoadUpd,
641 []>, RegConstraint<"$addr.reg = $ea_result">,
642 NoEncode<"$ea_result">;
644 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
646 "lbzux $rD, $addr", LdStLoadUpd,
647 []>, RegConstraint<"$addr.offreg = $ea_result">,
648 NoEncode<"$ea_result">;
649 def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
651 "lhzux $rD, $addr", LdStLoadUpd,
652 []>, RegConstraint<"$addr.offreg = $ea_result">,
653 NoEncode<"$ea_result">;
654 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
656 "lwzux $rD, $addr", LdStLoadUpd,
657 []>, RegConstraint<"$addr.offreg = $ea_result">,
658 NoEncode<"$ea_result">;
663 // Full 8-byte loads.
664 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
665 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
666 "ld $rD, $src", LdStLD,
667 [(set G8RC:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
668 def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src),
669 "ld $rD, $src", LdStLD,
671 // The following three definitions are selected for small code model only.
672 // Otherwise, we need to create two instructions to form a 32-bit offset,
673 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
674 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
677 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
678 def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
681 (PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64;
682 def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
685 (PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64;
687 let hasSideEffects = 1 in {
688 let RST = 2, DS = 2 in
689 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
690 "ld 2, 8($reg)", LdStLD,
691 [(PPCload_toc G8RC:$reg)]>, isPPC64;
693 let RST = 2, DS = 10, RA = 1 in
694 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
695 "ld 2, 40(1)", LdStLD,
696 [(PPCtoc_restore)]>, isPPC64;
698 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
699 "ldx $rD, $src", LdStLD,
700 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
703 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
704 "ldu $rD, $addr", LdStLDU,
705 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
706 NoEncode<"$ea_result">;
708 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
710 "ldux $rD, $addr", LdStLDU,
711 []>, RegConstraint<"$addr.offreg = $ea_result">,
712 NoEncode<"$ea_result">, isPPC64;
715 def : Pat<(PPCload ixaddr:$src),
717 def : Pat<(PPCload xaddr:$src),
720 // Support for medium and large code model.
721 def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
724 (PPCaddisTocHA G8RC:$reg, tglobaladdr:$disp))]>,
726 def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
729 (PPCldTocL tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
730 def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
733 (PPCaddiTocL G8RC:$reg, tglobaladdr:$disp))]>, isPPC64;
735 // Support for thread-local storage.
736 def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
739 (PPCaddisGotTprelHA G8RC:$reg,
740 tglobaltlsaddr:$disp))]>,
742 def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg),
745 (PPCldGotTprelL tglobaltlsaddr:$disp, G8RC:$reg))]>,
747 def : Pat<(PPCaddTls G8RC:$in, tglobaltlsaddr:$g),
748 (ADD8TLS G8RC:$in, tglobaltlsaddr:$g)>;
749 def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
752 (PPCaddisTlsgdHA G8RC:$reg, tglobaltlsaddr:$disp))]>,
754 def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
757 (PPCaddiTlsgdL G8RC:$reg, tglobaltlsaddr:$disp))]>,
759 def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
762 (PPCgetTlsAddr G8RC:$reg, tglobaltlsaddr:$sym))]>,
764 def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
767 (PPCaddisTlsldHA G8RC:$reg, tglobaltlsaddr:$disp))]>,
769 def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
772 (PPCaddiTlsldL G8RC:$reg, tglobaltlsaddr:$disp))]>,
774 def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
777 (PPCgetTlsldAddr G8RC:$reg, tglobaltlsaddr:$sym))]>,
779 def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
782 (PPCaddisDtprelHA G8RC:$reg,
783 tglobaltlsaddr:$disp))]>,
785 def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
788 (PPCaddiDtprelL G8RC:$reg, tglobaltlsaddr:$disp))]>,
791 let PPC970_Unit = 2 in {
792 // Truncating stores.
793 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
794 "stb $rS, $src", LdStStore,
795 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
796 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
797 "sth $rS, $src", LdStStore,
798 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
799 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
800 "stw $rS, $src", LdStStore,
801 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
802 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
803 "stbx $rS, $dst", LdStStore,
804 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
805 PPC970_DGroup_Cracked;
806 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
807 "sthx $rS, $dst", LdStStore,
808 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
809 PPC970_DGroup_Cracked;
810 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
811 "stwx $rS, $dst", LdStStore,
812 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
813 PPC970_DGroup_Cracked;
814 // Normal 8-byte stores.
815 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
816 "std $rS, $dst", LdStSTD,
817 [(aligned4store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
818 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
819 "stdx $rS, $dst", LdStSTD,
820 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
821 PPC970_DGroup_Cracked;
822 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
823 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
824 "std $rT, $dst", LdStSTD,
825 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
826 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
827 "stdx $rT, $dst", LdStSTD,
828 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
829 PPC970_DGroup_Cracked;
832 // Stores with Update (pre-inc).
833 let PPC970_Unit = 2, mayStore = 1 in {
834 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
835 "stbu $rS, $dst", LdStStoreUpd, []>,
836 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
837 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
838 "sthu $rS, $dst", LdStStoreUpd, []>,
839 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
840 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
841 "stwu $rS, $dst", LdStStoreUpd, []>,
842 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
843 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst),
844 "stdu $rS, $dst", LdStSTDU, []>,
845 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
848 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
849 "stbux $rS, $dst", LdStStoreUpd, []>,
850 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
851 PPC970_DGroup_Cracked;
852 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
853 "sthux $rS, $dst", LdStStoreUpd, []>,
854 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
855 PPC970_DGroup_Cracked;
856 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
857 "stwux $rS, $dst", LdStStoreUpd, []>,
858 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
859 PPC970_DGroup_Cracked;
860 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
861 "stdux $rS, $dst", LdStSTDU, []>,
862 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
863 PPC970_DGroup_Cracked, isPPC64;
866 // Patterns to match the pre-inc stores. We can't put the patterns on
867 // the instruction definitions directly as ISel wants the address base
868 // and offset to be separate operands, not a single complex operand.
869 def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
870 (STBU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
871 def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
872 (STHU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
873 def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
874 (STWU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
875 def : Pat<(aligned4pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
876 (STDU G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
878 def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
879 (STBUX8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
880 def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
881 (STHUX8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
882 def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
883 (STWUX8 G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
884 def : Pat<(pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
885 (STDUX G8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
888 //===----------------------------------------------------------------------===//
889 // Floating point instructions.
893 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
894 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
895 "fcfid $frD, $frB", FPGeneral,
896 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
897 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
898 "fctidz $frD, $frB", FPGeneral,
899 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
903 //===----------------------------------------------------------------------===//
904 // Instruction Patterns
907 // Extensions and truncates to/from 32-bit regs.
908 def : Pat<(i64 (zext GPRC:$in)),
909 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32),
911 def : Pat<(i64 (anyext GPRC:$in)),
912 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>;
913 def : Pat<(i32 (trunc G8RC:$in)),
914 (EXTRACT_SUBREG G8RC:$in, sub_32)>;
916 // Extending loads with i64 targets.
917 def : Pat<(zextloadi1 iaddr:$src),
919 def : Pat<(zextloadi1 xaddr:$src),
921 def : Pat<(extloadi1 iaddr:$src),
923 def : Pat<(extloadi1 xaddr:$src),
925 def : Pat<(extloadi8 iaddr:$src),
927 def : Pat<(extloadi8 xaddr:$src),
929 def : Pat<(extloadi16 iaddr:$src),
931 def : Pat<(extloadi16 xaddr:$src),
933 def : Pat<(extloadi32 iaddr:$src),
935 def : Pat<(extloadi32 xaddr:$src),
938 // Standard shifts. These are represented separately from the real shifts above
939 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
941 def : Pat<(sra G8RC:$rS, GPRC:$rB),
942 (SRAD G8RC:$rS, GPRC:$rB)>;
943 def : Pat<(srl G8RC:$rS, GPRC:$rB),
944 (SRD G8RC:$rS, GPRC:$rB)>;
945 def : Pat<(shl G8RC:$rS, GPRC:$rB),
946 (SLD G8RC:$rS, GPRC:$rB)>;
949 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
950 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
951 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
952 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
955 def : Pat<(rotl G8RC:$in, GPRC:$sh),
956 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
957 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
958 (RLDICL G8RC:$in, imm:$imm, 0)>;
960 // Hi and Lo for Darwin Global Addresses.
961 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
962 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
963 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
964 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
965 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
966 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
967 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
968 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
969 def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in),
970 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>;
971 def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in),
972 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>;
973 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
974 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
975 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
976 (ADDIS8 G8RC:$in, tconstpool:$g)>;
977 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
978 (ADDIS8 G8RC:$in, tjumptable:$g)>;
979 def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
980 (ADDIS8 G8RC:$in, tblockaddress:$g)>;
982 // Patterns to match r+r indexed loads and stores for
983 // addresses without at least 4-byte alignment.
984 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
986 def : Pat<(i64 (unaligned4load xoaddr:$src)),
988 def : Pat<(unaligned4store G8RC:$rS, xoaddr:$dst),
989 (STDX G8RC:$rS, xoaddr:$dst)>;