1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getZExtValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
56 //===----------------------------------------------------------------------===//
61 def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
65 let isCall = 1, PPC970_Unit = 7,
66 // All calls clobber the PPC64 non-callee saved registers.
67 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
68 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
69 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
71 CR0,CR1,CR5,CR6,CR7] in {
72 // Convenient aliases for call instructions
73 def BL8_Macho : IForm<18, 0, 1,
74 (outs), (ins calltarget:$func, variable_ops),
75 "bl $func", BrB, []>; // See Pat patterns below.
76 def BLA8_Macho : IForm<18, 1, 1,
77 (outs), (ins aaddr:$func, variable_ops),
78 "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
79 def BCTRL8_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
80 (outs), (ins variable_ops),
82 [(PPCbctrl_Macho)]>, Requires<[In64BitMode]>;
85 // ELF 64 ABI Calls = Macho ABI Calls
86 // Used to define BL8_ELF and BLA8_ELF
87 let isCall = 1, PPC970_Unit = 7,
88 // All calls clobber the PPC64 non-callee saved registers.
89 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
90 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
91 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
93 CR0,CR1,CR5,CR6,CR7] in {
94 // Convenient aliases for call instructions
95 def BL8_ELF : IForm<18, 0, 1,
96 (outs), (ins calltarget:$func, variable_ops),
97 "bl $func", BrB, []>; // See Pat patterns below.
98 def BLA8_ELF : IForm<18, 1, 1,
99 (outs), (ins aaddr:$func, variable_ops),
100 "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>;
101 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
102 (outs), (ins variable_ops),
104 [(PPCbctrl_ELF)]>, Requires<[In64BitMode]>;
109 def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)),
110 (BL8_Macho tglobaladdr:$dst)>;
111 def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)),
112 (BL8_Macho texternalsym:$dst)>;
114 def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
115 (BL8_ELF tglobaladdr:$dst)>;
116 def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
117 (BL8_ELF texternalsym:$dst)>;
120 let usesCustomDAGSchedInserter = 1 in {
121 let Uses = [CR0] in {
122 def ATOMIC_LOAD_ADD_I64 : Pseudo<
123 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
124 "${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!",
125 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
126 def ATOMIC_LOAD_SUB_I64 : Pseudo<
127 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
128 "${:comment} ATOMIC_LOAD_SUB_I64 PSEUDO!",
129 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
130 def ATOMIC_LOAD_OR_I64 : Pseudo<
131 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
132 "${:comment} ATOMIC_LOAD_OR_I64 PSEUDO!",
133 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
134 def ATOMIC_LOAD_XOR_I64 : Pseudo<
135 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
136 "${:comment} ATOMIC_LOAD_XOR_I64 PSEUDO!",
137 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
138 def ATOMIC_LOAD_AND_I64 : Pseudo<
139 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
140 "${:comment} ATOMIC_LOAD_AND_I64 PSEUDO!",
141 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
142 def ATOMIC_LOAD_NAND_I64 : Pseudo<
143 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
144 "${:comment} ATOMIC_LOAD_NAND_I64 PSEUDO!",
145 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
147 def ATOMIC_CMP_SWAP_I64 : Pseudo<
148 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
149 "${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
151 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
153 def ATOMIC_SWAP_I64 : Pseudo<
154 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
155 "${:comment} ATOMIC_SWAP_I64 PSEUDO!",
156 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
160 // Instructions to support atomic operations
161 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
162 "ldarx $rD, $ptr", LdStLDARX,
163 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
166 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
167 "stdcx. $rS, $dst", LdStSTDCX,
168 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
172 def TCRETURNdi8 :Pseudo< (outs),
173 (ins calltarget:$dst, i32imm:$offset, variable_ops),
174 "#TC_RETURNd8 $dst $offset",
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
179 "#TC_RETURNa8 $func $offset",
180 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
182 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
183 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops),
184 "#TC_RETURNr8 $dst $offset",
188 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
189 isIndirectBranch = 1, isCall = 1, isReturn = 1 in
190 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
191 Requires<[In64BitMode]>;
195 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
196 isBarrier = 1, isCall = 1, isReturn = 1 in
197 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
202 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
203 isBarrier = 1, isCall = 1, isReturn = 1 in
204 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
208 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
209 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
211 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
212 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
214 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
215 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
218 //===----------------------------------------------------------------------===//
219 // 64-bit SPR manipulation instrs.
221 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
222 "mfctr $rT", SprMFSPR>,
223 PPC970_DGroup_First, PPC970_Unit_FXU;
224 let Pattern = [(PPCmtctr G8RC:$rS)] in {
225 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
226 "mtctr $rS", SprMTSPR>,
227 PPC970_DGroup_First, PPC970_Unit_FXU;
230 let Defs = [X1], Uses = [X1] in
231 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),
232 "${:comment} DYNALLOC8 $result, $negsize, $fpsi",
234 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
236 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
237 "mtlr $rS", SprMTSPR>,
238 PPC970_DGroup_First, PPC970_Unit_FXU;
239 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
240 "mflr $rT", SprMFSPR>,
241 PPC970_DGroup_First, PPC970_Unit_FXU;
244 //===----------------------------------------------------------------------===//
245 // Fixed point instructions.
248 let PPC970_Unit = 1 in { // FXU Operations.
250 // Copies, extends, truncates.
251 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
252 "or $rA, $rS, $rB", IntGeneral,
254 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
255 "or $rA, $rS, $rB", IntGeneral,
258 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
259 "li $rD, $imm", IntGeneral,
260 [(set G8RC:$rD, immSExt16:$imm)]>;
261 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
262 "lis $rD, $imm", IntGeneral,
263 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
266 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
267 "nand $rA, $rS, $rB", IntGeneral,
268 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
269 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
270 "and $rA, $rS, $rB", IntGeneral,
271 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
272 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
273 "andc $rA, $rS, $rB", IntGeneral,
274 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
275 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
276 "or $rA, $rS, $rB", IntGeneral,
277 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
278 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
279 "nor $rA, $rS, $rB", IntGeneral,
280 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
281 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
282 "orc $rA, $rS, $rB", IntGeneral,
283 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
284 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
285 "eqv $rA, $rS, $rB", IntGeneral,
286 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
287 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
288 "xor $rA, $rS, $rB", IntGeneral,
289 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
291 // Logical ops with immediate.
292 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
293 "andi. $dst, $src1, $src2", IntGeneral,
294 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
296 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
297 "andis. $dst, $src1, $src2", IntGeneral,
298 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
300 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
301 "ori $dst, $src1, $src2", IntGeneral,
302 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
303 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
304 "oris $dst, $src1, $src2", IntGeneral,
305 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
306 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
307 "xori $dst, $src1, $src2", IntGeneral,
308 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
309 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
310 "xoris $dst, $src1, $src2", IntGeneral,
311 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
313 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
314 "add $rT, $rA, $rB", IntGeneral,
315 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
317 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
318 "addc $rT, $rA, $rB", IntGeneral,
319 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
320 PPC970_DGroup_Cracked;
321 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
322 "adde $rT, $rA, $rB", IntGeneral,
323 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
325 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
326 "addi $rD, $rA, $imm", IntGeneral,
327 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
328 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
329 "addis $rD, $rA, $imm", IntGeneral,
330 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
332 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
333 "subfic $rD, $rA, $imm", IntGeneral,
334 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
335 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
336 "subf $rT, $rA, $rB", IntGeneral,
337 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
338 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
339 "subfc $rT, $rA, $rB", IntGeneral,
340 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
341 PPC970_DGroup_Cracked;
343 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
344 "subfe $rT, $rA, $rB", IntGeneral,
345 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
346 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
347 "addme $rT, $rA", IntGeneral,
348 [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>;
349 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
350 "addze $rT, $rA", IntGeneral,
351 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
352 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
353 "neg $rT, $rA", IntGeneral,
354 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
355 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
356 "subfme $rT, $rA", IntGeneral,
357 [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>;
358 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
359 "subfze $rT, $rA", IntGeneral,
360 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
364 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
365 "mulhd $rT, $rA, $rB", IntMulHW,
366 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
367 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
368 "mulhdu $rT, $rA, $rB", IntMulHWU,
369 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
371 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
372 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
373 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
374 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
375 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
376 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
377 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
378 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
380 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
381 "sld $rA, $rS, $rB", IntRotateD,
382 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
383 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
384 "srd $rA, $rS, $rB", IntRotateD,
385 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
386 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
387 "srad $rA, $rS, $rB", IntRotateD,
388 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
390 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
391 "extsb $rA, $rS", IntGeneral,
392 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
393 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
394 "extsh $rA, $rS", IntGeneral,
395 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
397 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
398 "extsw $rA, $rS", IntGeneral,
399 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
400 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
401 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
402 "extsw $rA, $rS", IntGeneral,
403 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
404 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
405 "extsw $rA, $rS", IntGeneral,
406 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
408 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
409 "sradi $rA, $rS, $SH", IntRotateD,
410 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
411 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
412 "cntlzd $rA, $rS", IntGeneral,
413 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
415 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
416 "divd $rT, $rA, $rB", IntDivD,
417 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
418 PPC970_DGroup_First, PPC970_DGroup_Cracked;
419 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
420 "divdu $rT, $rA, $rB", IntDivD,
421 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
422 PPC970_DGroup_First, PPC970_DGroup_Cracked;
423 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
424 "mulld $rT, $rA, $rB", IntMulHD,
425 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
428 let isCommutable = 1 in {
429 def RLDIMI : MDForm_1<30, 3,
430 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
431 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
432 []>, isPPC64, RegConstraint<"$rSi = $rA">,
436 // Rotate instructions.
437 def RLDCL : MDForm_1<30, 0,
438 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
439 "rldcl $rA, $rS, $rB, $MB", IntRotateD,
441 def RLDICL : MDForm_1<30, 0,
442 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
443 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
445 def RLDICR : MDForm_1<30, 1,
446 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
447 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
449 } // End FXU Operations.
452 //===----------------------------------------------------------------------===//
453 // Load/Store instructions.
457 // Sign extending loads.
458 let isSimpleLoad = 1, PPC970_Unit = 2 in {
459 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
460 "lha $rD, $src", LdStLHA,
461 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
462 PPC970_DGroup_Cracked;
463 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
464 "lwa $rD, $src", LdStLWA,
465 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
466 PPC970_DGroup_Cracked;
467 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
468 "lhax $rD, $src", LdStLHA,
469 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
470 PPC970_DGroup_Cracked;
471 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
472 "lwax $rD, $src", LdStLHA,
473 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
474 PPC970_DGroup_Cracked;
477 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
479 "lhau $rD, $disp($rA)", LdStGeneral,
480 []>, RegConstraint<"$rA = $ea_result">,
481 NoEncode<"$ea_result">;
486 // Zero extending loads.
487 let isSimpleLoad = 1, PPC970_Unit = 2 in {
488 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
489 "lbz $rD, $src", LdStGeneral,
490 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
491 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
492 "lhz $rD, $src", LdStGeneral,
493 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
494 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
495 "lwz $rD, $src", LdStGeneral,
496 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
498 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
499 "lbzx $rD, $src", LdStGeneral,
500 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
501 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
502 "lhzx $rD, $src", LdStGeneral,
503 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
504 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
505 "lwzx $rD, $src", LdStGeneral,
506 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
510 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
511 "lbzu $rD, $addr", LdStGeneral,
512 []>, RegConstraint<"$addr.reg = $ea_result">,
513 NoEncode<"$ea_result">;
514 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
515 "lhzu $rD, $addr", LdStGeneral,
516 []>, RegConstraint<"$addr.reg = $ea_result">,
517 NoEncode<"$ea_result">;
518 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
519 "lwzu $rD, $addr", LdStGeneral,
520 []>, RegConstraint<"$addr.reg = $ea_result">,
521 NoEncode<"$ea_result">;
525 // Full 8-byte loads.
526 let isSimpleLoad = 1, PPC970_Unit = 2 in {
527 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
528 "ld $rD, $src", LdStLD,
529 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
530 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
531 "ldx $rD, $src", LdStLD,
532 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
534 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
535 "ldu $rD, $addr", LdStLD,
536 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
537 NoEncode<"$ea_result">;
541 let PPC970_Unit = 2 in {
542 // Truncating stores.
543 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
544 "stb $rS, $src", LdStGeneral,
545 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
546 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
547 "sth $rS, $src", LdStGeneral,
548 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
549 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
550 "stw $rS, $src", LdStGeneral,
551 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
552 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
553 "stbx $rS, $dst", LdStGeneral,
554 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
555 PPC970_DGroup_Cracked;
556 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
557 "sthx $rS, $dst", LdStGeneral,
558 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
559 PPC970_DGroup_Cracked;
560 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
561 "stwx $rS, $dst", LdStGeneral,
562 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
563 PPC970_DGroup_Cracked;
564 // Normal 8-byte stores.
565 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
566 "std $rS, $dst", LdStSTD,
567 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
568 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
569 "stdx $rS, $dst", LdStSTD,
570 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
571 PPC970_DGroup_Cracked;
574 let PPC970_Unit = 2 in {
576 def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
577 symbolLo:$ptroff, ptr_rc:$ptrreg),
578 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
579 [(set ptr_rc:$ea_res,
580 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
581 iaddroff:$ptroff))]>,
582 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
583 def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
584 symbolLo:$ptroff, ptr_rc:$ptrreg),
585 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
586 [(set ptr_rc:$ea_res,
587 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
588 iaddroff:$ptroff))]>,
589 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
590 def STWU8 : DForm_1<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
591 symbolLo:$ptroff, ptr_rc:$ptrreg),
592 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
593 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
594 iaddroff:$ptroff))]>,
595 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
598 def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
599 s16immX4:$ptroff, ptr_rc:$ptrreg),
600 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
601 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
602 iaddroff:$ptroff))]>,
603 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
607 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
608 "stdux $rS, $dst", LdStSTD,
611 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
612 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
613 "std $rT, $dst", LdStSTD,
614 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
615 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
616 "stdx $rT, $dst", LdStSTD,
617 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
618 PPC970_DGroup_Cracked;
623 //===----------------------------------------------------------------------===//
624 // Floating point instructions.
628 let PPC970_Unit = 3 in { // FPU Operations.
629 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
630 "fcfid $frD, $frB", FPGeneral,
631 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
632 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
633 "fctidz $frD, $frB", FPGeneral,
634 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
638 //===----------------------------------------------------------------------===//
639 // Instruction Patterns
642 // Extensions and truncates to/from 32-bit regs.
643 def : Pat<(i64 (zext GPRC:$in)),
644 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
645 def : Pat<(i64 (anyext GPRC:$in)),
646 (OR4To8 GPRC:$in, GPRC:$in)>;
647 def : Pat<(i32 (trunc G8RC:$in)),
648 (OR8To4 G8RC:$in, G8RC:$in)>;
650 // Extending loads with i64 targets.
651 def : Pat<(zextloadi1 iaddr:$src),
653 def : Pat<(zextloadi1 xaddr:$src),
655 def : Pat<(extloadi1 iaddr:$src),
657 def : Pat<(extloadi1 xaddr:$src),
659 def : Pat<(extloadi8 iaddr:$src),
661 def : Pat<(extloadi8 xaddr:$src),
663 def : Pat<(extloadi16 iaddr:$src),
665 def : Pat<(extloadi16 xaddr:$src),
667 def : Pat<(extloadi32 iaddr:$src),
669 def : Pat<(extloadi32 xaddr:$src),
672 // Standard shifts. These are represented separately from the real shifts above
673 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
675 def : Pat<(sra G8RC:$rS, GPRC:$rB),
676 (SRAD G8RC:$rS, GPRC:$rB)>;
677 def : Pat<(srl G8RC:$rS, GPRC:$rB),
678 (SRD G8RC:$rS, GPRC:$rB)>;
679 def : Pat<(shl G8RC:$rS, GPRC:$rB),
680 (SLD G8RC:$rS, GPRC:$rB)>;
683 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
684 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
685 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
686 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
689 def : Pat<(rotl G8RC:$in, GPRC:$sh),
690 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
691 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
692 (RLDICL G8RC:$in, imm:$imm, 0)>;
694 // Hi and Lo for Darwin Global Addresses.
695 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
696 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
697 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
698 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
699 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
700 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
701 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
702 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
703 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
704 (ADDIS8 G8RC:$in, tconstpool:$g)>;
705 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
706 (ADDIS8 G8RC:$in, tjumptable:$g)>;