1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
23 def u16imm64 : Operand<i64> {
24 let PrintMethod = "printU16ImmOperand";
25 let EncoderMethod = "getImm16Encoding";
26 let ParserMatchClass = PPCU16ImmAsmOperand;
28 def s17imm64 : Operand<i64> {
29 // This operand type is used for addis/lis to allow the assembler parser
30 // to accept immediates in the range -65536..65535 for compatibility with
31 // the GNU assembler. The operand is treated as 16-bit otherwise.
32 let PrintMethod = "printS16ImmOperand";
33 let EncoderMethod = "getImm16Encoding";
34 let ParserMatchClass = PPCS17ImmAsmOperand;
36 def tocentry : Operand<iPTR> {
37 let MIOperandInfo = (ops i64imm:$imm);
39 def tlsreg : Operand<i64> {
40 let EncoderMethod = "getTLSRegEncoding";
42 def tlsgd : Operand<i64> {}
44 //===----------------------------------------------------------------------===//
45 // 64-bit transformation functions.
48 def SHL64 : SDNodeXForm<imm, [{
49 // Transformation function: 63 - imm
50 return getI32Imm(63 - N->getZExtValue());
53 def SRL64 : SDNodeXForm<imm, [{
54 // Transformation function: 64 - imm
55 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
58 def HI32_48 : SDNodeXForm<imm, [{
59 // Transformation function: shift the immediate value down into the low bits.
60 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
63 def HI48_64 : SDNodeXForm<imm, [{
64 // Transformation function: shift the immediate value down into the low bits.
65 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
69 //===----------------------------------------------------------------------===//
73 let Interpretation64Bit = 1 in {
74 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
75 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
76 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
77 Requires<[In64BitMode]>;
79 let isCodeGenOnly = 1 in
80 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
81 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>,
82 Requires<[In64BitMode]>;
87 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
90 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
91 let Defs = [CTR8], Uses = [CTR8] in {
92 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
94 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
98 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
99 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
101 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
108 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
109 // Convenient aliases for call instructions
111 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
112 "bl $func", BrB, []>; // See Pat patterns below.
114 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
115 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
117 let Uses = [RM], isCodeGenOnly = 1 in {
118 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
119 (outs), (ins calltarget:$func),
120 "bl $func\n\tnop", BrB, []>;
122 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
123 (outs), (ins calltarget:$func, tlsgd:$sym),
124 "bl $func($sym)\n\tnop", BrB, []>;
126 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
127 (outs), (ins calltarget:$func, tlsgd:$sym),
128 "bl $func($sym)\n\tnop", BrB, []>;
130 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
131 (outs), (ins abscalltarget:$func),
132 "bla $func\n\tnop", BrB,
133 [(PPCcall_nop (i64 imm:$func))]>;
135 let Uses = [CTR8, RM] in {
136 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
137 "bctrl", BrB, [(PPCbctrl)]>,
138 Requires<[In64BitMode]>;
140 let isCodeGenOnly = 1 in
141 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
142 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>,
143 Requires<[In64BitMode]>;
146 } // Interpretation64Bit
149 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
150 (BL8 tglobaladdr:$dst)>;
151 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
152 (BL8_NOP tglobaladdr:$dst)>;
154 def : Pat<(PPCcall (i64 texternalsym:$dst)),
155 (BL8 texternalsym:$dst)>;
156 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
157 (BL8_NOP texternalsym:$dst)>;
160 let usesCustomInserter = 1 in {
161 let Defs = [CR0] in {
162 def ATOMIC_LOAD_ADD_I64 : Pseudo<
163 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
164 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
165 def ATOMIC_LOAD_SUB_I64 : Pseudo<
166 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
167 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
168 def ATOMIC_LOAD_OR_I64 : Pseudo<
169 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
170 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
171 def ATOMIC_LOAD_XOR_I64 : Pseudo<
172 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
173 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
174 def ATOMIC_LOAD_AND_I64 : Pseudo<
175 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
176 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
177 def ATOMIC_LOAD_NAND_I64 : Pseudo<
178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
179 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
181 def ATOMIC_CMP_SWAP_I64 : Pseudo<
182 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
183 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
185 def ATOMIC_SWAP_I64 : Pseudo<
186 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
187 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
191 // Instructions to support atomic operations
192 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
193 "ldarx $rD, $ptr", LdStLDARX,
194 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
197 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
198 "stdcx. $rS, $dst", LdStSTDCX,
199 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
202 let Interpretation64Bit = 1 in {
203 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
204 def TCRETURNdi8 :Pseudo< (outs),
205 (ins calltarget:$dst, i32imm:$offset),
206 "#TC_RETURNd8 $dst $offset",
209 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
210 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
211 "#TC_RETURNa8 $func $offset",
212 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
214 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
215 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
216 "#TC_RETURNr8 $dst $offset",
219 let isCodeGenOnly = 1 in {
221 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
222 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
223 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
224 Requires<[In64BitMode]>;
227 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
228 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
229 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
234 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
235 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
236 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
241 } // Interpretation64Bit
243 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
244 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
246 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
247 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
249 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
250 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
253 // 64-bit CR instructions
254 let Interpretation64Bit = 1 in {
255 let neverHasSideEffects = 1 in {
256 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS),
257 "mtcrf $FXM, $rS", BrMCRX>,
258 PPC970_MicroCode, PPC970_Unit_CRU;
260 let isCodeGenOnly = 1 in
261 def MFCR8pseud: XFXForm_3<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
262 "#MFCR8pseud", SprMFCR>,
263 PPC970_MicroCode, PPC970_Unit_CRU;
264 } // neverHasSideEffects = 1
266 let neverHasSideEffects = 1 in
267 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
268 "mfcr $rT", SprMFCR>,
269 PPC970_MicroCode, PPC970_Unit_CRU;
271 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
272 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
274 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
275 Requires<[In64BitMode]>;
276 let isTerminator = 1 in
277 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
278 "#EH_SJLJ_LONGJMP64",
279 [(PPCeh_sjlj_longjmp addr:$buf)]>,
280 Requires<[In64BitMode]>;
283 //===----------------------------------------------------------------------===//
284 // 64-bit SPR manipulation instrs.
286 let Uses = [CTR8] in {
287 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
288 "mfctr $rT", SprMFSPR>,
289 PPC970_DGroup_First, PPC970_Unit_FXU;
291 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
292 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
293 "mtctr $rS", SprMTSPR>,
294 PPC970_DGroup_First, PPC970_Unit_FXU;
296 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in {
297 let Pattern = [(int_ppc_mtctr i64:$rS)] in
298 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
299 "mtctr $rS", SprMTSPR>,
300 PPC970_DGroup_First, PPC970_Unit_FXU;
303 let Pattern = [(set i64:$rT, readcyclecounter)] in
304 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
305 "mfspr $rT, 268", SprMFTB>,
306 PPC970_DGroup_First, PPC970_Unit_FXU;
307 // Note that encoding mftb using mfspr is now the preferred form,
308 // and has been since at least ISA v2.03. The mftb instruction has
309 // now been phased out. Using mfspr, however, is known not to work on
312 let Defs = [X1], Uses = [X1] in
313 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
315 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
317 let Defs = [LR8] in {
318 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
319 "mtlr $rS", SprMTSPR>,
320 PPC970_DGroup_First, PPC970_Unit_FXU;
322 let Uses = [LR8] in {
323 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
324 "mflr $rT", SprMFSPR>,
325 PPC970_DGroup_First, PPC970_Unit_FXU;
327 } // Interpretation64Bit
329 //===----------------------------------------------------------------------===//
330 // Fixed point instructions.
333 let PPC970_Unit = 1 in { // FXU Operations.
334 let Interpretation64Bit = 1 in {
335 let neverHasSideEffects = 1 in {
337 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
338 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
339 "li $rD, $imm", IntSimple,
340 [(set i64:$rD, imm64SExt16:$imm)]>;
341 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
342 "lis $rD, $imm", IntSimple,
343 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
347 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
348 "nand", "$rA, $rS, $rB", IntSimple,
349 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
350 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
351 "and", "$rA, $rS, $rB", IntSimple,
352 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
353 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
354 "andc", "$rA, $rS, $rB", IntSimple,
355 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
356 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
357 "or", "$rA, $rS, $rB", IntSimple,
358 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
359 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
360 "nor", "$rA, $rS, $rB", IntSimple,
361 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
362 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
363 "orc", "$rA, $rS, $rB", IntSimple,
364 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
365 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
366 "eqv", "$rA, $rS, $rB", IntSimple,
367 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
368 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
369 "xor", "$rA, $rS, $rB", IntSimple,
370 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
372 // Logical ops with immediate.
373 let Defs = [CR0] in {
374 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
375 "andi. $dst, $src1, $src2", IntGeneral,
376 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
378 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
379 "andis. $dst, $src1, $src2", IntGeneral,
380 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
383 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
384 "ori $dst, $src1, $src2", IntSimple,
385 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
386 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
387 "oris $dst, $src1, $src2", IntSimple,
388 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
389 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
390 "xori $dst, $src1, $src2", IntSimple,
391 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
392 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
393 "xoris $dst, $src1, $src2", IntSimple,
394 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
396 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
397 "add", "$rT, $rA, $rB", IntSimple,
398 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
399 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
400 // initial-exec thread-local storage model.
401 let isCodeGenOnly = 1 in
402 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
403 "add $rT, $rA, $rB@tls", IntSimple,
404 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
406 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
407 "addc", "$rT, $rA, $rB", IntGeneral,
408 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
409 PPC970_DGroup_Cracked;
410 let Defs = [CARRY] in
411 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
412 "addic $rD, $rA, $imm", IntGeneral,
413 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
414 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
415 "addi $rD, $rA, $imm", IntSimple,
416 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
417 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
418 "addis $rD, $rA, $imm", IntSimple,
419 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
421 let Defs = [CARRY] in {
422 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
423 "subfic $rD, $rA, $imm", IntGeneral,
424 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
425 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
426 "subfc", "$rT, $rA, $rB", IntGeneral,
427 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
428 PPC970_DGroup_Cracked;
430 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
431 "subf", "$rT, $rA, $rB", IntGeneral,
432 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
433 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
434 "neg", "$rT, $rA", IntSimple,
435 [(set i64:$rT, (ineg i64:$rA))]>;
436 let Uses = [CARRY] in {
437 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
438 "adde", "$rT, $rA, $rB", IntGeneral,
439 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
440 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
441 "addme", "$rT, $rA", IntGeneral,
442 [(set i64:$rT, (adde i64:$rA, -1))]>;
443 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
444 "addze", "$rT, $rA", IntGeneral,
445 [(set i64:$rT, (adde i64:$rA, 0))]>;
446 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
447 "subfe", "$rT, $rA, $rB", IntGeneral,
448 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
449 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
450 "subfme", "$rT, $rA", IntGeneral,
451 [(set i64:$rT, (sube -1, i64:$rA))]>;
452 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
453 "subfze", "$rT, $rA", IntGeneral,
454 [(set i64:$rT, (sube 0, i64:$rA))]>;
458 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
459 "mulhd", "$rT, $rA, $rB", IntMulHW,
460 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
461 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
462 "mulhdu", "$rT, $rA, $rB", IntMulHWU,
463 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
465 } // Interpretation64Bit
467 let isCompare = 1, neverHasSideEffects = 1 in {
468 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
469 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
470 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
471 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
472 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
473 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
474 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
475 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
478 let neverHasSideEffects = 1 in {
479 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
480 "sld", "$rA, $rS, $rB", IntRotateD,
481 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
482 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
483 "srd", "$rA, $rS, $rB", IntRotateD,
484 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
485 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
486 "srad", "$rA, $rS, $rB", IntRotateD,
487 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
489 let Interpretation64Bit = 1 in {
490 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
491 "extsb", "$rA, $rS", IntSimple,
492 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
493 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
494 "extsh", "$rA, $rS", IntSimple,
495 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
496 } // Interpretation64Bit
498 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
499 "extsw", "$rA, $rS", IntSimple,
500 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
501 let Interpretation64Bit = 1 in
502 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
503 "extsw", "$rA, $rS", IntSimple,
504 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
506 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
507 "sradi", "$rA, $rS, $SH", IntRotateDI,
508 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
509 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
510 "cntlzd", "$rA, $rS", IntGeneral,
511 [(set i64:$rA, (ctlz i64:$rS))]>;
512 defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
513 "popcntd", "$rA, $rS", IntGeneral,
514 [(set i64:$rA, (ctpop i64:$rS))]>;
516 // popcntw also does a population count on the high 32 bits (storing the
517 // results in the high 32-bits of the output). We'll ignore that here (which is
518 // safe because we never separately use the high part of the 64-bit registers).
519 defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
520 "popcntw", "$rA, $rS", IntGeneral,
521 [(set i32:$rA, (ctpop i32:$rS))]>;
523 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
524 "divd", "$rT, $rA, $rB", IntDivD,
525 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
526 PPC970_DGroup_First, PPC970_DGroup_Cracked;
527 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
528 "divdu", "$rT, $rA, $rB", IntDivD,
529 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
530 PPC970_DGroup_First, PPC970_DGroup_Cracked;
531 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
532 "mulld", "$rT, $rA, $rB", IntMulHD,
533 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
536 let neverHasSideEffects = 1 in {
537 let isCommutable = 1 in {
538 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
539 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
540 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
541 []>, isPPC64, RegConstraint<"$rSi = $rA">,
545 // Rotate instructions.
546 defm RLDCL : MDSForm_1r<30, 8,
547 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
548 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
550 defm RLDCR : MDSForm_1r<30, 9,
551 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
552 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD,
554 defm RLDICL : MDForm_1r<30, 0,
555 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
556 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
558 defm RLDICR : MDForm_1r<30, 1,
559 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
560 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
562 defm RLDIC : MDForm_1r<30, 2,
563 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
564 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI,
567 let Interpretation64Bit = 1 in {
568 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
569 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
570 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
574 def ISEL8 : AForm_4<31, 15,
575 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
576 "isel $rT, $rA, $rB, $cond", IntGeneral,
578 } // Interpretation64Bit
579 } // neverHasSideEffects = 1
580 } // End FXU Operations.
583 //===----------------------------------------------------------------------===//
584 // Load/Store instructions.
588 // Sign extending loads.
589 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
590 let Interpretation64Bit = 1 in
591 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
592 "lha $rD, $src", LdStLHA,
593 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
594 PPC970_DGroup_Cracked;
595 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
596 "lwa $rD, $src", LdStLWA,
598 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
599 PPC970_DGroup_Cracked;
600 let Interpretation64Bit = 1 in
601 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
602 "lhax $rD, $src", LdStLHA,
603 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
604 PPC970_DGroup_Cracked;
605 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
606 "lwax $rD, $src", LdStLHA,
607 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
608 PPC970_DGroup_Cracked;
611 let mayLoad = 1, neverHasSideEffects = 1 in {
612 let Interpretation64Bit = 1 in
613 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
615 "lhau $rD, $addr", LdStLHAU,
616 []>, RegConstraint<"$addr.reg = $ea_result">,
617 NoEncode<"$ea_result">;
620 let Interpretation64Bit = 1 in
621 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
623 "lhaux $rD, $addr", LdStLHAU,
624 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
625 NoEncode<"$ea_result">;
626 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
628 "lwaux $rD, $addr", LdStLHAU,
629 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
630 NoEncode<"$ea_result">, isPPC64;
634 let Interpretation64Bit = 1 in {
635 // Zero extending loads.
636 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
637 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
638 "lbz $rD, $src", LdStLoad,
639 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
640 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
641 "lhz $rD, $src", LdStLoad,
642 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
643 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
644 "lwz $rD, $src", LdStLoad,
645 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
647 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
648 "lbzx $rD, $src", LdStLoad,
649 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
650 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
651 "lhzx $rD, $src", LdStLoad,
652 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
653 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
654 "lwzx $rD, $src", LdStLoad,
655 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
659 let mayLoad = 1, neverHasSideEffects = 1 in {
660 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
661 "lbzu $rD, $addr", LdStLoadUpd,
662 []>, RegConstraint<"$addr.reg = $ea_result">,
663 NoEncode<"$ea_result">;
664 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
665 "lhzu $rD, $addr", LdStLoadUpd,
666 []>, RegConstraint<"$addr.reg = $ea_result">,
667 NoEncode<"$ea_result">;
668 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
669 "lwzu $rD, $addr", LdStLoadUpd,
670 []>, RegConstraint<"$addr.reg = $ea_result">,
671 NoEncode<"$ea_result">;
673 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
675 "lbzux $rD, $addr", LdStLoadUpd,
676 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
677 NoEncode<"$ea_result">;
678 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
680 "lhzux $rD, $addr", LdStLoadUpd,
681 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
682 NoEncode<"$ea_result">;
683 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
685 "lwzux $rD, $addr", LdStLoadUpd,
686 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
687 NoEncode<"$ea_result">;
690 } // Interpretation64Bit
693 // Full 8-byte loads.
694 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
695 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
696 "ld $rD, $src", LdStLD,
697 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
698 // The following three definitions are selected for small code model only.
699 // Otherwise, we need to create two instructions to form a 32-bit offset,
700 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
701 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
704 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
705 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
708 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
709 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
712 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
714 let hasSideEffects = 1, isCodeGenOnly = 1 in {
715 let RST = 2, DS = 2 in
716 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
717 "ld 2, 8($reg)", LdStLD,
718 [(PPCload_toc i64:$reg)]>, isPPC64;
720 let RST = 2, DS = 10, RA = 1 in
721 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
722 "ld 2, 40(1)", LdStLD,
723 [(PPCtoc_restore)]>, isPPC64;
725 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
726 "ldx $rD, $src", LdStLD,
727 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
728 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
729 "ldbrx $rD, $src", LdStLoad,
730 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
732 let mayLoad = 1, neverHasSideEffects = 1 in {
733 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
734 "ldu $rD, $addr", LdStLDU,
735 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
736 NoEncode<"$ea_result">;
738 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
740 "ldux $rD, $addr", LdStLDU,
741 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
742 NoEncode<"$ea_result">, isPPC64;
746 def : Pat<(PPCload ixaddr:$src),
748 def : Pat<(PPCload xaddr:$src),
751 // Support for medium and large code model.
752 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
755 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
757 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
760 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
761 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
764 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
766 // Support for thread-local storage.
767 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
770 (PPCaddisGotTprelHA i64:$reg,
771 tglobaltlsaddr:$disp))]>,
773 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
776 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
778 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
779 (ADD8TLS $in, tglobaltlsaddr:$g)>;
780 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
783 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
785 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
788 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
790 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
793 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
795 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
798 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
800 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
803 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
805 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
808 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
810 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
813 (PPCaddisDtprelHA i64:$reg,
814 tglobaltlsaddr:$disp))]>,
816 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
819 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
822 let PPC970_Unit = 2 in {
823 let Interpretation64Bit = 1 in {
824 // Truncating stores.
825 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
826 "stb $rS, $src", LdStStore,
827 [(truncstorei8 i64:$rS, iaddr:$src)]>;
828 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
829 "sth $rS, $src", LdStStore,
830 [(truncstorei16 i64:$rS, iaddr:$src)]>;
831 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
832 "stw $rS, $src", LdStStore,
833 [(truncstorei32 i64:$rS, iaddr:$src)]>;
834 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
835 "stbx $rS, $dst", LdStStore,
836 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
837 PPC970_DGroup_Cracked;
838 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
839 "sthx $rS, $dst", LdStStore,
840 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
841 PPC970_DGroup_Cracked;
842 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
843 "stwx $rS, $dst", LdStStore,
844 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
845 PPC970_DGroup_Cracked;
846 } // Interpretation64Bit
848 // Normal 8-byte stores.
849 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
850 "std $rS, $dst", LdStSTD,
851 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
852 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
853 "stdx $rS, $dst", LdStSTD,
854 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
855 PPC970_DGroup_Cracked;
856 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
857 "stdbrx $rS, $dst", LdStStore,
858 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
859 PPC970_DGroup_Cracked;
862 // Stores with Update (pre-inc).
863 let PPC970_Unit = 2, mayStore = 1 in {
864 let Interpretation64Bit = 1 in {
865 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
866 "stbu $rS, $dst", LdStStoreUpd, []>,
867 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
868 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
869 "sthu $rS, $dst", LdStStoreUpd, []>,
870 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
871 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
872 "stwu $rS, $dst", LdStStoreUpd, []>,
873 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
874 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
875 "stdu $rS, $dst", LdStSTDU, []>,
876 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
879 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
880 "stbux $rS, $dst", LdStStoreUpd, []>,
881 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
882 PPC970_DGroup_Cracked;
883 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
884 "sthux $rS, $dst", LdStStoreUpd, []>,
885 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
886 PPC970_DGroup_Cracked;
887 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
888 "stwux $rS, $dst", LdStStoreUpd, []>,
889 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
890 PPC970_DGroup_Cracked;
891 } // Interpretation64Bit
893 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
894 "stdux $rS, $dst", LdStSTDU, []>,
895 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
896 PPC970_DGroup_Cracked, isPPC64;
899 // Patterns to match the pre-inc stores. We can't put the patterns on
900 // the instruction definitions directly as ISel wants the address base
901 // and offset to be separate operands, not a single complex operand.
902 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
903 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
904 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
905 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
906 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
907 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
908 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
909 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
911 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
912 (STBUX8 $rS, $ptrreg, $ptroff)>;
913 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
914 (STHUX8 $rS, $ptrreg, $ptroff)>;
915 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
916 (STWUX8 $rS, $ptrreg, $ptroff)>;
917 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
918 (STDUX $rS, $ptrreg, $ptroff)>;
921 //===----------------------------------------------------------------------===//
922 // Floating point instructions.
926 let PPC970_Unit = 3, neverHasSideEffects = 1,
927 Uses = [RM] in { // FPU Operations.
928 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
929 "fcfid", "$frD, $frB", FPGeneral,
930 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
931 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
932 "fctidz", "$frD, $frB", FPGeneral,
933 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
935 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
936 "fcfidu", "$frD, $frB", FPGeneral,
937 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
938 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
939 "fcfids", "$frD, $frB", FPGeneral,
940 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
941 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
942 "fcfidus", "$frD, $frB", FPGeneral,
943 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
944 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
945 "fctiduz", "$frD, $frB", FPGeneral,
946 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
947 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
948 "fctiwuz", "$frD, $frB", FPGeneral,
949 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
953 //===----------------------------------------------------------------------===//
954 // Instruction Patterns
957 // Extensions and truncates to/from 32-bit regs.
958 def : Pat<(i64 (zext i32:$in)),
959 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
961 def : Pat<(i64 (anyext i32:$in)),
962 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
963 def : Pat<(i32 (trunc i64:$in)),
964 (EXTRACT_SUBREG $in, sub_32)>;
966 // Extending loads with i64 targets.
967 def : Pat<(zextloadi1 iaddr:$src),
969 def : Pat<(zextloadi1 xaddr:$src),
971 def : Pat<(extloadi1 iaddr:$src),
973 def : Pat<(extloadi1 xaddr:$src),
975 def : Pat<(extloadi8 iaddr:$src),
977 def : Pat<(extloadi8 xaddr:$src),
979 def : Pat<(extloadi16 iaddr:$src),
981 def : Pat<(extloadi16 xaddr:$src),
983 def : Pat<(extloadi32 iaddr:$src),
985 def : Pat<(extloadi32 xaddr:$src),
988 // Standard shifts. These are represented separately from the real shifts above
989 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
991 def : Pat<(sra i64:$rS, i32:$rB),
993 def : Pat<(srl i64:$rS, i32:$rB),
995 def : Pat<(shl i64:$rS, i32:$rB),
999 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1000 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1001 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1002 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1005 def : Pat<(rotl i64:$in, i32:$sh),
1006 (RLDCL $in, $sh, 0)>;
1007 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1008 (RLDICL $in, imm:$imm, 0)>;
1010 // Hi and Lo for Darwin Global Addresses.
1011 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1012 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1013 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1014 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1015 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1016 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1017 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1018 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1019 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1020 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1021 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1022 (ADDI8 $in, tglobaltlsaddr:$g)>;
1023 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1024 (ADDIS8 $in, tglobaladdr:$g)>;
1025 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1026 (ADDIS8 $in, tconstpool:$g)>;
1027 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1028 (ADDIS8 $in, tjumptable:$g)>;
1029 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1030 (ADDIS8 $in, tblockaddress:$g)>;
1032 // Patterns to match r+r indexed loads and stores for
1033 // addresses without at least 4-byte alignment.
1034 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1035 (LWAX xoaddr:$src)>;
1036 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1038 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1039 (STDX $rS, xoaddr:$dst)>;