1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let ParserMatchClass = PPCS16ImmAsmOperand;
22 def u16imm64 : Operand<i64> {
23 let PrintMethod = "printU16ImmOperand";
24 let ParserMatchClass = PPCU16ImmAsmOperand;
26 def symbolHi64 : Operand<i64> {
27 let PrintMethod = "printSymbolHi";
28 let EncoderMethod = "getHA16Encoding";
29 let ParserMatchClass = PPCS16ImmAsmOperand;
31 def symbolLo64 : Operand<i64> {
32 let PrintMethod = "printSymbolLo";
33 let EncoderMethod = "getLO16Encoding";
34 let ParserMatchClass = PPCS16ImmAsmOperand;
36 def tocentry : Operand<iPTR> {
37 let MIOperandInfo = (ops i64imm:$imm);
39 def tlsreg : Operand<i64> {
40 let EncoderMethod = "getTLSRegEncoding";
42 def tlsgd : Operand<i64> {}
44 //===----------------------------------------------------------------------===//
45 // 64-bit transformation functions.
48 def SHL64 : SDNodeXForm<imm, [{
49 // Transformation function: 63 - imm
50 return getI32Imm(63 - N->getZExtValue());
53 def SRL64 : SDNodeXForm<imm, [{
54 // Transformation function: 64 - imm
55 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
58 def HI32_48 : SDNodeXForm<imm, [{
59 // Transformation function: shift the immediate value down into the low bits.
60 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
63 def HI48_64 : SDNodeXForm<imm, [{
64 // Transformation function: shift the immediate value down into the low bits.
65 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
69 //===----------------------------------------------------------------------===//
73 let Interpretation64Bit = 1 in {
74 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
75 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
76 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
77 Requires<[In64BitMode]>;
79 let isCodeGenOnly = 1 in
80 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
81 "b${cond:cc}ctr ${cond:reg}", BrB, []>,
82 Requires<[In64BitMode]>;
87 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
90 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
91 let Defs = [CTR8], Uses = [CTR8] in {
92 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
94 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
98 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
99 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
101 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
108 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
109 // Convenient aliases for call instructions
111 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
112 "bl $func", BrB, []>; // See Pat patterns below.
114 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func),
115 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
117 let Uses = [RM], isCodeGenOnly = 1 in {
118 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
119 (outs), (ins calltarget:$func),
120 "bl $func\n\tnop", BrB, []>;
122 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
123 (outs), (ins calltarget:$func, tlsgd:$sym),
124 "bl $func($sym)\n\tnop", BrB, []>;
126 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
127 (outs), (ins calltarget:$func, tlsgd:$sym),
128 "bl $func($sym)\n\tnop", BrB, []>;
130 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
131 (outs), (ins aaddr:$func),
132 "bla $func\n\tnop", BrB,
133 [(PPCcall_nop (i64 imm:$func))]>;
135 let Uses = [CTR8, RM] in {
136 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
137 "bctrl", BrB, [(PPCbctrl)]>,
138 Requires<[In64BitMode]>;
140 let isCodeGenOnly = 1 in
141 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
142 "b${cond:cc}ctrl ${cond:reg}", BrB, []>,
143 Requires<[In64BitMode]>;
146 } // Interpretation64Bit
149 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
150 (BL8 tglobaladdr:$dst)>;
151 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
152 (BL8_NOP tglobaladdr:$dst)>;
154 def : Pat<(PPCcall (i64 texternalsym:$dst)),
155 (BL8 texternalsym:$dst)>;
156 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
157 (BL8_NOP texternalsym:$dst)>;
160 let usesCustomInserter = 1 in {
161 let Defs = [CR0] in {
162 def ATOMIC_LOAD_ADD_I64 : Pseudo<
163 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
164 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
165 def ATOMIC_LOAD_SUB_I64 : Pseudo<
166 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
167 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
168 def ATOMIC_LOAD_OR_I64 : Pseudo<
169 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
170 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
171 def ATOMIC_LOAD_XOR_I64 : Pseudo<
172 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
173 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
174 def ATOMIC_LOAD_AND_I64 : Pseudo<
175 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
176 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
177 def ATOMIC_LOAD_NAND_I64 : Pseudo<
178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
179 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
181 def ATOMIC_CMP_SWAP_I64 : Pseudo<
182 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
183 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
185 def ATOMIC_SWAP_I64 : Pseudo<
186 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
187 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
191 // Instructions to support atomic operations
192 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
193 "ldarx $rD, $ptr", LdStLDARX,
194 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
197 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
198 "stdcx. $rS, $dst", LdStSTDCX,
199 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
202 let Interpretation64Bit = 1 in {
203 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
204 def TCRETURNdi8 :Pseudo< (outs),
205 (ins calltarget:$dst, i32imm:$offset),
206 "#TC_RETURNd8 $dst $offset",
209 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
210 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
211 "#TC_RETURNa8 $func $offset",
212 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
214 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
215 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
216 "#TC_RETURNr8 $dst $offset",
219 let isCodeGenOnly = 1 in {
221 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
222 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
223 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
224 Requires<[In64BitMode]>;
227 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
228 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
229 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
234 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
235 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
236 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
241 } // Interpretation64Bit
243 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
244 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
246 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
247 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
249 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
250 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
253 // 64-bit CR instructions
254 let Interpretation64Bit = 1 in {
255 let neverHasSideEffects = 1 in {
256 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS),
257 "mtcrf $FXM, $rS", BrMCRX>,
258 PPC970_MicroCode, PPC970_Unit_CRU;
260 let isCodeGenOnly = 1 in
261 def MFCR8pseud: XFXForm_3<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
262 "#MFCR8pseud", SprMFCR>,
263 PPC970_MicroCode, PPC970_Unit_CRU;
264 } // neverHasSideEffects = 1
266 let neverHasSideEffects = 1 in
267 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
268 "mfcr $rT", SprMFCR>,
269 PPC970_MicroCode, PPC970_Unit_CRU;
271 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
272 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
274 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
275 Requires<[In64BitMode]>;
276 let isTerminator = 1 in
277 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
278 "#EH_SJLJ_LONGJMP64",
279 [(PPCeh_sjlj_longjmp addr:$buf)]>,
280 Requires<[In64BitMode]>;
283 //===----------------------------------------------------------------------===//
284 // 64-bit SPR manipulation instrs.
286 let Uses = [CTR8] in {
287 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
288 "mfctr $rT", SprMFSPR>,
289 PPC970_DGroup_First, PPC970_Unit_FXU;
291 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
292 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
293 "mtctr $rS", SprMTSPR>,
294 PPC970_DGroup_First, PPC970_Unit_FXU;
297 let Pattern = [(set i64:$rT, readcyclecounter)] in
298 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
299 "mfspr $rT, 268", SprMFTB>,
300 PPC970_DGroup_First, PPC970_Unit_FXU;
301 // Note that encoding mftb using mfspr is now the preferred form,
302 // and has been since at least ISA v2.03. The mftb instruction has
303 // now been phased out. Using mfspr, however, is known not to work on
306 let Defs = [X1], Uses = [X1] in
307 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
309 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
311 let Defs = [LR8] in {
312 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
313 "mtlr $rS", SprMTSPR>,
314 PPC970_DGroup_First, PPC970_Unit_FXU;
316 let Uses = [LR8] in {
317 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
318 "mflr $rT", SprMFSPR>,
319 PPC970_DGroup_First, PPC970_Unit_FXU;
321 } // Interpretation64Bit
323 //===----------------------------------------------------------------------===//
324 // Fixed point instructions.
327 let PPC970_Unit = 1 in { // FXU Operations.
328 let Interpretation64Bit = 1 in {
329 let neverHasSideEffects = 1 in {
331 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
332 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins symbolLo64:$imm),
333 "li $rD, $imm", IntSimple,
334 [(set i64:$rD, immSExt16:$imm)]>;
335 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins symbolHi64:$imm),
336 "lis $rD, $imm", IntSimple,
337 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
341 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
342 "nand", "$rA, $rS, $rB", IntSimple,
343 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
344 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
345 "and", "$rA, $rS, $rB", IntSimple,
346 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
347 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
348 "andc", "$rA, $rS, $rB", IntSimple,
349 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
350 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
351 "or", "$rA, $rS, $rB", IntSimple,
352 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
353 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
354 "nor", "$rA, $rS, $rB", IntSimple,
355 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
356 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
357 "orc", "$rA, $rS, $rB", IntSimple,
358 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
359 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
360 "eqv", "$rA, $rS, $rB", IntSimple,
361 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
362 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
363 "xor", "$rA, $rS, $rB", IntSimple,
364 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
366 // Logical ops with immediate.
367 let Defs = [CR0] in {
368 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
369 "andi. $dst, $src1, $src2", IntGeneral,
370 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
372 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
373 "andis. $dst, $src1, $src2", IntGeneral,
374 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
377 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
378 "ori $dst, $src1, $src2", IntSimple,
379 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
380 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
381 "oris $dst, $src1, $src2", IntSimple,
382 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
383 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
384 "xori $dst, $src1, $src2", IntSimple,
385 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
386 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
387 "xoris $dst, $src1, $src2", IntSimple,
388 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
390 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
391 "add", "$rT, $rA, $rB", IntSimple,
392 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
393 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
394 // initial-exec thread-local storage model.
395 let isCodeGenOnly = 1 in
396 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
397 "add $rT, $rA, $rB@tls", IntSimple,
398 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
400 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
401 "addc", "$rT, $rA, $rB", IntGeneral,
402 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
403 PPC970_DGroup_Cracked;
404 let Defs = [CARRY] in
405 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
406 "addic $rD, $rA, $imm", IntGeneral,
407 [(set i64:$rD, (addc i64:$rA, immSExt16:$imm))]>;
408 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, symbolLo64:$imm),
409 "addi $rD, $rA, $imm", IntSimple,
410 [(set i64:$rD, (add i64:$rA, immSExt16:$imm))]>;
411 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, symbolHi64:$imm),
412 "addis $rD, $rA, $imm", IntSimple,
413 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
415 let Defs = [CARRY] in {
416 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
417 "subfic $rD, $rA, $imm", IntGeneral,
418 [(set i64:$rD, (subc immSExt16:$imm, i64:$rA))]>;
419 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
420 "subfc", "$rT, $rA, $rB", IntGeneral,
421 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
422 PPC970_DGroup_Cracked;
424 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
425 "subf", "$rT, $rA, $rB", IntGeneral,
426 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
427 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
428 "neg", "$rT, $rA", IntSimple,
429 [(set i64:$rT, (ineg i64:$rA))]>;
430 let Uses = [CARRY] in {
431 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
432 "adde", "$rT, $rA, $rB", IntGeneral,
433 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
434 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
435 "addme", "$rT, $rA", IntGeneral,
436 [(set i64:$rT, (adde i64:$rA, -1))]>;
437 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
438 "addze", "$rT, $rA", IntGeneral,
439 [(set i64:$rT, (adde i64:$rA, 0))]>;
440 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
441 "subfe", "$rT, $rA, $rB", IntGeneral,
442 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
443 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
444 "subfme", "$rT, $rA", IntGeneral,
445 [(set i64:$rT, (sube -1, i64:$rA))]>;
446 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
447 "subfze", "$rT, $rA", IntGeneral,
448 [(set i64:$rT, (sube 0, i64:$rA))]>;
452 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
453 "mulhd", "$rT, $rA, $rB", IntMulHW,
454 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
455 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
456 "mulhdu", "$rT, $rA, $rB", IntMulHWU,
457 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
459 } // Interpretation64Bit
461 let isCompare = 1, neverHasSideEffects = 1 in {
462 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
463 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
464 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
465 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
466 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
467 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
468 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
469 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
472 let neverHasSideEffects = 1 in {
473 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
474 "sld", "$rA, $rS, $rB", IntRotateD,
475 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
476 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
477 "srd", "$rA, $rS, $rB", IntRotateD,
478 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
479 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
480 "srad", "$rA, $rS, $rB", IntRotateD,
481 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
483 let Interpretation64Bit = 1 in {
484 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
485 "extsb", "$rA, $rS", IntSimple,
486 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
487 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
488 "extsh", "$rA, $rS", IntSimple,
489 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
490 } // Interpretation64Bit
492 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
493 "extsw", "$rA, $rS", IntSimple,
494 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
495 let Interpretation64Bit = 1 in
496 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
497 "extsw", "$rA, $rS", IntSimple,
498 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
500 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
501 "sradi", "$rA, $rS, $SH", IntRotateDI,
502 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
503 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
504 "cntlzd", "$rA, $rS", IntGeneral,
505 [(set i64:$rA, (ctlz i64:$rS))]>;
506 defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
507 "popcntd", "$rA, $rS", IntGeneral,
508 [(set i64:$rA, (ctpop i64:$rS))]>;
510 // popcntw also does a population count on the high 32 bits (storing the
511 // results in the high 32-bits of the output). We'll ignore that here (which is
512 // safe because we never separately use the high part of the 64-bit registers).
513 defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
514 "popcntw", "$rA, $rS", IntGeneral,
515 [(set i32:$rA, (ctpop i32:$rS))]>;
517 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
518 "divd", "$rT, $rA, $rB", IntDivD,
519 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
520 PPC970_DGroup_First, PPC970_DGroup_Cracked;
521 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
522 "divdu", "$rT, $rA, $rB", IntDivD,
523 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
524 PPC970_DGroup_First, PPC970_DGroup_Cracked;
525 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
526 "mulld", "$rT, $rA, $rB", IntMulHD,
527 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
530 let neverHasSideEffects = 1 in {
531 let isCommutable = 1 in {
532 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
533 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
534 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
535 []>, isPPC64, RegConstraint<"$rSi = $rA">,
539 // Rotate instructions.
540 defm RLDCL : MDSForm_1r<30, 8,
541 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
542 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
544 defm RLDICL : MDForm_1r<30, 0,
545 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
546 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
548 defm RLDICR : MDForm_1r<30, 1,
549 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
550 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
553 let Interpretation64Bit = 1 in {
554 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
555 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
556 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
560 def ISEL8 : AForm_4<31, 15,
561 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
562 "isel $rT, $rA, $rB, $cond", IntGeneral,
564 } // Interpretation64Bit
565 } // neverHasSideEffects = 1
566 } // End FXU Operations.
569 //===----------------------------------------------------------------------===//
570 // Load/Store instructions.
574 // Sign extending loads.
575 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
576 let Interpretation64Bit = 1 in
577 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
578 "lha $rD, $src", LdStLHA,
579 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
580 PPC970_DGroup_Cracked;
581 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
582 "lwa $rD, $src", LdStLWA,
584 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
585 PPC970_DGroup_Cracked;
586 let Interpretation64Bit = 1 in
587 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
588 "lhax $rD, $src", LdStLHA,
589 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
590 PPC970_DGroup_Cracked;
591 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
592 "lwax $rD, $src", LdStLHA,
593 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
594 PPC970_DGroup_Cracked;
597 let mayLoad = 1, neverHasSideEffects = 1 in {
598 let Interpretation64Bit = 1 in
599 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
601 "lhau $rD, $addr", LdStLHAU,
602 []>, RegConstraint<"$addr.reg = $ea_result">,
603 NoEncode<"$ea_result">;
606 let Interpretation64Bit = 1 in
607 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
609 "lhaux $rD, $addr", LdStLHAU,
610 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
611 NoEncode<"$ea_result">;
612 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
614 "lwaux $rD, $addr", LdStLHAU,
615 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
616 NoEncode<"$ea_result">, isPPC64;
620 let Interpretation64Bit = 1 in {
621 // Zero extending loads.
622 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
623 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
624 "lbz $rD, $src", LdStLoad,
625 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
626 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
627 "lhz $rD, $src", LdStLoad,
628 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
629 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
630 "lwz $rD, $src", LdStLoad,
631 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
633 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
634 "lbzx $rD, $src", LdStLoad,
635 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
636 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
637 "lhzx $rD, $src", LdStLoad,
638 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
639 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
640 "lwzx $rD, $src", LdStLoad,
641 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
645 let mayLoad = 1, neverHasSideEffects = 1 in {
646 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
647 "lbzu $rD, $addr", LdStLoadUpd,
648 []>, RegConstraint<"$addr.reg = $ea_result">,
649 NoEncode<"$ea_result">;
650 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
651 "lhzu $rD, $addr", LdStLoadUpd,
652 []>, RegConstraint<"$addr.reg = $ea_result">,
653 NoEncode<"$ea_result">;
654 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
655 "lwzu $rD, $addr", LdStLoadUpd,
656 []>, RegConstraint<"$addr.reg = $ea_result">,
657 NoEncode<"$ea_result">;
659 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
661 "lbzux $rD, $addr", LdStLoadUpd,
662 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
663 NoEncode<"$ea_result">;
664 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
666 "lhzux $rD, $addr", LdStLoadUpd,
667 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
668 NoEncode<"$ea_result">;
669 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
671 "lwzux $rD, $addr", LdStLoadUpd,
672 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
673 NoEncode<"$ea_result">;
676 } // Interpretation64Bit
679 // Full 8-byte loads.
680 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
681 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
682 "ld $rD, $src", LdStLD,
683 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
684 // The following three definitions are selected for small code model only.
685 // Otherwise, we need to create two instructions to form a 32-bit offset,
686 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
687 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
690 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
691 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
694 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
695 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
698 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
700 let hasSideEffects = 1, isCodeGenOnly = 1 in {
701 let RST = 2, DS = 2 in
702 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
703 "ld 2, 8($reg)", LdStLD,
704 [(PPCload_toc i64:$reg)]>, isPPC64;
706 let RST = 2, DS = 10, RA = 1 in
707 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
708 "ld 2, 40(1)", LdStLD,
709 [(PPCtoc_restore)]>, isPPC64;
711 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
712 "ldx $rD, $src", LdStLD,
713 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
714 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
715 "ldbrx $rD, $src", LdStLoad,
716 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
718 let mayLoad = 1, neverHasSideEffects = 1 in {
719 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
720 "ldu $rD, $addr", LdStLDU,
721 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
722 NoEncode<"$ea_result">;
724 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
726 "ldux $rD, $addr", LdStLDU,
727 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
728 NoEncode<"$ea_result">, isPPC64;
732 def : Pat<(PPCload ixaddr:$src),
734 def : Pat<(PPCload xaddr:$src),
737 // Support for medium and large code model.
738 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
741 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
743 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
746 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
747 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
750 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
752 // Support for thread-local storage.
753 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
756 (PPCaddisGotTprelHA i64:$reg,
757 tglobaltlsaddr:$disp))]>,
759 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins symbolLo64:$disp, g8rc_nox0:$reg),
762 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
764 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
765 (ADD8TLS $in, tglobaltlsaddr:$g)>;
766 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
769 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
771 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp),
774 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
776 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
779 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
781 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
784 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
786 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp),
789 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
791 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
794 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
796 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
799 (PPCaddisDtprelHA i64:$reg,
800 tglobaltlsaddr:$disp))]>,
802 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp),
805 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
808 let PPC970_Unit = 2 in {
809 let Interpretation64Bit = 1 in {
810 // Truncating stores.
811 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
812 "stb $rS, $src", LdStStore,
813 [(truncstorei8 i64:$rS, iaddr:$src)]>;
814 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
815 "sth $rS, $src", LdStStore,
816 [(truncstorei16 i64:$rS, iaddr:$src)]>;
817 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
818 "stw $rS, $src", LdStStore,
819 [(truncstorei32 i64:$rS, iaddr:$src)]>;
820 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
821 "stbx $rS, $dst", LdStStore,
822 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
823 PPC970_DGroup_Cracked;
824 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
825 "sthx $rS, $dst", LdStStore,
826 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
827 PPC970_DGroup_Cracked;
828 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
829 "stwx $rS, $dst", LdStStore,
830 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
831 PPC970_DGroup_Cracked;
832 } // Interpretation64Bit
834 // Normal 8-byte stores.
835 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
836 "std $rS, $dst", LdStSTD,
837 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
838 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
839 "stdx $rS, $dst", LdStSTD,
840 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
841 PPC970_DGroup_Cracked;
842 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
843 "stdbrx $rS, $dst", LdStStore,
844 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
845 PPC970_DGroup_Cracked;
848 // Stores with Update (pre-inc).
849 let PPC970_Unit = 2, mayStore = 1 in {
850 let Interpretation64Bit = 1 in {
851 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
852 "stbu $rS, $dst", LdStStoreUpd, []>,
853 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
854 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
855 "sthu $rS, $dst", LdStStoreUpd, []>,
856 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
857 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
858 "stwu $rS, $dst", LdStStoreUpd, []>,
859 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
860 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
861 "stdu $rS, $dst", LdStSTDU, []>,
862 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
865 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
866 "stbux $rS, $dst", LdStStoreUpd, []>,
867 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
868 PPC970_DGroup_Cracked;
869 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
870 "sthux $rS, $dst", LdStStoreUpd, []>,
871 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
872 PPC970_DGroup_Cracked;
873 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
874 "stwux $rS, $dst", LdStStoreUpd, []>,
875 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
876 PPC970_DGroup_Cracked;
877 } // Interpretation64Bit
879 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
880 "stdux $rS, $dst", LdStSTDU, []>,
881 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
882 PPC970_DGroup_Cracked, isPPC64;
885 // Patterns to match the pre-inc stores. We can't put the patterns on
886 // the instruction definitions directly as ISel wants the address base
887 // and offset to be separate operands, not a single complex operand.
888 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
889 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
890 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
891 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
892 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
893 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
894 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
895 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
897 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
898 (STBUX8 $rS, $ptrreg, $ptroff)>;
899 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
900 (STHUX8 $rS, $ptrreg, $ptroff)>;
901 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
902 (STWUX8 $rS, $ptrreg, $ptroff)>;
903 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
904 (STDUX $rS, $ptrreg, $ptroff)>;
907 //===----------------------------------------------------------------------===//
908 // Floating point instructions.
912 let PPC970_Unit = 3, neverHasSideEffects = 1,
913 Uses = [RM] in { // FPU Operations.
914 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
915 "fcfid", "$frD, $frB", FPGeneral,
916 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
917 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
918 "fctidz", "$frD, $frB", FPGeneral,
919 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
921 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
922 "fcfidu", "$frD, $frB", FPGeneral,
923 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
924 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
925 "fcfids", "$frD, $frB", FPGeneral,
926 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
927 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
928 "fcfidus", "$frD, $frB", FPGeneral,
929 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
930 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
931 "fctiduz", "$frD, $frB", FPGeneral,
932 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
933 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
934 "fctiwuz", "$frD, $frB", FPGeneral,
935 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
939 //===----------------------------------------------------------------------===//
940 // Instruction Patterns
943 // Extensions and truncates to/from 32-bit regs.
944 def : Pat<(i64 (zext i32:$in)),
945 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
947 def : Pat<(i64 (anyext i32:$in)),
948 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
949 def : Pat<(i32 (trunc i64:$in)),
950 (EXTRACT_SUBREG $in, sub_32)>;
952 // Extending loads with i64 targets.
953 def : Pat<(zextloadi1 iaddr:$src),
955 def : Pat<(zextloadi1 xaddr:$src),
957 def : Pat<(extloadi1 iaddr:$src),
959 def : Pat<(extloadi1 xaddr:$src),
961 def : Pat<(extloadi8 iaddr:$src),
963 def : Pat<(extloadi8 xaddr:$src),
965 def : Pat<(extloadi16 iaddr:$src),
967 def : Pat<(extloadi16 xaddr:$src),
969 def : Pat<(extloadi32 iaddr:$src),
971 def : Pat<(extloadi32 xaddr:$src),
974 // Standard shifts. These are represented separately from the real shifts above
975 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
977 def : Pat<(sra i64:$rS, i32:$rB),
979 def : Pat<(srl i64:$rS, i32:$rB),
981 def : Pat<(shl i64:$rS, i32:$rB),
985 def : Pat<(shl i64:$in, (i32 imm:$imm)),
986 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
987 def : Pat<(srl i64:$in, (i32 imm:$imm)),
988 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
991 def : Pat<(rotl i64:$in, i32:$sh),
992 (RLDCL $in, $sh, 0)>;
993 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
994 (RLDICL $in, imm:$imm, 0)>;
996 // Hi and Lo for Darwin Global Addresses.
997 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
998 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
999 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1000 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1001 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1002 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1003 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1004 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1005 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1006 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1007 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1008 (ADDI8 $in, tglobaltlsaddr:$g)>;
1009 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1010 (ADDIS8 $in, tglobaladdr:$g)>;
1011 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1012 (ADDIS8 $in, tconstpool:$g)>;
1013 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1014 (ADDIS8 $in, tjumptable:$g)>;
1015 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1016 (ADDIS8 $in, tblockaddress:$g)>;
1018 // Patterns to match r+r indexed loads and stores for
1019 // addresses without at least 4-byte alignment.
1020 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1021 (LWAX xoaddr:$src)>;
1022 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1024 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1025 (STDX $rS, xoaddr:$dst)>;