1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue());
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
67 def HI32_48 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
72 def HI48_64 : SDNodeXForm<imm, [{
73 // Transformation function: shift the immediate value down into the low bits.
74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
78 //===----------------------------------------------------------------------===//
82 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
83 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
84 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
85 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
87 Requires<[In64BitMode]>;
88 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
89 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
91 Requires<[In64BitMode]>;
96 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
99 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
100 let Defs = [CTR8], Uses = [CTR8] in {
101 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
103 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
107 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
108 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
109 "bdzlr", IIC_BrB, []>;
110 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
111 "bdnzlr", IIC_BrB, []>;
117 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
118 // Convenient aliases for call instructions
120 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
121 "bl $func", IIC_BrB, []>; // See Pat patterns below.
123 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
124 "bl $func", IIC_BrB, []>;
126 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
127 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
129 let Uses = [RM], isCodeGenOnly = 1 in {
130 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
131 (outs), (ins calltarget:$func),
132 "bl $func\n\tnop", IIC_BrB, []>;
134 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
135 (outs), (ins tlscall:$func),
136 "bl $func\n\tnop", IIC_BrB, []>;
138 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
139 (outs), (ins abscalltarget:$func),
140 "bla $func\n\tnop", IIC_BrB,
141 [(PPCcall_nop (i64 imm:$func))]>;
143 let Uses = [CTR8, RM] in {
144 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
145 "bctrl", IIC_BrB, [(PPCbctrl)]>,
146 Requires<[In64BitMode]>;
148 let isCodeGenOnly = 1 in
149 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
150 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
152 Requires<[In64BitMode]>;
155 } // Interpretation64Bit
157 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
158 // previous definition must be marked as CodeGen only to prevent decoding
160 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
161 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
162 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
163 "bl $func", IIC_BrB, []>;
166 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
167 (BL8 tglobaladdr:$dst)>;
168 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
169 (BL8_NOP tglobaladdr:$dst)>;
171 def : Pat<(PPCcall (i64 texternalsym:$dst)),
172 (BL8 texternalsym:$dst)>;
173 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
174 (BL8_NOP texternalsym:$dst)>;
177 let usesCustomInserter = 1 in {
178 let Defs = [CR0] in {
179 def ATOMIC_LOAD_ADD_I64 : Pseudo<
180 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
181 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
182 def ATOMIC_LOAD_SUB_I64 : Pseudo<
183 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
184 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
185 def ATOMIC_LOAD_OR_I64 : Pseudo<
186 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
187 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
188 def ATOMIC_LOAD_XOR_I64 : Pseudo<
189 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
190 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
191 def ATOMIC_LOAD_AND_I64 : Pseudo<
192 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
193 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
194 def ATOMIC_LOAD_NAND_I64 : Pseudo<
195 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
196 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
198 def ATOMIC_CMP_SWAP_I64 : Pseudo<
199 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
200 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
202 def ATOMIC_SWAP_I64 : Pseudo<
203 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
204 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
208 // Instructions to support atomic operations
209 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
210 "ldarx $rD, $ptr", IIC_LdStLDARX,
211 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
214 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
215 "stdcx. $rS, $dst", IIC_LdStSTDCX,
216 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
219 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
220 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
221 def TCRETURNdi8 :Pseudo< (outs),
222 (ins calltarget:$dst, i32imm:$offset),
223 "#TC_RETURNd8 $dst $offset",
226 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
227 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
228 "#TC_RETURNa8 $func $offset",
229 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
231 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
232 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
233 "#TC_RETURNr8 $dst $offset",
236 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
237 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
238 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
240 Requires<[In64BitMode]>;
242 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
243 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
244 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
248 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
249 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
250 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
253 } // Interpretation64Bit
255 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
256 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
258 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
259 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
261 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
262 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
265 // 64-bit CR instructions
266 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
267 let neverHasSideEffects = 1 in {
268 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
269 "mtocrf $FXM, $ST", IIC_BrMCRX>,
270 PPC970_DGroup_First, PPC970_Unit_CRU;
272 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
273 "mtcrf $FXM, $rS", IIC_BrMCRX>,
274 PPC970_MicroCode, PPC970_Unit_CRU;
276 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
277 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
278 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
279 PPC970_DGroup_First, PPC970_Unit_CRU;
281 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
282 "mfcr $rT", IIC_SprMFCR>,
283 PPC970_MicroCode, PPC970_Unit_CRU;
284 } // neverHasSideEffects = 1
286 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
288 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
290 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
291 Requires<[In64BitMode]>;
292 let isTerminator = 1 in
293 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
294 "#EH_SJLJ_LONGJMP64",
295 [(PPCeh_sjlj_longjmp addr:$buf)]>,
296 Requires<[In64BitMode]>;
299 //===----------------------------------------------------------------------===//
300 // 64-bit SPR manipulation instrs.
302 let Uses = [CTR8] in {
303 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
304 "mfctr $rT", IIC_SprMFSPR>,
305 PPC970_DGroup_First, PPC970_Unit_FXU;
307 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
308 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
309 "mtctr $rS", IIC_SprMTSPR>,
310 PPC970_DGroup_First, PPC970_Unit_FXU;
312 let hasSideEffects = 1, Defs = [CTR8] in {
313 let Pattern = [(int_ppc_mtctr i64:$rS)] in
314 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
315 "mtctr $rS", IIC_SprMTSPR>,
316 PPC970_DGroup_First, PPC970_Unit_FXU;
319 let Pattern = [(set i64:$rT, readcyclecounter)] in
320 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
321 "mfspr $rT, 268", IIC_SprMFTB>,
322 PPC970_DGroup_First, PPC970_Unit_FXU;
323 // Note that encoding mftb using mfspr is now the preferred form,
324 // and has been since at least ISA v2.03. The mftb instruction has
325 // now been phased out. Using mfspr, however, is known not to work on
328 let Defs = [X1], Uses = [X1] in
329 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
331 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
333 let Defs = [LR8] in {
334 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
335 "mtlr $rS", IIC_SprMTSPR>,
336 PPC970_DGroup_First, PPC970_Unit_FXU;
338 let Uses = [LR8] in {
339 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
340 "mflr $rT", IIC_SprMFSPR>,
341 PPC970_DGroup_First, PPC970_Unit_FXU;
343 } // Interpretation64Bit
345 //===----------------------------------------------------------------------===//
346 // Fixed point instructions.
349 let PPC970_Unit = 1 in { // FXU Operations.
350 let Interpretation64Bit = 1 in {
351 let neverHasSideEffects = 1 in {
352 let isCodeGenOnly = 1 in {
354 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
355 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
356 "li $rD, $imm", IIC_IntSimple,
357 [(set i64:$rD, imm64SExt16:$imm)]>;
358 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
359 "lis $rD, $imm", IIC_IntSimple,
360 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
364 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
365 "nand", "$rA, $rS, $rB", IIC_IntSimple,
366 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
367 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
368 "and", "$rA, $rS, $rB", IIC_IntSimple,
369 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
370 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
371 "andc", "$rA, $rS, $rB", IIC_IntSimple,
372 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
373 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
374 "or", "$rA, $rS, $rB", IIC_IntSimple,
375 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
376 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
377 "nor", "$rA, $rS, $rB", IIC_IntSimple,
378 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
379 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
380 "orc", "$rA, $rS, $rB", IIC_IntSimple,
381 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
382 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
383 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
384 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
385 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
386 "xor", "$rA, $rS, $rB", IIC_IntSimple,
387 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
389 // Logical ops with immediate.
390 let Defs = [CR0] in {
391 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
392 "andi. $dst, $src1, $src2", IIC_IntGeneral,
393 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
395 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
396 "andis. $dst, $src1, $src2", IIC_IntGeneral,
397 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
400 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
401 "ori $dst, $src1, $src2", IIC_IntSimple,
402 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
403 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
404 "oris $dst, $src1, $src2", IIC_IntSimple,
405 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
406 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
407 "xori $dst, $src1, $src2", IIC_IntSimple,
408 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
409 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
410 "xoris $dst, $src1, $src2", IIC_IntSimple,
411 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
413 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
414 "add", "$rT, $rA, $rB", IIC_IntSimple,
415 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
416 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
417 // initial-exec thread-local storage model.
418 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
419 "add $rT, $rA, $rB", IIC_IntSimple,
420 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
422 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
423 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
424 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
425 PPC970_DGroup_Cracked;
426 let Defs = [CARRY] in
427 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
428 "addic $rD, $rA, $imm", IIC_IntGeneral,
429 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
430 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
431 "addi $rD, $rA, $imm", IIC_IntSimple,
432 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
433 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
434 "addis $rD, $rA, $imm", IIC_IntSimple,
435 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
437 let Defs = [CARRY] in {
438 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
439 "subfic $rD, $rA, $imm", IIC_IntGeneral,
440 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
441 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
442 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
443 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
444 PPC970_DGroup_Cracked;
446 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
447 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
448 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
449 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
450 "neg", "$rT, $rA", IIC_IntSimple,
451 [(set i64:$rT, (ineg i64:$rA))]>;
452 let Uses = [CARRY] in {
453 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
454 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
455 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
456 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
457 "addme", "$rT, $rA", IIC_IntGeneral,
458 [(set i64:$rT, (adde i64:$rA, -1))]>;
459 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
460 "addze", "$rT, $rA", IIC_IntGeneral,
461 [(set i64:$rT, (adde i64:$rA, 0))]>;
462 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
463 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
464 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
465 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
466 "subfme", "$rT, $rA", IIC_IntGeneral,
467 [(set i64:$rT, (sube -1, i64:$rA))]>;
468 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
469 "subfze", "$rT, $rA", IIC_IntGeneral,
470 [(set i64:$rT, (sube 0, i64:$rA))]>;
474 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
475 // previous definition must be marked as CodeGen only to prevent decoding
477 let isAsmParserOnly = 1 in
478 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
479 "add $rT, $rA, $rB", IIC_IntSimple, []>;
481 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
482 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
483 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
484 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
485 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
486 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
488 } // Interpretation64Bit
490 let isCompare = 1, neverHasSideEffects = 1 in {
491 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
492 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
493 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
494 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
495 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
496 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
497 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
498 "cmpldi $dst, $src1, $src2",
499 IIC_IntCompare>, isPPC64;
502 let neverHasSideEffects = 1 in {
503 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
504 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
505 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
506 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
507 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
508 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
509 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
510 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
511 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
513 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
514 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
515 "extsb", "$rA, $rS", IIC_IntSimple,
516 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
517 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
518 "extsh", "$rA, $rS", IIC_IntSimple,
519 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
520 } // Interpretation64Bit
523 let isCodeGenOnly = 1 in {
524 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
525 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
526 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
527 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
528 } // isCodeGenOnly for fast-isel
530 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
531 "extsw", "$rA, $rS", IIC_IntSimple,
532 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
533 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
534 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
535 "extsw", "$rA, $rS", IIC_IntSimple,
536 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
538 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
539 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
540 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
541 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
542 "cntlzd", "$rA, $rS", IIC_IntGeneral,
543 [(set i64:$rA, (ctlz i64:$rS))]>;
544 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
545 "popcntd $rA, $rS", IIC_IntGeneral,
546 [(set i64:$rA, (ctpop i64:$rS))]>;
548 // popcntw also does a population count on the high 32 bits (storing the
549 // results in the high 32-bits of the output). We'll ignore that here (which is
550 // safe because we never separately use the high part of the 64-bit registers).
551 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
552 "popcntw $rA, $rS", IIC_IntGeneral,
553 [(set i32:$rA, (ctpop i32:$rS))]>;
555 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
556 "divd", "$rT, $rA, $rB", IIC_IntDivD,
557 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
558 PPC970_DGroup_First, PPC970_DGroup_Cracked;
559 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
560 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
561 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
562 PPC970_DGroup_First, PPC970_DGroup_Cracked;
563 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
564 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
565 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
566 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
567 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
568 "mulli $rD, $rA, $imm", IIC_IntMulLI,
569 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
572 let neverHasSideEffects = 1 in {
573 let isCommutable = 1 in {
574 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
575 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
576 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
577 []>, isPPC64, RegConstraint<"$rSi = $rA">,
581 // Rotate instructions.
582 defm RLDCL : MDSForm_1r<30, 8,
583 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
584 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
586 defm RLDCR : MDSForm_1r<30, 9,
587 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
588 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
590 defm RLDICL : MDForm_1r<30, 0,
591 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
592 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
595 let isCodeGenOnly = 1 in
596 def RLDICL_32_64 : MDForm_1<30, 0,
598 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
599 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
602 defm RLDICR : MDForm_1r<30, 1,
603 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
604 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
606 defm RLDIC : MDForm_1r<30, 2,
607 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
608 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
611 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
612 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
613 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
614 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
618 def ISEL8 : AForm_4<31, 15,
619 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
620 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
622 } // Interpretation64Bit
623 } // neverHasSideEffects = 1
624 } // End FXU Operations.
627 //===----------------------------------------------------------------------===//
628 // Load/Store instructions.
632 // Sign extending loads.
633 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
634 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
635 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
636 "lha $rD, $src", IIC_LdStLHA,
637 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
638 PPC970_DGroup_Cracked;
639 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
640 "lwa $rD, $src", IIC_LdStLWA,
642 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
643 PPC970_DGroup_Cracked;
644 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
645 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
646 "lhax $rD, $src", IIC_LdStLHA,
647 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
648 PPC970_DGroup_Cracked;
649 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
650 "lwax $rD, $src", IIC_LdStLHA,
651 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
652 PPC970_DGroup_Cracked;
654 let isCodeGenOnly = 1, mayLoad = 1 in {
655 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
656 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
657 PPC970_DGroup_Cracked;
658 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
659 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
660 PPC970_DGroup_Cracked;
661 } // end fast-isel isCodeGenOnly
664 let mayLoad = 1, neverHasSideEffects = 1 in {
665 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
666 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
668 "lhau $rD, $addr", IIC_LdStLHAU,
669 []>, RegConstraint<"$addr.reg = $ea_result">,
670 NoEncode<"$ea_result">;
673 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
674 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
676 "lhaux $rD, $addr", IIC_LdStLHAUX,
677 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
678 NoEncode<"$ea_result">;
679 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
681 "lwaux $rD, $addr", IIC_LdStLHAUX,
682 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
683 NoEncode<"$ea_result">, isPPC64;
687 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
688 // Zero extending loads.
689 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
690 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
691 "lbz $rD, $src", IIC_LdStLoad,
692 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
693 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
694 "lhz $rD, $src", IIC_LdStLoad,
695 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
696 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
697 "lwz $rD, $src", IIC_LdStLoad,
698 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
700 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
701 "lbzx $rD, $src", IIC_LdStLoad,
702 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
703 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
704 "lhzx $rD, $src", IIC_LdStLoad,
705 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
706 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
707 "lwzx $rD, $src", IIC_LdStLoad,
708 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
712 let mayLoad = 1, neverHasSideEffects = 1 in {
713 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
714 "lbzu $rD, $addr", IIC_LdStLoadUpd,
715 []>, RegConstraint<"$addr.reg = $ea_result">,
716 NoEncode<"$ea_result">;
717 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
718 "lhzu $rD, $addr", IIC_LdStLoadUpd,
719 []>, RegConstraint<"$addr.reg = $ea_result">,
720 NoEncode<"$ea_result">;
721 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
722 "lwzu $rD, $addr", IIC_LdStLoadUpd,
723 []>, RegConstraint<"$addr.reg = $ea_result">,
724 NoEncode<"$ea_result">;
726 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
728 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
729 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
730 NoEncode<"$ea_result">;
731 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
733 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
734 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
735 NoEncode<"$ea_result">;
736 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
738 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
739 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
740 NoEncode<"$ea_result">;
743 } // Interpretation64Bit
746 // Full 8-byte loads.
747 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
748 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
749 "ld $rD, $src", IIC_LdStLD,
750 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
751 // The following three definitions are selected for small code model only.
752 // Otherwise, we need to create two instructions to form a 32-bit offset,
753 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
754 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
757 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
758 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
761 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
762 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
765 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
767 let hasSideEffects = 1, isCodeGenOnly = 1 in {
768 let RST = 2, DS = 2 in
769 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
770 "ld 2, 8($reg)", IIC_LdStLD,
771 [(PPCload_toc i64:$reg)]>, isPPC64;
773 let RST = 2, DS = 10, RA = 1 in
774 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
775 "ld 2, 40(1)", IIC_LdStLD,
776 [(PPCtoc_restore)]>, isPPC64;
778 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
779 "ldx $rD, $src", IIC_LdStLD,
780 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
781 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
782 "ldbrx $rD, $src", IIC_LdStLoad,
783 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
785 let mayLoad = 1, neverHasSideEffects = 1 in {
786 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
787 "ldu $rD, $addr", IIC_LdStLDU,
788 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
789 NoEncode<"$ea_result">;
791 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
793 "ldux $rD, $addr", IIC_LdStLDUX,
794 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
795 NoEncode<"$ea_result">, isPPC64;
799 def : Pat<(PPCload ixaddr:$src),
801 def : Pat<(PPCload xaddr:$src),
804 // Support for medium and large code model.
805 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
808 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
810 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
813 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
814 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
817 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
819 // Support for thread-local storage.
820 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
823 (PPCaddisGotTprelHA i64:$reg,
824 tglobaltlsaddr:$disp))]>,
826 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
829 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
831 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
832 (ADD8TLS $in, tglobaltlsaddr:$g)>;
833 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
836 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
838 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
841 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
843 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
846 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
848 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
851 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
853 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
856 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
858 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
861 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
863 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
866 (PPCaddisDtprelHA i64:$reg,
867 tglobaltlsaddr:$disp))]>,
869 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
872 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
875 let PPC970_Unit = 2 in {
876 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
877 // Truncating stores.
878 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
879 "stb $rS, $src", IIC_LdStStore,
880 [(truncstorei8 i64:$rS, iaddr:$src)]>;
881 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
882 "sth $rS, $src", IIC_LdStStore,
883 [(truncstorei16 i64:$rS, iaddr:$src)]>;
884 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
885 "stw $rS, $src", IIC_LdStStore,
886 [(truncstorei32 i64:$rS, iaddr:$src)]>;
887 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
888 "stbx $rS, $dst", IIC_LdStStore,
889 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
890 PPC970_DGroup_Cracked;
891 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
892 "sthx $rS, $dst", IIC_LdStStore,
893 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
894 PPC970_DGroup_Cracked;
895 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
896 "stwx $rS, $dst", IIC_LdStStore,
897 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
898 PPC970_DGroup_Cracked;
899 } // Interpretation64Bit
901 // Normal 8-byte stores.
902 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
903 "std $rS, $dst", IIC_LdStSTD,
904 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
905 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
906 "stdx $rS, $dst", IIC_LdStSTD,
907 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
908 PPC970_DGroup_Cracked;
909 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
910 "stdbrx $rS, $dst", IIC_LdStStore,
911 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
912 PPC970_DGroup_Cracked;
915 // Stores with Update (pre-inc).
916 let PPC970_Unit = 2, mayStore = 1 in {
917 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
918 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
919 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
920 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
921 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
922 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
923 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
924 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
925 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
926 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
928 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
929 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
930 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
931 PPC970_DGroup_Cracked;
932 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
933 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
934 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
935 PPC970_DGroup_Cracked;
936 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
937 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
938 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
939 PPC970_DGroup_Cracked;
940 } // Interpretation64Bit
942 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
943 "stdu $rS, $dst", IIC_LdStSTDU, []>,
944 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
947 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
948 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
949 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
950 PPC970_DGroup_Cracked, isPPC64;
953 // Patterns to match the pre-inc stores. We can't put the patterns on
954 // the instruction definitions directly as ISel wants the address base
955 // and offset to be separate operands, not a single complex operand.
956 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
957 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
958 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
959 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
960 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
961 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
962 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
963 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
965 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
966 (STBUX8 $rS, $ptrreg, $ptroff)>;
967 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
968 (STHUX8 $rS, $ptrreg, $ptroff)>;
969 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
970 (STWUX8 $rS, $ptrreg, $ptroff)>;
971 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
972 (STDUX $rS, $ptrreg, $ptroff)>;
975 //===----------------------------------------------------------------------===//
976 // Floating point instructions.
980 let PPC970_Unit = 3, neverHasSideEffects = 1,
981 Uses = [RM] in { // FPU Operations.
982 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
983 "fcfid", "$frD, $frB", IIC_FPGeneral,
984 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
985 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
986 "fctid", "$frD, $frB", IIC_FPGeneral,
988 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
989 "fctidz", "$frD, $frB", IIC_FPGeneral,
990 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
992 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
993 "fcfidu", "$frD, $frB", IIC_FPGeneral,
994 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
995 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
996 "fcfids", "$frD, $frB", IIC_FPGeneral,
997 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
998 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
999 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1000 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1001 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1002 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1003 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1004 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1005 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1006 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1010 //===----------------------------------------------------------------------===//
1011 // Instruction Patterns
1014 // Extensions and truncates to/from 32-bit regs.
1015 def : Pat<(i64 (zext i32:$in)),
1016 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1018 def : Pat<(i64 (anyext i32:$in)),
1019 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1020 def : Pat<(i32 (trunc i64:$in)),
1021 (EXTRACT_SUBREG $in, sub_32)>;
1023 // Extending loads with i64 targets.
1024 def : Pat<(zextloadi1 iaddr:$src),
1026 def : Pat<(zextloadi1 xaddr:$src),
1027 (LBZX8 xaddr:$src)>;
1028 def : Pat<(extloadi1 iaddr:$src),
1030 def : Pat<(extloadi1 xaddr:$src),
1031 (LBZX8 xaddr:$src)>;
1032 def : Pat<(extloadi8 iaddr:$src),
1034 def : Pat<(extloadi8 xaddr:$src),
1035 (LBZX8 xaddr:$src)>;
1036 def : Pat<(extloadi16 iaddr:$src),
1038 def : Pat<(extloadi16 xaddr:$src),
1039 (LHZX8 xaddr:$src)>;
1040 def : Pat<(extloadi32 iaddr:$src),
1042 def : Pat<(extloadi32 xaddr:$src),
1043 (LWZX8 xaddr:$src)>;
1045 // Standard shifts. These are represented separately from the real shifts above
1046 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1048 def : Pat<(sra i64:$rS, i32:$rB),
1050 def : Pat<(srl i64:$rS, i32:$rB),
1052 def : Pat<(shl i64:$rS, i32:$rB),
1056 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1057 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1058 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1059 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1062 def : Pat<(rotl i64:$in, i32:$sh),
1063 (RLDCL $in, $sh, 0)>;
1064 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1065 (RLDICL $in, imm:$imm, 0)>;
1067 // Hi and Lo for Darwin Global Addresses.
1068 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1069 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1070 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1071 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1072 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1073 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1074 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1075 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1076 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1077 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1078 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1079 (ADDI8 $in, tglobaltlsaddr:$g)>;
1080 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1081 (ADDIS8 $in, tglobaladdr:$g)>;
1082 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1083 (ADDIS8 $in, tconstpool:$g)>;
1084 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1085 (ADDIS8 $in, tjumptable:$g)>;
1086 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1087 (ADDIS8 $in, tblockaddress:$g)>;
1089 // Patterns to match r+r indexed loads and stores for
1090 // addresses without at least 4-byte alignment.
1091 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1092 (LWAX xoaddr:$src)>;
1093 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1095 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1096 (STDX $rS, xoaddr:$dst)>;