1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
23 def u16imm64 : Operand<i64> {
24 let PrintMethod = "printU16ImmOperand";
25 let EncoderMethod = "getImm16Encoding";
26 let ParserMatchClass = PPCU16ImmAsmOperand;
28 def s17imm64 : Operand<i64> {
29 // This operand type is used for addis/lis to allow the assembler parser
30 // to accept immediates in the range -65536..65535 for compatibility with
31 // the GNU assembler. The operand is treated as 16-bit otherwise.
32 let PrintMethod = "printS16ImmOperand";
33 let EncoderMethod = "getImm16Encoding";
34 let ParserMatchClass = PPCS17ImmAsmOperand;
36 def tocentry : Operand<iPTR> {
37 let MIOperandInfo = (ops i64imm:$imm);
39 def tlsreg : Operand<i64> {
40 let EncoderMethod = "getTLSRegEncoding";
42 def tlsgd : Operand<i64> {}
43 def tlscall : Operand<i64> {
44 let PrintMethod = "printTLSCall";
45 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
46 let EncoderMethod = "getTLSCallEncoding";
49 //===----------------------------------------------------------------------===//
50 // 64-bit transformation functions.
53 def SHL64 : SDNodeXForm<imm, [{
54 // Transformation function: 63 - imm
55 return getI32Imm(63 - N->getZExtValue());
58 def SRL64 : SDNodeXForm<imm, [{
59 // Transformation function: 64 - imm
60 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
63 def HI32_48 : SDNodeXForm<imm, [{
64 // Transformation function: shift the immediate value down into the low bits.
65 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
68 def HI48_64 : SDNodeXForm<imm, [{
69 // Transformation function: shift the immediate value down into the low bits.
70 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
74 //===----------------------------------------------------------------------===//
78 let Interpretation64Bit = 1 in {
79 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
81 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
82 Requires<[In64BitMode]>;
84 let isCodeGenOnly = 1 in
85 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>,
87 Requires<[In64BitMode]>;
92 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
95 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
96 let Defs = [CTR8], Uses = [CTR8] in {
97 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
99 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
103 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
104 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
106 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
113 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
114 // Convenient aliases for call instructions
116 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
117 "bl $func", BrB, []>; // See Pat patterns below.
119 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
120 "bl $func", BrB, []>;
122 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
123 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
125 let Uses = [RM], isCodeGenOnly = 1 in {
126 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
127 (outs), (ins calltarget:$func),
128 "bl $func\n\tnop", BrB, []>;
130 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
131 (outs), (ins tlscall:$func),
132 "bl $func\n\tnop", BrB, []>;
134 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
135 (outs), (ins abscalltarget:$func),
136 "bla $func\n\tnop", BrB,
137 [(PPCcall_nop (i64 imm:$func))]>;
139 let Uses = [CTR8, RM] in {
140 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
141 "bctrl", BrB, [(PPCbctrl)]>,
142 Requires<[In64BitMode]>;
144 let isCodeGenOnly = 1 in
145 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
146 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>,
147 Requires<[In64BitMode]>;
150 } // Interpretation64Bit
153 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
154 (BL8 tglobaladdr:$dst)>;
155 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
156 (BL8_NOP tglobaladdr:$dst)>;
158 def : Pat<(PPCcall (i64 texternalsym:$dst)),
159 (BL8 texternalsym:$dst)>;
160 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
161 (BL8_NOP texternalsym:$dst)>;
164 let usesCustomInserter = 1 in {
165 let Defs = [CR0] in {
166 def ATOMIC_LOAD_ADD_I64 : Pseudo<
167 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
168 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
169 def ATOMIC_LOAD_SUB_I64 : Pseudo<
170 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
171 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
172 def ATOMIC_LOAD_OR_I64 : Pseudo<
173 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
174 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
175 def ATOMIC_LOAD_XOR_I64 : Pseudo<
176 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
177 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
178 def ATOMIC_LOAD_AND_I64 : Pseudo<
179 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
180 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
181 def ATOMIC_LOAD_NAND_I64 : Pseudo<
182 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
183 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
185 def ATOMIC_CMP_SWAP_I64 : Pseudo<
186 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
187 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
189 def ATOMIC_SWAP_I64 : Pseudo<
190 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
191 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
195 // Instructions to support atomic operations
196 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
197 "ldarx $rD, $ptr", LdStLDARX,
198 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
201 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
202 "stdcx. $rS, $dst", LdStSTDCX,
203 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
206 let Interpretation64Bit = 1 in {
207 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
208 def TCRETURNdi8 :Pseudo< (outs),
209 (ins calltarget:$dst, i32imm:$offset),
210 "#TC_RETURNd8 $dst $offset",
213 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
214 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
215 "#TC_RETURNa8 $func $offset",
216 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
218 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
219 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
220 "#TC_RETURNr8 $dst $offset",
223 let isCodeGenOnly = 1 in {
225 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
226 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
227 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
228 Requires<[In64BitMode]>;
231 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
232 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
233 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
238 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
239 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
240 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
245 } // Interpretation64Bit
247 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
248 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
250 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
251 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
253 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
254 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
257 // 64-bit CR instructions
258 let Interpretation64Bit = 1 in {
259 let neverHasSideEffects = 1 in {
260 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
261 "mtocrf $FXM, $ST", BrMCRX>,
262 PPC970_DGroup_First, PPC970_Unit_CRU;
264 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
265 "mtcrf $FXM, $rS", BrMCRX>,
266 PPC970_MicroCode, PPC970_Unit_CRU;
268 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
269 "mfocrf $rT, $FXM", SprMFCR>,
270 PPC970_DGroup_First, PPC970_Unit_CRU;
272 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
273 "mfcr $rT", SprMFCR>,
274 PPC970_MicroCode, PPC970_Unit_CRU;
275 } // neverHasSideEffects = 1
277 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
278 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
280 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
281 Requires<[In64BitMode]>;
282 let isTerminator = 1 in
283 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
284 "#EH_SJLJ_LONGJMP64",
285 [(PPCeh_sjlj_longjmp addr:$buf)]>,
286 Requires<[In64BitMode]>;
289 //===----------------------------------------------------------------------===//
290 // 64-bit SPR manipulation instrs.
292 let Uses = [CTR8] in {
293 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
294 "mfctr $rT", SprMFSPR>,
295 PPC970_DGroup_First, PPC970_Unit_FXU;
297 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
298 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
299 "mtctr $rS", SprMTSPR>,
300 PPC970_DGroup_First, PPC970_Unit_FXU;
302 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in {
303 let Pattern = [(int_ppc_mtctr i64:$rS)] in
304 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
305 "mtctr $rS", SprMTSPR>,
306 PPC970_DGroup_First, PPC970_Unit_FXU;
309 let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in
310 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
311 "mfspr $rT, 268", SprMFTB>,
312 PPC970_DGroup_First, PPC970_Unit_FXU;
313 // Note that encoding mftb using mfspr is now the preferred form,
314 // and has been since at least ISA v2.03. The mftb instruction has
315 // now been phased out. Using mfspr, however, is known not to work on
318 let Defs = [X1], Uses = [X1] in
319 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
321 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
323 let Defs = [LR8] in {
324 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
325 "mtlr $rS", SprMTSPR>,
326 PPC970_DGroup_First, PPC970_Unit_FXU;
328 let Uses = [LR8] in {
329 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
330 "mflr $rT", SprMFSPR>,
331 PPC970_DGroup_First, PPC970_Unit_FXU;
333 } // Interpretation64Bit
335 //===----------------------------------------------------------------------===//
336 // Fixed point instructions.
339 let PPC970_Unit = 1 in { // FXU Operations.
340 let Interpretation64Bit = 1 in {
341 let neverHasSideEffects = 1 in {
343 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
344 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
345 "li $rD, $imm", IntSimple,
346 [(set i64:$rD, imm64SExt16:$imm)]>;
347 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
348 "lis $rD, $imm", IntSimple,
349 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
353 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
354 "nand", "$rA, $rS, $rB", IntSimple,
355 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
356 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
357 "and", "$rA, $rS, $rB", IntSimple,
358 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
359 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
360 "andc", "$rA, $rS, $rB", IntSimple,
361 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
362 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
363 "or", "$rA, $rS, $rB", IntSimple,
364 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
365 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
366 "nor", "$rA, $rS, $rB", IntSimple,
367 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
368 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
369 "orc", "$rA, $rS, $rB", IntSimple,
370 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
371 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
372 "eqv", "$rA, $rS, $rB", IntSimple,
373 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
374 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
375 "xor", "$rA, $rS, $rB", IntSimple,
376 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
378 // Logical ops with immediate.
379 let Defs = [CR0] in {
380 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
381 "andi. $dst, $src1, $src2", IntGeneral,
382 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
384 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
385 "andis. $dst, $src1, $src2", IntGeneral,
386 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
389 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
390 "ori $dst, $src1, $src2", IntSimple,
391 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
392 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
393 "oris $dst, $src1, $src2", IntSimple,
394 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
395 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
396 "xori $dst, $src1, $src2", IntSimple,
397 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
398 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
399 "xoris $dst, $src1, $src2", IntSimple,
400 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
402 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
403 "add", "$rT, $rA, $rB", IntSimple,
404 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
405 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
406 // initial-exec thread-local storage model.
407 let isCodeGenOnly = 1 in
408 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
409 "add $rT, $rA, $rB@tls", IntSimple,
410 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
412 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
413 "addc", "$rT, $rA, $rB", IntGeneral,
414 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
415 PPC970_DGroup_Cracked;
416 let Defs = [CARRY] in
417 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
418 "addic $rD, $rA, $imm", IntGeneral,
419 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
420 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
421 "addi $rD, $rA, $imm", IntSimple,
422 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
423 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
424 "addis $rD, $rA, $imm", IntSimple,
425 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
427 let Defs = [CARRY] in {
428 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
429 "subfic $rD, $rA, $imm", IntGeneral,
430 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
431 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
432 "subfc", "$rT, $rA, $rB", IntGeneral,
433 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
434 PPC970_DGroup_Cracked;
436 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
437 "subf", "$rT, $rA, $rB", IntGeneral,
438 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
439 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
440 "neg", "$rT, $rA", IntSimple,
441 [(set i64:$rT, (ineg i64:$rA))]>;
442 let Uses = [CARRY] in {
443 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
444 "adde", "$rT, $rA, $rB", IntGeneral,
445 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
446 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
447 "addme", "$rT, $rA", IntGeneral,
448 [(set i64:$rT, (adde i64:$rA, -1))]>;
449 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
450 "addze", "$rT, $rA", IntGeneral,
451 [(set i64:$rT, (adde i64:$rA, 0))]>;
452 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
453 "subfe", "$rT, $rA, $rB", IntGeneral,
454 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
455 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
456 "subfme", "$rT, $rA", IntGeneral,
457 [(set i64:$rT, (sube -1, i64:$rA))]>;
458 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
459 "subfze", "$rT, $rA", IntGeneral,
460 [(set i64:$rT, (sube 0, i64:$rA))]>;
464 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
465 "mulhd", "$rT, $rA, $rB", IntMulHW,
466 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
467 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
468 "mulhdu", "$rT, $rA, $rB", IntMulHWU,
469 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
471 } // Interpretation64Bit
473 let isCompare = 1, neverHasSideEffects = 1 in {
474 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
475 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
476 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
477 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
478 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
479 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
480 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
481 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
484 let neverHasSideEffects = 1 in {
485 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
486 "sld", "$rA, $rS, $rB", IntRotateD,
487 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
488 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
489 "srd", "$rA, $rS, $rB", IntRotateD,
490 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
491 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
492 "srad", "$rA, $rS, $rB", IntRotateD,
493 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
495 let Interpretation64Bit = 1 in {
496 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
497 "extsb", "$rA, $rS", IntSimple,
498 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
499 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
500 "extsh", "$rA, $rS", IntSimple,
501 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
502 } // Interpretation64Bit
504 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
505 "extsw", "$rA, $rS", IntSimple,
506 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
507 let Interpretation64Bit = 1 in
508 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
509 "extsw", "$rA, $rS", IntSimple,
510 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
512 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
513 "sradi", "$rA, $rS, $SH", IntRotateDI,
514 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
515 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
516 "cntlzd", "$rA, $rS", IntGeneral,
517 [(set i64:$rA, (ctlz i64:$rS))]>;
518 defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
519 "popcntd", "$rA, $rS", IntGeneral,
520 [(set i64:$rA, (ctpop i64:$rS))]>;
522 // popcntw also does a population count on the high 32 bits (storing the
523 // results in the high 32-bits of the output). We'll ignore that here (which is
524 // safe because we never separately use the high part of the 64-bit registers).
525 defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
526 "popcntw", "$rA, $rS", IntGeneral,
527 [(set i32:$rA, (ctpop i32:$rS))]>;
529 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
530 "divd", "$rT, $rA, $rB", IntDivD,
531 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
532 PPC970_DGroup_First, PPC970_DGroup_Cracked;
533 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
534 "divdu", "$rT, $rA, $rB", IntDivD,
535 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
536 PPC970_DGroup_First, PPC970_DGroup_Cracked;
537 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
538 "mulld", "$rT, $rA, $rB", IntMulHD,
539 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
542 let neverHasSideEffects = 1 in {
543 let isCommutable = 1 in {
544 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
545 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
546 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
547 []>, isPPC64, RegConstraint<"$rSi = $rA">,
551 // Rotate instructions.
552 defm RLDCL : MDSForm_1r<30, 8,
553 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
554 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
556 defm RLDCR : MDSForm_1r<30, 9,
557 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
558 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD,
560 defm RLDICL : MDForm_1r<30, 0,
561 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
562 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
564 defm RLDICR : MDForm_1r<30, 1,
565 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
566 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
568 defm RLDIC : MDForm_1r<30, 2,
569 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
570 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI,
573 let Interpretation64Bit = 1 in {
574 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
575 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
576 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
580 def ISEL8 : AForm_4<31, 15,
581 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
582 "isel $rT, $rA, $rB, $cond", IntGeneral,
584 } // Interpretation64Bit
585 } // neverHasSideEffects = 1
586 } // End FXU Operations.
589 //===----------------------------------------------------------------------===//
590 // Load/Store instructions.
594 // Sign extending loads.
595 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
596 let Interpretation64Bit = 1 in
597 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
598 "lha $rD, $src", LdStLHA,
599 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
600 PPC970_DGroup_Cracked;
601 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
602 "lwa $rD, $src", LdStLWA,
604 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
605 PPC970_DGroup_Cracked;
606 let Interpretation64Bit = 1 in
607 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
608 "lhax $rD, $src", LdStLHA,
609 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
610 PPC970_DGroup_Cracked;
611 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
612 "lwax $rD, $src", LdStLHA,
613 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
614 PPC970_DGroup_Cracked;
617 let mayLoad = 1, neverHasSideEffects = 1 in {
618 let Interpretation64Bit = 1 in
619 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
621 "lhau $rD, $addr", LdStLHAU,
622 []>, RegConstraint<"$addr.reg = $ea_result">,
623 NoEncode<"$ea_result">;
626 let Interpretation64Bit = 1 in
627 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
629 "lhaux $rD, $addr", LdStLHAU,
630 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
631 NoEncode<"$ea_result">;
632 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
634 "lwaux $rD, $addr", LdStLHAU,
635 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
636 NoEncode<"$ea_result">, isPPC64;
640 let Interpretation64Bit = 1 in {
641 // Zero extending loads.
642 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
643 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
644 "lbz $rD, $src", LdStLoad,
645 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
646 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
647 "lhz $rD, $src", LdStLoad,
648 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
649 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
650 "lwz $rD, $src", LdStLoad,
651 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
653 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
654 "lbzx $rD, $src", LdStLoad,
655 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
656 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
657 "lhzx $rD, $src", LdStLoad,
658 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
659 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
660 "lwzx $rD, $src", LdStLoad,
661 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
665 let mayLoad = 1, neverHasSideEffects = 1 in {
666 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
667 "lbzu $rD, $addr", LdStLoadUpd,
668 []>, RegConstraint<"$addr.reg = $ea_result">,
669 NoEncode<"$ea_result">;
670 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
671 "lhzu $rD, $addr", LdStLoadUpd,
672 []>, RegConstraint<"$addr.reg = $ea_result">,
673 NoEncode<"$ea_result">;
674 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
675 "lwzu $rD, $addr", LdStLoadUpd,
676 []>, RegConstraint<"$addr.reg = $ea_result">,
677 NoEncode<"$ea_result">;
679 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
681 "lbzux $rD, $addr", LdStLoadUpd,
682 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
683 NoEncode<"$ea_result">;
684 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
686 "lhzux $rD, $addr", LdStLoadUpd,
687 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
688 NoEncode<"$ea_result">;
689 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
691 "lwzux $rD, $addr", LdStLoadUpd,
692 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
693 NoEncode<"$ea_result">;
696 } // Interpretation64Bit
699 // Full 8-byte loads.
700 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
701 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
702 "ld $rD, $src", LdStLD,
703 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
704 // The following three definitions are selected for small code model only.
705 // Otherwise, we need to create two instructions to form a 32-bit offset,
706 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
707 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
710 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
711 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
714 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
715 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
718 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
720 let hasSideEffects = 1, isCodeGenOnly = 1 in {
721 let RST = 2, DS = 2 in
722 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
723 "ld 2, 8($reg)", LdStLD,
724 [(PPCload_toc i64:$reg)]>, isPPC64;
726 let RST = 2, DS = 10, RA = 1 in
727 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
728 "ld 2, 40(1)", LdStLD,
729 [(PPCtoc_restore)]>, isPPC64;
731 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
732 "ldx $rD, $src", LdStLD,
733 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
734 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
735 "ldbrx $rD, $src", LdStLoad,
736 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
738 let mayLoad = 1, neverHasSideEffects = 1 in {
739 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
740 "ldu $rD, $addr", LdStLDU,
741 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
742 NoEncode<"$ea_result">;
744 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
746 "ldux $rD, $addr", LdStLDU,
747 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
748 NoEncode<"$ea_result">, isPPC64;
752 def : Pat<(PPCload ixaddr:$src),
754 def : Pat<(PPCload xaddr:$src),
757 // Support for medium and large code model.
758 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
761 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
763 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
766 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
767 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
770 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
772 // Support for thread-local storage.
773 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
776 (PPCaddisGotTprelHA i64:$reg,
777 tglobaltlsaddr:$disp))]>,
779 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
782 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
784 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
785 (ADD8TLS $in, tglobaltlsaddr:$g)>;
786 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
789 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
791 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
794 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
796 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
799 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
801 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
804 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
806 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
809 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
811 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
814 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
816 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
819 (PPCaddisDtprelHA i64:$reg,
820 tglobaltlsaddr:$disp))]>,
822 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
825 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
828 let PPC970_Unit = 2 in {
829 let Interpretation64Bit = 1 in {
830 // Truncating stores.
831 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
832 "stb $rS, $src", LdStStore,
833 [(truncstorei8 i64:$rS, iaddr:$src)]>;
834 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
835 "sth $rS, $src", LdStStore,
836 [(truncstorei16 i64:$rS, iaddr:$src)]>;
837 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
838 "stw $rS, $src", LdStStore,
839 [(truncstorei32 i64:$rS, iaddr:$src)]>;
840 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
841 "stbx $rS, $dst", LdStStore,
842 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
843 PPC970_DGroup_Cracked;
844 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
845 "sthx $rS, $dst", LdStStore,
846 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
847 PPC970_DGroup_Cracked;
848 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
849 "stwx $rS, $dst", LdStStore,
850 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
851 PPC970_DGroup_Cracked;
852 } // Interpretation64Bit
854 // Normal 8-byte stores.
855 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
856 "std $rS, $dst", LdStSTD,
857 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
858 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
859 "stdx $rS, $dst", LdStSTD,
860 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
861 PPC970_DGroup_Cracked;
862 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
863 "stdbrx $rS, $dst", LdStStore,
864 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
865 PPC970_DGroup_Cracked;
868 // Stores with Update (pre-inc).
869 let PPC970_Unit = 2, mayStore = 1 in {
870 let Interpretation64Bit = 1 in {
871 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
872 "stbu $rS, $dst", LdStStoreUpd, []>,
873 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
874 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
875 "sthu $rS, $dst", LdStStoreUpd, []>,
876 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
877 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
878 "stwu $rS, $dst", LdStStoreUpd, []>,
879 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
880 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
881 "stdu $rS, $dst", LdStSTDU, []>,
882 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
885 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
886 "stbux $rS, $dst", LdStStoreUpd, []>,
887 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
888 PPC970_DGroup_Cracked;
889 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
890 "sthux $rS, $dst", LdStStoreUpd, []>,
891 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
892 PPC970_DGroup_Cracked;
893 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
894 "stwux $rS, $dst", LdStStoreUpd, []>,
895 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
896 PPC970_DGroup_Cracked;
897 } // Interpretation64Bit
899 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
900 "stdux $rS, $dst", LdStSTDU, []>,
901 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
902 PPC970_DGroup_Cracked, isPPC64;
905 // Patterns to match the pre-inc stores. We can't put the patterns on
906 // the instruction definitions directly as ISel wants the address base
907 // and offset to be separate operands, not a single complex operand.
908 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
909 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
910 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
911 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
912 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
913 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
914 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
915 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
917 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
918 (STBUX8 $rS, $ptrreg, $ptroff)>;
919 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
920 (STHUX8 $rS, $ptrreg, $ptroff)>;
921 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
922 (STWUX8 $rS, $ptrreg, $ptroff)>;
923 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
924 (STDUX $rS, $ptrreg, $ptroff)>;
927 //===----------------------------------------------------------------------===//
928 // Floating point instructions.
932 let PPC970_Unit = 3, neverHasSideEffects = 1,
933 Uses = [RM] in { // FPU Operations.
934 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
935 "fcfid", "$frD, $frB", FPGeneral,
936 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
937 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
938 "fctidz", "$frD, $frB", FPGeneral,
939 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
941 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
942 "fcfidu", "$frD, $frB", FPGeneral,
943 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
944 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
945 "fcfids", "$frD, $frB", FPGeneral,
946 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
947 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
948 "fcfidus", "$frD, $frB", FPGeneral,
949 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
950 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
951 "fctiduz", "$frD, $frB", FPGeneral,
952 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
953 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
954 "fctiwuz", "$frD, $frB", FPGeneral,
955 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
959 //===----------------------------------------------------------------------===//
960 // Instruction Patterns
963 // Extensions and truncates to/from 32-bit regs.
964 def : Pat<(i64 (zext i32:$in)),
965 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
967 def : Pat<(i64 (anyext i32:$in)),
968 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
969 def : Pat<(i32 (trunc i64:$in)),
970 (EXTRACT_SUBREG $in, sub_32)>;
972 // Extending loads with i64 targets.
973 def : Pat<(zextloadi1 iaddr:$src),
975 def : Pat<(zextloadi1 xaddr:$src),
977 def : Pat<(extloadi1 iaddr:$src),
979 def : Pat<(extloadi1 xaddr:$src),
981 def : Pat<(extloadi8 iaddr:$src),
983 def : Pat<(extloadi8 xaddr:$src),
985 def : Pat<(extloadi16 iaddr:$src),
987 def : Pat<(extloadi16 xaddr:$src),
989 def : Pat<(extloadi32 iaddr:$src),
991 def : Pat<(extloadi32 xaddr:$src),
994 // Standard shifts. These are represented separately from the real shifts above
995 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
997 def : Pat<(sra i64:$rS, i32:$rB),
999 def : Pat<(srl i64:$rS, i32:$rB),
1001 def : Pat<(shl i64:$rS, i32:$rB),
1005 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1006 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1007 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1008 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1011 def : Pat<(rotl i64:$in, i32:$sh),
1012 (RLDCL $in, $sh, 0)>;
1013 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1014 (RLDICL $in, imm:$imm, 0)>;
1016 // Hi and Lo for Darwin Global Addresses.
1017 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1018 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1019 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1020 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1021 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1022 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1023 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1024 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1025 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1026 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1027 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1028 (ADDI8 $in, tglobaltlsaddr:$g)>;
1029 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1030 (ADDIS8 $in, tglobaladdr:$g)>;
1031 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1032 (ADDIS8 $in, tconstpool:$g)>;
1033 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1034 (ADDIS8 $in, tjumptable:$g)>;
1035 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1036 (ADDIS8 $in, tblockaddress:$g)>;
1038 // Patterns to match r+r indexed loads and stores for
1039 // addresses without at least 4-byte alignment.
1040 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1041 (LWAX xoaddr:$src)>;
1042 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1044 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1045 (STDX $rS, xoaddr:$dst)>;