1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
23 def u16imm64 : Operand<i64> {
24 let PrintMethod = "printU16ImmOperand";
25 let EncoderMethod = "getImm16Encoding";
26 let ParserMatchClass = PPCU16ImmAsmOperand;
28 def s17imm64 : Operand<i64> {
29 // This operand type is used for addis/lis to allow the assembler parser
30 // to accept immediates in the range -65536..65535 for compatibility with
31 // the GNU assembler. The operand is treated as 16-bit otherwise.
32 let PrintMethod = "printS16ImmOperand";
33 let EncoderMethod = "getImm16Encoding";
34 let ParserMatchClass = PPCS17ImmAsmOperand;
36 def tocentry : Operand<iPTR> {
37 let MIOperandInfo = (ops i64imm:$imm);
39 def PPCTLSRegOperand : AsmOperandClass {
40 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
41 let RenderMethod = "addTLSRegOperands";
43 def tlsreg : Operand<i64> {
44 let EncoderMethod = "getTLSRegEncoding";
45 let ParserMatchClass = PPCTLSRegOperand;
47 def tlsgd : Operand<i64> {}
48 def tlscall : Operand<i64> {
49 let PrintMethod = "printTLSCall";
50 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
51 let EncoderMethod = "getTLSCallEncoding";
54 //===----------------------------------------------------------------------===//
55 // 64-bit transformation functions.
58 def SHL64 : SDNodeXForm<imm, [{
59 // Transformation function: 63 - imm
60 return getI32Imm(63 - N->getZExtValue());
63 def SRL64 : SDNodeXForm<imm, [{
64 // Transformation function: 64 - imm
65 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
68 def HI32_48 : SDNodeXForm<imm, [{
69 // Transformation function: shift the immediate value down into the low bits.
70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
73 def HI48_64 : SDNodeXForm<imm, [{
74 // Transformation function: shift the immediate value down into the low bits.
75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
79 //===----------------------------------------------------------------------===//
83 let Interpretation64Bit = 1 in {
84 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
85 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
86 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
87 Requires<[In64BitMode]>;
89 let isCodeGenOnly = 1 in
90 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
91 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>,
92 Requires<[In64BitMode]>;
97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
100 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
101 let Defs = [CTR8], Uses = [CTR8] in {
102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
118 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
119 // Convenient aliases for call instructions
121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
122 "bl $func", BrB, []>; // See Pat patterns below.
124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
125 "bl $func", BrB, []>;
127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
128 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
130 let Uses = [RM], isCodeGenOnly = 1 in {
131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
132 (outs), (ins calltarget:$func),
133 "bl $func\n\tnop", BrB, []>;
135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
136 (outs), (ins tlscall:$func),
137 "bl $func\n\tnop", BrB, []>;
139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
140 (outs), (ins abscalltarget:$func),
141 "bla $func\n\tnop", BrB,
142 [(PPCcall_nop (i64 imm:$func))]>;
144 let Uses = [CTR8, RM] in {
145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
146 "bctrl", BrB, [(PPCbctrl)]>,
147 Requires<[In64BitMode]>;
149 let isCodeGenOnly = 1 in
150 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>,
152 Requires<[In64BitMode]>;
155 } // Interpretation64Bit
158 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
159 (BL8 tglobaladdr:$dst)>;
160 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
161 (BL8_NOP tglobaladdr:$dst)>;
163 def : Pat<(PPCcall (i64 texternalsym:$dst)),
164 (BL8 texternalsym:$dst)>;
165 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
166 (BL8_NOP texternalsym:$dst)>;
169 let usesCustomInserter = 1 in {
170 let Defs = [CR0] in {
171 def ATOMIC_LOAD_ADD_I64 : Pseudo<
172 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
173 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
174 def ATOMIC_LOAD_SUB_I64 : Pseudo<
175 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
176 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
177 def ATOMIC_LOAD_OR_I64 : Pseudo<
178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
179 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
180 def ATOMIC_LOAD_XOR_I64 : Pseudo<
181 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
182 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
183 def ATOMIC_LOAD_AND_I64 : Pseudo<
184 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
185 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
186 def ATOMIC_LOAD_NAND_I64 : Pseudo<
187 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
188 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
190 def ATOMIC_CMP_SWAP_I64 : Pseudo<
191 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
192 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
194 def ATOMIC_SWAP_I64 : Pseudo<
195 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
196 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
200 // Instructions to support atomic operations
201 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
202 "ldarx $rD, $ptr", LdStLDARX,
203 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
206 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
207 "stdcx. $rS, $dst", LdStSTDCX,
208 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
211 let Interpretation64Bit = 1 in {
212 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
213 def TCRETURNdi8 :Pseudo< (outs),
214 (ins calltarget:$dst, i32imm:$offset),
215 "#TC_RETURNd8 $dst $offset",
218 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
219 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
220 "#TC_RETURNa8 $func $offset",
221 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
223 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
224 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
225 "#TC_RETURNr8 $dst $offset",
228 let isCodeGenOnly = 1 in {
230 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
231 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
232 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
233 Requires<[In64BitMode]>;
236 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
237 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
238 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
243 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
244 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
245 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
250 } // Interpretation64Bit
252 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
253 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
255 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
256 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
258 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
259 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
262 // 64-bit CR instructions
263 let Interpretation64Bit = 1 in {
264 let neverHasSideEffects = 1 in {
265 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
266 "mtocrf $FXM, $ST", BrMCRX>,
267 PPC970_DGroup_First, PPC970_Unit_CRU;
269 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
270 "mtcrf $FXM, $rS", BrMCRX>,
271 PPC970_MicroCode, PPC970_Unit_CRU;
273 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
274 "mfocrf $rT, $FXM", SprMFCR>,
275 PPC970_DGroup_First, PPC970_Unit_CRU;
277 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
278 "mfcr $rT", SprMFCR>,
279 PPC970_MicroCode, PPC970_Unit_CRU;
280 } // neverHasSideEffects = 1
282 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
283 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
285 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
286 Requires<[In64BitMode]>;
287 let isTerminator = 1 in
288 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
289 "#EH_SJLJ_LONGJMP64",
290 [(PPCeh_sjlj_longjmp addr:$buf)]>,
291 Requires<[In64BitMode]>;
294 //===----------------------------------------------------------------------===//
295 // 64-bit SPR manipulation instrs.
297 let Uses = [CTR8] in {
298 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
299 "mfctr $rT", SprMFSPR>,
300 PPC970_DGroup_First, PPC970_Unit_FXU;
302 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
303 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
304 "mtctr $rS", SprMTSPR>,
305 PPC970_DGroup_First, PPC970_Unit_FXU;
307 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in {
308 let Pattern = [(int_ppc_mtctr i64:$rS)] in
309 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
310 "mtctr $rS", SprMTSPR>,
311 PPC970_DGroup_First, PPC970_Unit_FXU;
314 let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in
315 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
316 "mfspr $rT, 268", SprMFTB>,
317 PPC970_DGroup_First, PPC970_Unit_FXU;
318 // Note that encoding mftb using mfspr is now the preferred form,
319 // and has been since at least ISA v2.03. The mftb instruction has
320 // now been phased out. Using mfspr, however, is known not to work on
323 let Defs = [X1], Uses = [X1] in
324 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
326 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
328 let Defs = [LR8] in {
329 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
330 "mtlr $rS", SprMTSPR>,
331 PPC970_DGroup_First, PPC970_Unit_FXU;
333 let Uses = [LR8] in {
334 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
335 "mflr $rT", SprMFSPR>,
336 PPC970_DGroup_First, PPC970_Unit_FXU;
338 } // Interpretation64Bit
340 //===----------------------------------------------------------------------===//
341 // Fixed point instructions.
344 let PPC970_Unit = 1 in { // FXU Operations.
345 let Interpretation64Bit = 1 in {
346 let neverHasSideEffects = 1 in {
348 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
349 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
350 "li $rD, $imm", IntSimple,
351 [(set i64:$rD, imm64SExt16:$imm)]>;
352 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
353 "lis $rD, $imm", IntSimple,
354 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
358 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
359 "nand", "$rA, $rS, $rB", IntSimple,
360 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
361 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
362 "and", "$rA, $rS, $rB", IntSimple,
363 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
364 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
365 "andc", "$rA, $rS, $rB", IntSimple,
366 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
367 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
368 "or", "$rA, $rS, $rB", IntSimple,
369 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
370 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
371 "nor", "$rA, $rS, $rB", IntSimple,
372 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
373 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
374 "orc", "$rA, $rS, $rB", IntSimple,
375 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
376 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
377 "eqv", "$rA, $rS, $rB", IntSimple,
378 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
379 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
380 "xor", "$rA, $rS, $rB", IntSimple,
381 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
383 // Logical ops with immediate.
384 let Defs = [CR0] in {
385 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
386 "andi. $dst, $src1, $src2", IntGeneral,
387 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
389 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
390 "andis. $dst, $src1, $src2", IntGeneral,
391 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
394 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
395 "ori $dst, $src1, $src2", IntSimple,
396 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
397 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
398 "oris $dst, $src1, $src2", IntSimple,
399 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
400 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
401 "xori $dst, $src1, $src2", IntSimple,
402 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
403 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
404 "xoris $dst, $src1, $src2", IntSimple,
405 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
407 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
408 "add", "$rT, $rA, $rB", IntSimple,
409 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
410 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
411 // initial-exec thread-local storage model.
412 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
413 "add $rT, $rA, $rB", IntSimple,
414 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
416 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
417 "addc", "$rT, $rA, $rB", IntGeneral,
418 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
419 PPC970_DGroup_Cracked;
420 let Defs = [CARRY] in
421 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
422 "addic $rD, $rA, $imm", IntGeneral,
423 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
424 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
425 "addi $rD, $rA, $imm", IntSimple,
426 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
427 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
428 "addis $rD, $rA, $imm", IntSimple,
429 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
431 let Defs = [CARRY] in {
432 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
433 "subfic $rD, $rA, $imm", IntGeneral,
434 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
435 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
436 "subfc", "$rT, $rA, $rB", IntGeneral,
437 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
438 PPC970_DGroup_Cracked;
440 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
441 "subf", "$rT, $rA, $rB", IntGeneral,
442 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
443 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
444 "neg", "$rT, $rA", IntSimple,
445 [(set i64:$rT, (ineg i64:$rA))]>;
446 let Uses = [CARRY] in {
447 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
448 "adde", "$rT, $rA, $rB", IntGeneral,
449 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
450 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
451 "addme", "$rT, $rA", IntGeneral,
452 [(set i64:$rT, (adde i64:$rA, -1))]>;
453 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
454 "addze", "$rT, $rA", IntGeneral,
455 [(set i64:$rT, (adde i64:$rA, 0))]>;
456 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
457 "subfe", "$rT, $rA, $rB", IntGeneral,
458 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
459 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
460 "subfme", "$rT, $rA", IntGeneral,
461 [(set i64:$rT, (sube -1, i64:$rA))]>;
462 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
463 "subfze", "$rT, $rA", IntGeneral,
464 [(set i64:$rT, (sube 0, i64:$rA))]>;
468 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
469 "mulhd", "$rT, $rA, $rB", IntMulHW,
470 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
471 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
472 "mulhdu", "$rT, $rA, $rB", IntMulHWU,
473 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
475 } // Interpretation64Bit
477 let isCompare = 1, neverHasSideEffects = 1 in {
478 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
479 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
480 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
481 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
482 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
483 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
484 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
485 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
488 let neverHasSideEffects = 1 in {
489 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
490 "sld", "$rA, $rS, $rB", IntRotateD,
491 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
492 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
493 "srd", "$rA, $rS, $rB", IntRotateD,
494 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
495 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
496 "srad", "$rA, $rS, $rB", IntRotateD,
497 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
499 let Interpretation64Bit = 1 in {
500 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
501 "extsb", "$rA, $rS", IntSimple,
502 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
503 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
504 "extsh", "$rA, $rS", IntSimple,
505 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
506 } // Interpretation64Bit
508 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
509 "extsw", "$rA, $rS", IntSimple,
510 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
511 let Interpretation64Bit = 1 in
512 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
513 "extsw", "$rA, $rS", IntSimple,
514 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
516 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
517 "sradi", "$rA, $rS, $SH", IntRotateDI,
518 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
519 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
520 "cntlzd", "$rA, $rS", IntGeneral,
521 [(set i64:$rA, (ctlz i64:$rS))]>;
522 defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
523 "popcntd", "$rA, $rS", IntGeneral,
524 [(set i64:$rA, (ctpop i64:$rS))]>;
526 // popcntw also does a population count on the high 32 bits (storing the
527 // results in the high 32-bits of the output). We'll ignore that here (which is
528 // safe because we never separately use the high part of the 64-bit registers).
529 defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
530 "popcntw", "$rA, $rS", IntGeneral,
531 [(set i32:$rA, (ctpop i32:$rS))]>;
533 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
534 "divd", "$rT, $rA, $rB", IntDivD,
535 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
536 PPC970_DGroup_First, PPC970_DGroup_Cracked;
537 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
538 "divdu", "$rT, $rA, $rB", IntDivD,
539 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
540 PPC970_DGroup_First, PPC970_DGroup_Cracked;
541 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
542 "mulld", "$rT, $rA, $rB", IntMulHD,
543 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
546 let neverHasSideEffects = 1 in {
547 let isCommutable = 1 in {
548 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
549 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
550 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
551 []>, isPPC64, RegConstraint<"$rSi = $rA">,
555 // Rotate instructions.
556 defm RLDCL : MDSForm_1r<30, 8,
557 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
558 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
560 defm RLDCR : MDSForm_1r<30, 9,
561 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
562 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD,
564 defm RLDICL : MDForm_1r<30, 0,
565 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
566 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
568 defm RLDICR : MDForm_1r<30, 1,
569 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
570 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
572 defm RLDIC : MDForm_1r<30, 2,
573 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
574 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI,
577 let Interpretation64Bit = 1 in {
578 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
579 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
580 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
584 def ISEL8 : AForm_4<31, 15,
585 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
586 "isel $rT, $rA, $rB, $cond", IntGeneral,
588 } // Interpretation64Bit
589 } // neverHasSideEffects = 1
590 } // End FXU Operations.
593 //===----------------------------------------------------------------------===//
594 // Load/Store instructions.
598 // Sign extending loads.
599 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
600 let Interpretation64Bit = 1 in
601 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
602 "lha $rD, $src", LdStLHA,
603 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
604 PPC970_DGroup_Cracked;
605 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
606 "lwa $rD, $src", LdStLWA,
608 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
609 PPC970_DGroup_Cracked;
610 let Interpretation64Bit = 1 in
611 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
612 "lhax $rD, $src", LdStLHA,
613 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
614 PPC970_DGroup_Cracked;
615 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
616 "lwax $rD, $src", LdStLHA,
617 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
618 PPC970_DGroup_Cracked;
621 let mayLoad = 1, neverHasSideEffects = 1 in {
622 let Interpretation64Bit = 1 in
623 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
625 "lhau $rD, $addr", LdStLHAU,
626 []>, RegConstraint<"$addr.reg = $ea_result">,
627 NoEncode<"$ea_result">;
630 let Interpretation64Bit = 1 in
631 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
633 "lhaux $rD, $addr", LdStLHAU,
634 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
635 NoEncode<"$ea_result">;
636 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
638 "lwaux $rD, $addr", LdStLHAU,
639 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
640 NoEncode<"$ea_result">, isPPC64;
644 let Interpretation64Bit = 1 in {
645 // Zero extending loads.
646 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
647 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
648 "lbz $rD, $src", LdStLoad,
649 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
650 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
651 "lhz $rD, $src", LdStLoad,
652 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
653 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
654 "lwz $rD, $src", LdStLoad,
655 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
657 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
658 "lbzx $rD, $src", LdStLoad,
659 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
660 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
661 "lhzx $rD, $src", LdStLoad,
662 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
663 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
664 "lwzx $rD, $src", LdStLoad,
665 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
669 let mayLoad = 1, neverHasSideEffects = 1 in {
670 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
671 "lbzu $rD, $addr", LdStLoadUpd,
672 []>, RegConstraint<"$addr.reg = $ea_result">,
673 NoEncode<"$ea_result">;
674 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
675 "lhzu $rD, $addr", LdStLoadUpd,
676 []>, RegConstraint<"$addr.reg = $ea_result">,
677 NoEncode<"$ea_result">;
678 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
679 "lwzu $rD, $addr", LdStLoadUpd,
680 []>, RegConstraint<"$addr.reg = $ea_result">,
681 NoEncode<"$ea_result">;
683 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
685 "lbzux $rD, $addr", LdStLoadUpd,
686 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
687 NoEncode<"$ea_result">;
688 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
690 "lhzux $rD, $addr", LdStLoadUpd,
691 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
692 NoEncode<"$ea_result">;
693 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
695 "lwzux $rD, $addr", LdStLoadUpd,
696 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
697 NoEncode<"$ea_result">;
700 } // Interpretation64Bit
703 // Full 8-byte loads.
704 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
705 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
706 "ld $rD, $src", LdStLD,
707 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
708 // The following three definitions are selected for small code model only.
709 // Otherwise, we need to create two instructions to form a 32-bit offset,
710 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
711 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
714 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
715 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
718 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
719 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
722 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
724 let hasSideEffects = 1, isCodeGenOnly = 1 in {
725 let RST = 2, DS = 2 in
726 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
727 "ld 2, 8($reg)", LdStLD,
728 [(PPCload_toc i64:$reg)]>, isPPC64;
730 let RST = 2, DS = 10, RA = 1 in
731 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
732 "ld 2, 40(1)", LdStLD,
733 [(PPCtoc_restore)]>, isPPC64;
735 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
736 "ldx $rD, $src", LdStLD,
737 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
738 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
739 "ldbrx $rD, $src", LdStLoad,
740 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
742 let mayLoad = 1, neverHasSideEffects = 1 in {
743 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
744 "ldu $rD, $addr", LdStLDU,
745 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
746 NoEncode<"$ea_result">;
748 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
750 "ldux $rD, $addr", LdStLDU,
751 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
752 NoEncode<"$ea_result">, isPPC64;
756 def : Pat<(PPCload ixaddr:$src),
758 def : Pat<(PPCload xaddr:$src),
761 // Support for medium and large code model.
762 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
765 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
767 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
770 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
771 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
774 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
776 // Support for thread-local storage.
777 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
780 (PPCaddisGotTprelHA i64:$reg,
781 tglobaltlsaddr:$disp))]>,
783 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
786 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
788 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
789 (ADD8TLS $in, tglobaltlsaddr:$g)>;
790 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
793 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
795 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
798 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
800 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
803 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
805 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
808 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
810 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
813 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
815 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
818 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
820 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
823 (PPCaddisDtprelHA i64:$reg,
824 tglobaltlsaddr:$disp))]>,
826 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
829 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
832 let PPC970_Unit = 2 in {
833 let Interpretation64Bit = 1 in {
834 // Truncating stores.
835 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
836 "stb $rS, $src", LdStStore,
837 [(truncstorei8 i64:$rS, iaddr:$src)]>;
838 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
839 "sth $rS, $src", LdStStore,
840 [(truncstorei16 i64:$rS, iaddr:$src)]>;
841 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
842 "stw $rS, $src", LdStStore,
843 [(truncstorei32 i64:$rS, iaddr:$src)]>;
844 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
845 "stbx $rS, $dst", LdStStore,
846 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
847 PPC970_DGroup_Cracked;
848 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
849 "sthx $rS, $dst", LdStStore,
850 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
851 PPC970_DGroup_Cracked;
852 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
853 "stwx $rS, $dst", LdStStore,
854 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
855 PPC970_DGroup_Cracked;
856 } // Interpretation64Bit
858 // Normal 8-byte stores.
859 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
860 "std $rS, $dst", LdStSTD,
861 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
862 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
863 "stdx $rS, $dst", LdStSTD,
864 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
865 PPC970_DGroup_Cracked;
866 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
867 "stdbrx $rS, $dst", LdStStore,
868 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
869 PPC970_DGroup_Cracked;
872 // Stores with Update (pre-inc).
873 let PPC970_Unit = 2, mayStore = 1 in {
874 let Interpretation64Bit = 1 in {
875 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
876 "stbu $rS, $dst", LdStStoreUpd, []>,
877 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
878 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
879 "sthu $rS, $dst", LdStStoreUpd, []>,
880 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
881 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
882 "stwu $rS, $dst", LdStStoreUpd, []>,
883 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
884 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
885 "stdu $rS, $dst", LdStSTDU, []>,
886 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
889 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
890 "stbux $rS, $dst", LdStStoreUpd, []>,
891 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
892 PPC970_DGroup_Cracked;
893 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
894 "sthux $rS, $dst", LdStStoreUpd, []>,
895 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
896 PPC970_DGroup_Cracked;
897 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
898 "stwux $rS, $dst", LdStStoreUpd, []>,
899 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
900 PPC970_DGroup_Cracked;
901 } // Interpretation64Bit
903 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
904 "stdux $rS, $dst", LdStSTDU, []>,
905 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
906 PPC970_DGroup_Cracked, isPPC64;
909 // Patterns to match the pre-inc stores. We can't put the patterns on
910 // the instruction definitions directly as ISel wants the address base
911 // and offset to be separate operands, not a single complex operand.
912 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
913 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
914 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
915 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
916 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
917 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
918 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
919 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
921 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
922 (STBUX8 $rS, $ptrreg, $ptroff)>;
923 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
924 (STHUX8 $rS, $ptrreg, $ptroff)>;
925 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
926 (STWUX8 $rS, $ptrreg, $ptroff)>;
927 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
928 (STDUX $rS, $ptrreg, $ptroff)>;
931 //===----------------------------------------------------------------------===//
932 // Floating point instructions.
936 let PPC970_Unit = 3, neverHasSideEffects = 1,
937 Uses = [RM] in { // FPU Operations.
938 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
939 "fcfid", "$frD, $frB", FPGeneral,
940 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
941 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
942 "fctidz", "$frD, $frB", FPGeneral,
943 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
945 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
946 "fcfidu", "$frD, $frB", FPGeneral,
947 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
948 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
949 "fcfids", "$frD, $frB", FPGeneral,
950 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
951 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
952 "fcfidus", "$frD, $frB", FPGeneral,
953 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
954 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
955 "fctiduz", "$frD, $frB", FPGeneral,
956 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
957 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
958 "fctiwuz", "$frD, $frB", FPGeneral,
959 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
963 //===----------------------------------------------------------------------===//
964 // Instruction Patterns
967 // Extensions and truncates to/from 32-bit regs.
968 def : Pat<(i64 (zext i32:$in)),
969 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
971 def : Pat<(i64 (anyext i32:$in)),
972 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
973 def : Pat<(i32 (trunc i64:$in)),
974 (EXTRACT_SUBREG $in, sub_32)>;
976 // Extending loads with i64 targets.
977 def : Pat<(zextloadi1 iaddr:$src),
979 def : Pat<(zextloadi1 xaddr:$src),
981 def : Pat<(extloadi1 iaddr:$src),
983 def : Pat<(extloadi1 xaddr:$src),
985 def : Pat<(extloadi8 iaddr:$src),
987 def : Pat<(extloadi8 xaddr:$src),
989 def : Pat<(extloadi16 iaddr:$src),
991 def : Pat<(extloadi16 xaddr:$src),
993 def : Pat<(extloadi32 iaddr:$src),
995 def : Pat<(extloadi32 xaddr:$src),
998 // Standard shifts. These are represented separately from the real shifts above
999 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1001 def : Pat<(sra i64:$rS, i32:$rB),
1003 def : Pat<(srl i64:$rS, i32:$rB),
1005 def : Pat<(shl i64:$rS, i32:$rB),
1009 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1010 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1011 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1012 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1015 def : Pat<(rotl i64:$in, i32:$sh),
1016 (RLDCL $in, $sh, 0)>;
1017 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1018 (RLDICL $in, imm:$imm, 0)>;
1020 // Hi and Lo for Darwin Global Addresses.
1021 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1022 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1023 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1024 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1025 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1026 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1027 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1028 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1029 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1030 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1031 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1032 (ADDI8 $in, tglobaltlsaddr:$g)>;
1033 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1034 (ADDIS8 $in, tglobaladdr:$g)>;
1035 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1036 (ADDIS8 $in, tconstpool:$g)>;
1037 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1038 (ADDIS8 $in, tjumptable:$g)>;
1039 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1040 (ADDIS8 $in, tblockaddress:$g)>;
1042 // Patterns to match r+r indexed loads and stores for
1043 // addresses without at least 4-byte alignment.
1044 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1045 (LWAX xoaddr:$src)>;
1046 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1048 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1049 (STDX $rS, xoaddr:$dst)>;