1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue());
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
67 def HI32_48 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
72 def HI48_64 : SDNodeXForm<imm, [{
73 // Transformation function: shift the immediate value down into the low bits.
74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
78 //===----------------------------------------------------------------------===//
82 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
83 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
84 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
85 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
87 Requires<[In64BitMode]>;
88 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
89 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
91 Requires<[In64BitMode]>;
93 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
94 "bcctr 12, $bi, 0", IIC_BrB, []>,
95 Requires<[In64BitMode]>;
96 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
97 "bcctr 4, $bi, 0", IIC_BrB, []>,
98 Requires<[In64BitMode]>;
103 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
106 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
107 let Defs = [CTR8], Uses = [CTR8] in {
108 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
110 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
114 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
115 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
116 "bdzlr", IIC_BrB, []>;
117 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
118 "bdnzlr", IIC_BrB, []>;
124 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
125 // Convenient aliases for call instructions
127 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
128 "bl $func", IIC_BrB, []>; // See Pat patterns below.
130 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
131 "bl $func", IIC_BrB, []>;
133 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
134 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
136 let Uses = [RM], isCodeGenOnly = 1 in {
137 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
138 (outs), (ins calltarget:$func),
139 "bl $func\n\tnop", IIC_BrB, []>;
141 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
142 (outs), (ins tlscall:$func),
143 "bl $func\n\tnop", IIC_BrB, []>;
145 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
146 (outs), (ins abscalltarget:$func),
147 "bla $func\n\tnop", IIC_BrB,
148 [(PPCcall_nop (i64 imm:$func))]>;
150 let Uses = [CTR8, RM] in {
151 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
152 "bctrl", IIC_BrB, [(PPCbctrl)]>,
153 Requires<[In64BitMode]>;
155 let isCodeGenOnly = 1 in {
156 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
157 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
159 Requires<[In64BitMode]>;
161 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
162 "bcctrl 12, $bi, 0", IIC_BrB, []>,
163 Requires<[In64BitMode]>;
164 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
165 "bcctrl 4, $bi, 0", IIC_BrB, []>,
166 Requires<[In64BitMode]>;
170 } // Interpretation64Bit
172 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
173 // previous definition must be marked as CodeGen only to prevent decoding
175 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
176 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
177 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
178 "bl $func", IIC_BrB, []>;
181 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
182 (BL8 tglobaladdr:$dst)>;
183 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
184 (BL8_NOP tglobaladdr:$dst)>;
186 def : Pat<(PPCcall (i64 texternalsym:$dst)),
187 (BL8 texternalsym:$dst)>;
188 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
189 (BL8_NOP texternalsym:$dst)>;
191 def : Pat<(PPCcall_nop_tls texternalsym:$func, tglobaltlsaddr:$sym),
192 (BL8_NOP_TLS texternalsym:$func, tglobaltlsaddr:$sym)>;
195 let usesCustomInserter = 1 in {
196 let Defs = [CR0] in {
197 def ATOMIC_LOAD_ADD_I64 : Pseudo<
198 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
199 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
200 def ATOMIC_LOAD_SUB_I64 : Pseudo<
201 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
202 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
203 def ATOMIC_LOAD_OR_I64 : Pseudo<
204 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
205 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
206 def ATOMIC_LOAD_XOR_I64 : Pseudo<
207 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
208 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
209 def ATOMIC_LOAD_AND_I64 : Pseudo<
210 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
211 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
212 def ATOMIC_LOAD_NAND_I64 : Pseudo<
213 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
214 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
216 def ATOMIC_CMP_SWAP_I64 : Pseudo<
217 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
218 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
220 def ATOMIC_SWAP_I64 : Pseudo<
221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
222 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
226 // Instructions to support atomic operations
227 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
228 "ldarx $rD, $ptr", IIC_LdStLDARX,
229 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
232 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
233 "stdcx. $rS, $dst", IIC_LdStSTDCX,
234 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
237 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
238 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
239 def TCRETURNdi8 :Pseudo< (outs),
240 (ins calltarget:$dst, i32imm:$offset),
241 "#TC_RETURNd8 $dst $offset",
244 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
245 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
246 "#TC_RETURNa8 $func $offset",
247 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
249 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
250 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
251 "#TC_RETURNr8 $dst $offset",
254 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
255 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
256 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
258 Requires<[In64BitMode]>;
260 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
261 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
262 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
266 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
267 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
268 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
271 } // Interpretation64Bit
273 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
274 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
276 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
277 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
279 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
280 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
283 // 64-bit CR instructions
284 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
285 let neverHasSideEffects = 1 in {
286 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
287 "mtocrf $FXM, $ST", IIC_BrMCRX>,
288 PPC970_DGroup_First, PPC970_Unit_CRU;
290 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
291 "mtcrf $FXM, $rS", IIC_BrMCRX>,
292 PPC970_MicroCode, PPC970_Unit_CRU;
294 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
295 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
296 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
297 PPC970_DGroup_First, PPC970_Unit_CRU;
299 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
300 "mfcr $rT", IIC_SprMFCR>,
301 PPC970_MicroCode, PPC970_Unit_CRU;
302 } // neverHasSideEffects = 1
304 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
306 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
308 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
309 Requires<[In64BitMode]>;
310 let isTerminator = 1 in
311 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
312 "#EH_SJLJ_LONGJMP64",
313 [(PPCeh_sjlj_longjmp addr:$buf)]>,
314 Requires<[In64BitMode]>;
317 //===----------------------------------------------------------------------===//
318 // 64-bit SPR manipulation instrs.
320 let Uses = [CTR8] in {
321 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
322 "mfctr $rT", IIC_SprMFSPR>,
323 PPC970_DGroup_First, PPC970_Unit_FXU;
325 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
326 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
327 "mtctr $rS", IIC_SprMTSPR>,
328 PPC970_DGroup_First, PPC970_Unit_FXU;
330 let hasSideEffects = 1, Defs = [CTR8] in {
331 let Pattern = [(int_ppc_mtctr i64:$rS)] in
332 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
333 "mtctr $rS", IIC_SprMTSPR>,
334 PPC970_DGroup_First, PPC970_Unit_FXU;
337 let Pattern = [(set i64:$rT, readcyclecounter)] in
338 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
339 "mfspr $rT, 268", IIC_SprMFTB>,
340 PPC970_DGroup_First, PPC970_Unit_FXU;
341 // Note that encoding mftb using mfspr is now the preferred form,
342 // and has been since at least ISA v2.03. The mftb instruction has
343 // now been phased out. Using mfspr, however, is known not to work on
346 let Defs = [X1], Uses = [X1] in
347 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
349 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
351 let Defs = [LR8] in {
352 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
353 "mtlr $rS", IIC_SprMTSPR>,
354 PPC970_DGroup_First, PPC970_Unit_FXU;
356 let Uses = [LR8] in {
357 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
358 "mflr $rT", IIC_SprMFSPR>,
359 PPC970_DGroup_First, PPC970_Unit_FXU;
361 } // Interpretation64Bit
363 //===----------------------------------------------------------------------===//
364 // Fixed point instructions.
367 let PPC970_Unit = 1 in { // FXU Operations.
368 let Interpretation64Bit = 1 in {
369 let neverHasSideEffects = 1 in {
370 let isCodeGenOnly = 1 in {
372 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
373 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
374 "li $rD, $imm", IIC_IntSimple,
375 [(set i64:$rD, imm64SExt16:$imm)]>;
376 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
377 "lis $rD, $imm", IIC_IntSimple,
378 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
382 let isCommutable = 1 in {
383 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
384 "nand", "$rA, $rS, $rB", IIC_IntSimple,
385 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
386 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
387 "and", "$rA, $rS, $rB", IIC_IntSimple,
388 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
390 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
391 "andc", "$rA, $rS, $rB", IIC_IntSimple,
392 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
393 let isCommutable = 1 in {
394 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
395 "or", "$rA, $rS, $rB", IIC_IntSimple,
396 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
397 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
398 "nor", "$rA, $rS, $rB", IIC_IntSimple,
399 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
401 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
402 "orc", "$rA, $rS, $rB", IIC_IntSimple,
403 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
404 let isCommutable = 1 in {
405 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
406 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
407 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
408 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
409 "xor", "$rA, $rS, $rB", IIC_IntSimple,
410 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
411 } // let isCommutable = 1
413 // Logical ops with immediate.
414 let Defs = [CR0] in {
415 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
416 "andi. $dst, $src1, $src2", IIC_IntGeneral,
417 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
419 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
420 "andis. $dst, $src1, $src2", IIC_IntGeneral,
421 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
424 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
425 "ori $dst, $src1, $src2", IIC_IntSimple,
426 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
427 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
428 "oris $dst, $src1, $src2", IIC_IntSimple,
429 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
430 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
431 "xori $dst, $src1, $src2", IIC_IntSimple,
432 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
433 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
434 "xoris $dst, $src1, $src2", IIC_IntSimple,
435 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
437 let isCommutable = 1 in
438 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
439 "add", "$rT, $rA, $rB", IIC_IntSimple,
440 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
441 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
442 // initial-exec thread-local storage model.
443 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
444 "add $rT, $rA, $rB", IIC_IntSimple,
445 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
447 let isCommutable = 1 in
448 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
449 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
450 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
451 PPC970_DGroup_Cracked;
453 let Defs = [CARRY] in
454 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
455 "addic $rD, $rA, $imm", IIC_IntGeneral,
456 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
457 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
458 "addi $rD, $rA, $imm", IIC_IntSimple,
459 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
460 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
461 "addis $rD, $rA, $imm", IIC_IntSimple,
462 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
464 let Defs = [CARRY] in {
465 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
466 "subfic $rD, $rA, $imm", IIC_IntGeneral,
467 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
468 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
469 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
470 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
471 PPC970_DGroup_Cracked;
473 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
474 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
475 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
476 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
477 "neg", "$rT, $rA", IIC_IntSimple,
478 [(set i64:$rT, (ineg i64:$rA))]>;
479 let Uses = [CARRY] in {
480 let isCommutable = 1 in
481 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
482 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
483 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
484 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
485 "addme", "$rT, $rA", IIC_IntGeneral,
486 [(set i64:$rT, (adde i64:$rA, -1))]>;
487 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
488 "addze", "$rT, $rA", IIC_IntGeneral,
489 [(set i64:$rT, (adde i64:$rA, 0))]>;
490 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
491 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
492 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
493 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
494 "subfme", "$rT, $rA", IIC_IntGeneral,
495 [(set i64:$rT, (sube -1, i64:$rA))]>;
496 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
497 "subfze", "$rT, $rA", IIC_IntGeneral,
498 [(set i64:$rT, (sube 0, i64:$rA))]>;
502 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
503 // previous definition must be marked as CodeGen only to prevent decoding
505 let isAsmParserOnly = 1 in
506 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
507 "add $rT, $rA, $rB", IIC_IntSimple, []>;
509 let isCommutable = 1 in {
510 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
511 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
512 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
513 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
514 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
515 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
518 } // Interpretation64Bit
520 let isCompare = 1, neverHasSideEffects = 1 in {
521 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
522 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
523 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
524 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
525 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
526 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
527 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
528 "cmpldi $dst, $src1, $src2",
529 IIC_IntCompare>, isPPC64;
532 let neverHasSideEffects = 1 in {
533 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
534 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
535 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
536 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
537 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
538 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
539 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
540 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
541 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
543 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
544 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
545 "extsb", "$rA, $rS", IIC_IntSimple,
546 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
547 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
548 "extsh", "$rA, $rS", IIC_IntSimple,
549 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
550 } // Interpretation64Bit
553 let isCodeGenOnly = 1 in {
554 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
555 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
556 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
557 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
558 } // isCodeGenOnly for fast-isel
560 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
561 "extsw", "$rA, $rS", IIC_IntSimple,
562 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
563 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
564 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
565 "extsw", "$rA, $rS", IIC_IntSimple,
566 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
568 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
569 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
570 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
571 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
572 "cntlzd", "$rA, $rS", IIC_IntGeneral,
573 [(set i64:$rA, (ctlz i64:$rS))]>;
574 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
575 "popcntd $rA, $rS", IIC_IntGeneral,
576 [(set i64:$rA, (ctpop i64:$rS))]>;
578 // popcntw also does a population count on the high 32 bits (storing the
579 // results in the high 32-bits of the output). We'll ignore that here (which is
580 // safe because we never separately use the high part of the 64-bit registers).
581 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
582 "popcntw $rA, $rS", IIC_IntGeneral,
583 [(set i32:$rA, (ctpop i32:$rS))]>;
585 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
586 "divd", "$rT, $rA, $rB", IIC_IntDivD,
587 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
588 PPC970_DGroup_First, PPC970_DGroup_Cracked;
589 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
590 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
591 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
592 PPC970_DGroup_First, PPC970_DGroup_Cracked;
593 let isCommutable = 1 in
594 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
595 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
596 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
597 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
598 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
599 "mulli $rD, $rA, $imm", IIC_IntMulLI,
600 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
603 let neverHasSideEffects = 1 in {
604 let isCommutable = 1 in {
605 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
606 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
607 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
608 []>, isPPC64, RegConstraint<"$rSi = $rA">,
612 // Rotate instructions.
613 defm RLDCL : MDSForm_1r<30, 8,
614 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
615 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
617 defm RLDCR : MDSForm_1r<30, 9,
618 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
619 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
621 defm RLDICL : MDForm_1r<30, 0,
622 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
623 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
626 let isCodeGenOnly = 1 in
627 def RLDICL_32_64 : MDForm_1<30, 0,
629 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
630 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
633 defm RLDICR : MDForm_1r<30, 1,
634 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
635 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
637 defm RLDIC : MDForm_1r<30, 2,
638 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
639 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
642 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
643 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
644 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
645 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
648 let isCommutable = 1 in {
649 // RLWIMI can be commuted if the rotate amount is zero.
650 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
651 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
652 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
653 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
654 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
655 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
659 def ISEL8 : AForm_4<31, 15,
660 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
661 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
663 } // Interpretation64Bit
664 } // neverHasSideEffects = 1
665 } // End FXU Operations.
668 //===----------------------------------------------------------------------===//
669 // Load/Store instructions.
673 // Sign extending loads.
674 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
675 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
676 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
677 "lha $rD, $src", IIC_LdStLHA,
678 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
679 PPC970_DGroup_Cracked;
680 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
681 "lwa $rD, $src", IIC_LdStLWA,
683 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
684 PPC970_DGroup_Cracked;
685 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
686 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
687 "lhax $rD, $src", IIC_LdStLHA,
688 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
689 PPC970_DGroup_Cracked;
690 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
691 "lwax $rD, $src", IIC_LdStLHA,
692 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
693 PPC970_DGroup_Cracked;
695 let isCodeGenOnly = 1, mayLoad = 1 in {
696 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
697 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
698 PPC970_DGroup_Cracked;
699 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
700 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
701 PPC970_DGroup_Cracked;
702 } // end fast-isel isCodeGenOnly
705 let mayLoad = 1, neverHasSideEffects = 1 in {
706 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
707 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
709 "lhau $rD, $addr", IIC_LdStLHAU,
710 []>, RegConstraint<"$addr.reg = $ea_result">,
711 NoEncode<"$ea_result">;
714 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
715 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
717 "lhaux $rD, $addr", IIC_LdStLHAUX,
718 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
719 NoEncode<"$ea_result">;
720 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
722 "lwaux $rD, $addr", IIC_LdStLHAUX,
723 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
724 NoEncode<"$ea_result">, isPPC64;
728 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
729 // Zero extending loads.
730 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
731 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
732 "lbz $rD, $src", IIC_LdStLoad,
733 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
734 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
735 "lhz $rD, $src", IIC_LdStLoad,
736 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
737 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
738 "lwz $rD, $src", IIC_LdStLoad,
739 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
741 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
742 "lbzx $rD, $src", IIC_LdStLoad,
743 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
744 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
745 "lhzx $rD, $src", IIC_LdStLoad,
746 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
747 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
748 "lwzx $rD, $src", IIC_LdStLoad,
749 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
753 let mayLoad = 1, neverHasSideEffects = 1 in {
754 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
755 "lbzu $rD, $addr", IIC_LdStLoadUpd,
756 []>, RegConstraint<"$addr.reg = $ea_result">,
757 NoEncode<"$ea_result">;
758 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
759 "lhzu $rD, $addr", IIC_LdStLoadUpd,
760 []>, RegConstraint<"$addr.reg = $ea_result">,
761 NoEncode<"$ea_result">;
762 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
763 "lwzu $rD, $addr", IIC_LdStLoadUpd,
764 []>, RegConstraint<"$addr.reg = $ea_result">,
765 NoEncode<"$ea_result">;
767 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
769 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
770 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
771 NoEncode<"$ea_result">;
772 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
774 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
775 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
776 NoEncode<"$ea_result">;
777 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
779 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
780 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
781 NoEncode<"$ea_result">;
784 } // Interpretation64Bit
787 // Full 8-byte loads.
788 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
789 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
790 "ld $rD, $src", IIC_LdStLD,
791 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
792 // The following four definitions are selected for small code model only.
793 // Otherwise, we need to create two instructions to form a 32-bit offset,
794 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
795 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
798 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
799 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
802 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
803 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
806 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
807 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
810 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
812 let hasSideEffects = 1, isCodeGenOnly = 1, RST = 2, Defs = [X2] in
813 def LDinto_toc: DSForm_1<58, 0, (outs), (ins memrix:$src),
814 "ld 2, $src", IIC_LdStLD,
815 [(PPCload_toc ixaddr:$src)]>, isPPC64;
817 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
818 "ldx $rD, $src", IIC_LdStLD,
819 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
820 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
821 "ldbrx $rD, $src", IIC_LdStLoad,
822 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
824 let mayLoad = 1, neverHasSideEffects = 1 in {
825 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
826 "ldu $rD, $addr", IIC_LdStLDU,
827 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
828 NoEncode<"$ea_result">;
830 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
832 "ldux $rD, $addr", IIC_LdStLDUX,
833 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
834 NoEncode<"$ea_result">, isPPC64;
838 def : Pat<(PPCload ixaddr:$src),
840 def : Pat<(PPCload xaddr:$src),
843 // Support for medium and large code model.
844 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
847 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
849 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
852 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
853 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
856 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
858 // Support for thread-local storage.
859 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
862 (PPCaddisGotTprelHA i64:$reg,
863 tglobaltlsaddr:$disp))]>,
865 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
868 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
870 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
871 (ADD8TLS $in, tglobaltlsaddr:$g)>;
872 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
875 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
877 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
880 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
882 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
885 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
887 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
890 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
892 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
895 (PPCaddisDtprelHA i64:$reg,
896 tglobaltlsaddr:$disp))]>,
898 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
901 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
904 let PPC970_Unit = 2 in {
905 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
906 // Truncating stores.
907 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
908 "stb $rS, $src", IIC_LdStStore,
909 [(truncstorei8 i64:$rS, iaddr:$src)]>;
910 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
911 "sth $rS, $src", IIC_LdStStore,
912 [(truncstorei16 i64:$rS, iaddr:$src)]>;
913 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
914 "stw $rS, $src", IIC_LdStStore,
915 [(truncstorei32 i64:$rS, iaddr:$src)]>;
916 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
917 "stbx $rS, $dst", IIC_LdStStore,
918 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
919 PPC970_DGroup_Cracked;
920 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
921 "sthx $rS, $dst", IIC_LdStStore,
922 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
923 PPC970_DGroup_Cracked;
924 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
925 "stwx $rS, $dst", IIC_LdStStore,
926 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
927 PPC970_DGroup_Cracked;
928 } // Interpretation64Bit
930 // Normal 8-byte stores.
931 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
932 "std $rS, $dst", IIC_LdStSTD,
933 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
934 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
935 "stdx $rS, $dst", IIC_LdStSTD,
936 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
937 PPC970_DGroup_Cracked;
938 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
939 "stdbrx $rS, $dst", IIC_LdStStore,
940 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
941 PPC970_DGroup_Cracked;
944 // Stores with Update (pre-inc).
945 let PPC970_Unit = 2, mayStore = 1 in {
946 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
947 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
948 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
949 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
950 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
951 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
952 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
953 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
954 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
955 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
957 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
958 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
959 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
960 PPC970_DGroup_Cracked;
961 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
962 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
963 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
964 PPC970_DGroup_Cracked;
965 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
966 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
967 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
968 PPC970_DGroup_Cracked;
969 } // Interpretation64Bit
971 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
972 "stdu $rS, $dst", IIC_LdStSTDU, []>,
973 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
976 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
977 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
978 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
979 PPC970_DGroup_Cracked, isPPC64;
982 // Patterns to match the pre-inc stores. We can't put the patterns on
983 // the instruction definitions directly as ISel wants the address base
984 // and offset to be separate operands, not a single complex operand.
985 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
986 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
987 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
988 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
989 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
990 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
991 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
992 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
994 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
995 (STBUX8 $rS, $ptrreg, $ptroff)>;
996 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
997 (STHUX8 $rS, $ptrreg, $ptroff)>;
998 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
999 (STWUX8 $rS, $ptrreg, $ptroff)>;
1000 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1001 (STDUX $rS, $ptrreg, $ptroff)>;
1004 //===----------------------------------------------------------------------===//
1005 // Floating point instructions.
1009 let PPC970_Unit = 3, neverHasSideEffects = 1,
1010 Uses = [RM] in { // FPU Operations.
1011 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
1012 "fcfid", "$frD, $frB", IIC_FPGeneral,
1013 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
1014 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
1015 "fctid", "$frD, $frB", IIC_FPGeneral,
1017 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
1018 "fctidz", "$frD, $frB", IIC_FPGeneral,
1019 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1021 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
1022 "fcfidu", "$frD, $frB", IIC_FPGeneral,
1023 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
1024 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1025 "fcfids", "$frD, $frB", IIC_FPGeneral,
1026 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1027 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1028 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1029 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1030 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1031 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1032 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1033 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1034 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1035 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1039 //===----------------------------------------------------------------------===//
1040 // Instruction Patterns
1043 // Extensions and truncates to/from 32-bit regs.
1044 def : Pat<(i64 (zext i32:$in)),
1045 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1047 def : Pat<(i64 (anyext i32:$in)),
1048 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1049 def : Pat<(i32 (trunc i64:$in)),
1050 (EXTRACT_SUBREG $in, sub_32)>;
1052 // Implement the 'not' operation with the NOR instruction.
1053 // (we could use the default xori pattern, but nor has lower latency on some
1054 // cores (such as the A2)).
1055 def i64not : OutPatFrag<(ops node:$in),
1057 def : Pat<(not i64:$in),
1060 // Extending loads with i64 targets.
1061 def : Pat<(zextloadi1 iaddr:$src),
1063 def : Pat<(zextloadi1 xaddr:$src),
1064 (LBZX8 xaddr:$src)>;
1065 def : Pat<(extloadi1 iaddr:$src),
1067 def : Pat<(extloadi1 xaddr:$src),
1068 (LBZX8 xaddr:$src)>;
1069 def : Pat<(extloadi8 iaddr:$src),
1071 def : Pat<(extloadi8 xaddr:$src),
1072 (LBZX8 xaddr:$src)>;
1073 def : Pat<(extloadi16 iaddr:$src),
1075 def : Pat<(extloadi16 xaddr:$src),
1076 (LHZX8 xaddr:$src)>;
1077 def : Pat<(extloadi32 iaddr:$src),
1079 def : Pat<(extloadi32 xaddr:$src),
1080 (LWZX8 xaddr:$src)>;
1082 // Standard shifts. These are represented separately from the real shifts above
1083 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1085 def : Pat<(sra i64:$rS, i32:$rB),
1087 def : Pat<(srl i64:$rS, i32:$rB),
1089 def : Pat<(shl i64:$rS, i32:$rB),
1093 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1094 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1095 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1096 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1099 def : Pat<(rotl i64:$in, i32:$sh),
1100 (RLDCL $in, $sh, 0)>;
1101 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1102 (RLDICL $in, imm:$imm, 0)>;
1104 // Hi and Lo for Darwin Global Addresses.
1105 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1106 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1107 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1108 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1109 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1110 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1111 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1112 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1113 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1114 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1115 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1116 (ADDI8 $in, tglobaltlsaddr:$g)>;
1117 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1118 (ADDIS8 $in, tglobaladdr:$g)>;
1119 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1120 (ADDIS8 $in, tconstpool:$g)>;
1121 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1122 (ADDIS8 $in, tjumptable:$g)>;
1123 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1124 (ADDIS8 $in, tblockaddress:$g)>;
1126 // Patterns to match r+r indexed loads and stores for
1127 // addresses without at least 4-byte alignment.
1128 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1129 (LWAX xoaddr:$src)>;
1130 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1132 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1133 (STDX $rS, xoaddr:$dst)>;
1135 // 64-bits atomic loads and stores
1136 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>;
1137 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>;
1139 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>;
1140 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>;