1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
32 def tocentry : Operand<iPTR> {
33 let MIOperandInfo = (ops i32imm:$imm);
36 //===----------------------------------------------------------------------===//
37 // 64-bit transformation functions.
40 def SHL64 : SDNodeXForm<imm, [{
41 // Transformation function: 63 - imm
42 return getI32Imm(63 - N->getZExtValue());
45 def SRL64 : SDNodeXForm<imm, [{
46 // Transformation function: 64 - imm
47 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
50 def HI32_48 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
55 def HI48_64 : SDNodeXForm<imm, [{
56 // Transformation function: shift the immediate value down into the low bits.
57 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
61 //===----------------------------------------------------------------------===//
66 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
70 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
71 // Convenient aliases for call instructions
73 def BL8_Darwin : IForm<18, 0, 1,
74 (outs), (ins calltarget:$func),
75 "bl $func", BrB, []>; // See Pat patterns below.
76 def BLA8_Darwin : IForm<18, 1, 1,
77 (outs), (ins aaddr:$func),
78 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>;
80 let Uses = [CTR8, RM] in {
81 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
84 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>;
88 // ELF 64 ABI Calls = Darwin ABI Calls
89 // Used to define BL8_ELF and BLA8_ELF
90 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
91 // Convenient aliases for call instructions
93 def BL8_ELF : IForm<18, 0, 1,
94 (outs), (ins calltarget:$func),
95 "bl $func", BrB, []>; // See Pat patterns below.
97 let isCodeGenOnly = 1 in
98 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24,
99 (outs), (ins calltarget:$func),
100 "bl $func\n\tnop", BrB, []>;
102 def BLA8_ELF : IForm<18, 1, 1,
103 (outs), (ins aaddr:$func),
104 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>;
106 let isCodeGenOnly = 1 in
107 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24,
108 (outs), (ins aaddr:$func),
109 "bla $func\n\tnop", BrB,
110 [(PPCcall_nop_SVR4 (i64 imm:$func))]>;
112 let Uses = [X11, CTR8, RM] in {
113 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
116 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>;
122 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
123 (BL8_Darwin tglobaladdr:$dst)>;
124 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
125 (BL8_Darwin texternalsym:$dst)>;
127 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
128 (BL8_ELF tglobaladdr:$dst)>;
129 def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)),
130 (BL8_NOP_ELF tglobaladdr:$dst)>;
132 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
133 (BL8_ELF texternalsym:$dst)>;
134 def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)),
135 (BL8_NOP_ELF texternalsym:$dst)>;
141 let usesCustomInserter = 1 in {
142 let Defs = [CR0] in {
143 def ATOMIC_LOAD_ADD_I64 : Pseudo<
144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
145 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
146 def ATOMIC_LOAD_SUB_I64 : Pseudo<
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
148 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
149 def ATOMIC_LOAD_OR_I64 : Pseudo<
150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
151 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
152 def ATOMIC_LOAD_XOR_I64 : Pseudo<
153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
154 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
155 def ATOMIC_LOAD_AND_I64 : Pseudo<
156 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
157 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
158 def ATOMIC_LOAD_NAND_I64 : Pseudo<
159 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
160 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
162 def ATOMIC_CMP_SWAP_I64 : Pseudo<
163 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
165 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
167 def ATOMIC_SWAP_I64 : Pseudo<
168 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
169 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
173 // Instructions to support atomic operations
174 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
175 "ldarx $rD, $ptr", LdStLDARX,
176 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
179 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
180 "stdcx. $rS, $dst", LdStSTDCX,
181 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
185 def TCRETURNdi8 :Pseudo< (outs),
186 (ins calltarget:$dst, i32imm:$offset),
187 "#TC_RETURNd8 $dst $offset",
190 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
191 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
192 "#TC_RETURNa8 $func $offset",
193 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
195 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
196 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
197 "#TC_RETURNr8 $dst $offset",
201 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
202 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in {
203 let isReturn = 1 in {
204 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
205 Requires<[In64BitMode]>;
208 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
209 Requires<[In64BitMode]>;
213 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
214 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
215 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
220 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
221 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
222 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
226 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
227 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
229 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
230 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
232 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
233 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
235 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
236 let Defs = [CTR8], Uses = [CTR8] in {
237 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
239 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
244 // 64-but CR instructions
245 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
246 "mtcrf $FXM, $rS", BrMCRX>,
247 PPC970_MicroCode, PPC970_Unit_CRU;
249 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
250 "#MFCR8pseud", SprMFCR>,
251 PPC970_MicroCode, PPC970_Unit_CRU;
253 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
254 "mfcr $rT", SprMFCR>,
255 PPC970_MicroCode, PPC970_Unit_CRU;
257 //===----------------------------------------------------------------------===//
258 // 64-bit SPR manipulation instrs.
260 let Uses = [CTR8] in {
261 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
262 "mfctr $rT", SprMFSPR>,
263 PPC970_DGroup_First, PPC970_Unit_FXU;
265 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in {
266 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
267 "mtctr $rS", SprMTSPR>,
268 PPC970_DGroup_First, PPC970_Unit_FXU;
271 let Pattern = [(set G8RC:$rT, readcyclecounter)] in
272 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
273 "mfspr $rT, 268", SprMFTB>,
274 PPC970_DGroup_First, PPC970_Unit_FXU;
275 // Note that encoding mftb using mfspr is now the preferred form,
276 // and has been since at least ISA v2.03. The mftb instruction has
277 // now been phased out. Using mfspr, however, is known not to work on
280 let Defs = [X1], Uses = [X1] in
281 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
283 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
285 let Defs = [LR8] in {
286 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
287 "mtlr $rS", SprMTSPR>,
288 PPC970_DGroup_First, PPC970_Unit_FXU;
290 let Uses = [LR8] in {
291 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
292 "mflr $rT", SprMFSPR>,
293 PPC970_DGroup_First, PPC970_Unit_FXU;
296 //===----------------------------------------------------------------------===//
297 // Fixed point instructions.
300 let PPC970_Unit = 1 in { // FXU Operations.
302 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
303 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
304 "li $rD, $imm", IntSimple,
305 [(set G8RC:$rD, immSExt16:$imm)]>;
306 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
307 "lis $rD, $imm", IntSimple,
308 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
312 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
313 "nand $rA, $rS, $rB", IntSimple,
314 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
315 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
316 "and $rA, $rS, $rB", IntSimple,
317 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
318 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
319 "andc $rA, $rS, $rB", IntSimple,
320 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
321 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
322 "or $rA, $rS, $rB", IntSimple,
323 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
324 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
325 "nor $rA, $rS, $rB", IntSimple,
326 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
327 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
328 "orc $rA, $rS, $rB", IntSimple,
329 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
330 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
331 "eqv $rA, $rS, $rB", IntSimple,
332 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
333 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
334 "xor $rA, $rS, $rB", IntSimple,
335 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
337 // Logical ops with immediate.
338 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
339 "andi. $dst, $src1, $src2", IntGeneral,
340 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
342 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
343 "andis. $dst, $src1, $src2", IntGeneral,
344 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
346 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
347 "ori $dst, $src1, $src2", IntSimple,
348 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
349 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
350 "oris $dst, $src1, $src2", IntSimple,
351 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
352 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
353 "xori $dst, $src1, $src2", IntSimple,
354 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
355 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
356 "xoris $dst, $src1, $src2", IntSimple,
357 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
359 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
360 "add $rT, $rA, $rB", IntSimple,
361 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
363 let Defs = [CARRY] in {
364 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
365 "addc $rT, $rA, $rB", IntGeneral,
366 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
367 PPC970_DGroup_Cracked;
368 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
369 "addic $rD, $rA, $imm", IntGeneral,
370 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
372 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
373 "addi $rD, $rA, $imm", IntSimple,
374 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
375 def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, symbolLo64:$imm),
376 "addi $rD, $rA, $imm", IntSimple,
377 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
378 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
379 "addis $rD, $rA, $imm", IntSimple,
380 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
382 let Defs = [CARRY] in {
383 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
384 "subfic $rD, $rA, $imm", IntGeneral,
385 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
386 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
387 "subfc $rT, $rA, $rB", IntGeneral,
388 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
389 PPC970_DGroup_Cracked;
391 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
392 "subf $rT, $rA, $rB", IntGeneral,
393 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
394 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
395 "neg $rT, $rA", IntSimple,
396 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
397 let Uses = [CARRY], Defs = [CARRY] in {
398 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
399 "adde $rT, $rA, $rB", IntGeneral,
400 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
401 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
402 "addme $rT, $rA", IntGeneral,
403 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>;
404 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
405 "addze $rT, $rA", IntGeneral,
406 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
407 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
408 "subfe $rT, $rA, $rB", IntGeneral,
409 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
410 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
411 "subfme $rT, $rA", IntGeneral,
412 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>;
413 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
414 "subfze $rT, $rA", IntGeneral,
415 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
419 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
420 "mulhd $rT, $rA, $rB", IntMulHW,
421 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
422 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
423 "mulhdu $rT, $rA, $rB", IntMulHWU,
424 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
426 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
427 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
428 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
429 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
430 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
431 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
432 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
433 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
435 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
436 "sld $rA, $rS, $rB", IntRotateD,
437 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
438 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
439 "srd $rA, $rS, $rB", IntRotateD,
440 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
441 let Defs = [CARRY] in {
442 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
443 "srad $rA, $rS, $rB", IntRotateD,
444 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
447 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
448 "extsb $rA, $rS", IntSimple,
449 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
450 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
451 "extsh $rA, $rS", IntSimple,
452 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
454 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
455 "extsw $rA, $rS", IntSimple,
456 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
457 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
458 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
459 "extsw $rA, $rS", IntSimple,
460 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
461 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
462 "extsw $rA, $rS", IntSimple,
463 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
465 let Defs = [CARRY] in {
466 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
467 "sradi $rA, $rS, $SH", IntRotateDI,
468 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
470 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
471 "cntlzd $rA, $rS", IntGeneral,
472 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
474 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
475 "divd $rT, $rA, $rB", IntDivD,
476 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
477 PPC970_DGroup_First, PPC970_DGroup_Cracked;
478 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
479 "divdu $rT, $rA, $rB", IntDivD,
480 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
481 PPC970_DGroup_First, PPC970_DGroup_Cracked;
482 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
483 "mulld $rT, $rA, $rB", IntMulHD,
484 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
487 let isCommutable = 1 in {
488 def RLDIMI : MDForm_1<30, 3,
489 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
490 "rldimi $rA, $rS, $SH, $MB", IntRotateDI,
491 []>, isPPC64, RegConstraint<"$rSi = $rA">,
495 // Rotate instructions.
496 def RLDCL : MDForm_1<30, 0,
497 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
498 "rldcl $rA, $rS, $rB, $MBE", IntRotateD,
500 def RLDICL : MDForm_1<30, 0,
501 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
502 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
504 def RLDICR : MDForm_1<30, 1,
505 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
506 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI,
509 def RLWINM8 : MForm_2<21,
510 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
511 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
514 def ISEL8 : AForm_4<31, 15,
515 (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB, pred:$cond),
516 "isel $rT, $rA, $rB, $cond", IntGeneral,
518 } // End FXU Operations.
521 //===----------------------------------------------------------------------===//
522 // Load/Store instructions.
526 // Sign extending loads.
527 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
528 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
529 "lha $rD, $src", LdStLHA,
530 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
531 PPC970_DGroup_Cracked;
532 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
533 "lwa $rD, $src", LdStLWA,
534 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
535 PPC970_DGroup_Cracked;
536 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
537 "lhax $rD, $src", LdStLHA,
538 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
539 PPC970_DGroup_Cracked;
540 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
541 "lwax $rD, $src", LdStLHA,
542 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
543 PPC970_DGroup_Cracked;
547 def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
549 "lhau $rD, $disp($rA)", LdStLHAU,
550 []>, RegConstraint<"$rA = $ea_result">,
551 NoEncode<"$ea_result">;
554 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result),
556 "lhaux $rD, $addr", LdStLHAU,
557 []>, RegConstraint<"$addr.offreg = $ea_result">,
558 NoEncode<"$ea_result">;
559 def LWAUX : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result),
561 "lwaux $rD, $addr", LdStLHAU,
562 []>, RegConstraint<"$addr.offreg = $ea_result">,
563 NoEncode<"$ea_result">, isPPC64;
566 // Zero extending loads.
567 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
568 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
569 "lbz $rD, $src", LdStLoad,
570 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
571 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
572 "lhz $rD, $src", LdStLoad,
573 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
574 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
575 "lwz $rD, $src", LdStLoad,
576 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
578 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
579 "lbzx $rD, $src", LdStLoad,
580 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
581 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
582 "lhzx $rD, $src", LdStLoad,
583 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
584 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
585 "lwzx $rD, $src", LdStLoad,
586 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
591 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
592 "lbzu $rD, $addr", LdStLoadUpd,
593 []>, RegConstraint<"$addr.reg = $ea_result">,
594 NoEncode<"$ea_result">;
595 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
596 "lhzu $rD, $addr", LdStLoadUpd,
597 []>, RegConstraint<"$addr.reg = $ea_result">,
598 NoEncode<"$ea_result">;
599 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
600 "lwzu $rD, $addr", LdStLoadUpd,
601 []>, RegConstraint<"$addr.reg = $ea_result">,
602 NoEncode<"$ea_result">;
604 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc:$ea_result),
606 "lbzux $rD, $addr", LdStLoadUpd,
607 []>, RegConstraint<"$addr.offreg = $ea_result">,
608 NoEncode<"$ea_result">;
609 def LHZUX8 : XForm_1<31, 331, (outs G8RC:$rD, ptr_rc:$ea_result),
611 "lhzux $rD, $addr", LdStLoadUpd,
612 []>, RegConstraint<"$addr.offreg = $ea_result">,
613 NoEncode<"$ea_result">;
614 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc:$ea_result),
616 "lwzux $rD, $addr", LdStLoadUpd,
617 []>, RegConstraint<"$addr.offreg = $ea_result">,
618 NoEncode<"$ea_result">;
623 // Full 8-byte loads.
624 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
625 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
626 "ld $rD, $src", LdStLD,
627 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
628 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
631 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
632 def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
635 (PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64;
636 def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
639 (PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64;
641 let hasSideEffects = 1 in {
642 let RST = 2, DS = 2 in
643 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
644 "ld 2, 8($reg)", LdStLD,
645 [(PPCload_toc G8RC:$reg)]>, isPPC64;
647 let RST = 2, DS = 10, RA = 1 in
648 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
649 "ld 2, 40(1)", LdStLD,
650 [(PPCtoc_restore)]>, isPPC64;
652 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
653 "ldx $rD, $src", LdStLD,
654 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
657 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
658 "ldu $rD, $addr", LdStLDU,
659 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
660 NoEncode<"$ea_result">;
662 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc:$ea_result),
664 "ldux $rD, $addr", LdStLDU,
665 []>, RegConstraint<"$addr.offreg = $ea_result">,
666 NoEncode<"$ea_result">, isPPC64;
669 def : Pat<(PPCload ixaddr:$src),
671 def : Pat<(PPCload xaddr:$src),
674 let PPC970_Unit = 2 in {
675 // Truncating stores.
676 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
677 "stb $rS, $src", LdStStore,
678 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
679 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
680 "sth $rS, $src", LdStStore,
681 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
682 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
683 "stw $rS, $src", LdStStore,
684 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
685 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
686 "stbx $rS, $dst", LdStStore,
687 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
688 PPC970_DGroup_Cracked;
689 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
690 "sthx $rS, $dst", LdStStore,
691 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
692 PPC970_DGroup_Cracked;
693 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
694 "stwx $rS, $dst", LdStStore,
695 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
696 PPC970_DGroup_Cracked;
697 // Normal 8-byte stores.
698 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
699 "std $rS, $dst", LdStSTD,
700 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
701 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
702 "stdx $rS, $dst", LdStSTD,
703 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
704 PPC970_DGroup_Cracked;
707 let PPC970_Unit = 2 in {
709 def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
710 symbolLo:$ptroff, ptr_rc:$ptrreg),
711 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
712 [(set ptr_rc:$ea_res,
713 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
714 iaddroff:$ptroff))]>,
715 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
716 def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
717 symbolLo:$ptroff, ptr_rc:$ptrreg),
718 "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd,
719 [(set ptr_rc:$ea_res,
720 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
721 iaddroff:$ptroff))]>,
722 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
724 def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
725 symbolLo:$ptroff, ptr_rc:$ptrreg),
726 "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd,
727 [(set ptr_rc:$ea_res,
728 (pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg,
729 iaddroff:$ptroff))]>,
730 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
732 def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
733 s16immX4:$ptroff, ptr_rc:$ptrreg),
734 "stdu $rS, $ptroff($ptrreg)", LdStSTDU,
735 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
736 iaddroff:$ptroff))]>,
737 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
741 def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res),
742 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
743 "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd,
744 [(set ptr_rc:$ea_res,
745 (pre_truncsti8 G8RC:$rS,
746 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
747 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
748 PPC970_DGroup_Cracked;
750 def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res),
751 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
752 "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd,
753 [(set ptr_rc:$ea_res,
754 (pre_truncsti16 G8RC:$rS,
755 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
756 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
757 PPC970_DGroup_Cracked;
759 def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res),
760 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
761 "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd,
762 [(set ptr_rc:$ea_res,
763 (pre_truncsti32 G8RC:$rS,
764 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
765 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
766 PPC970_DGroup_Cracked;
768 def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res),
769 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
770 "stdux $rS, $ptroff, $ptrreg", LdStSTDU,
771 [(set ptr_rc:$ea_res,
772 (pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
773 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
774 PPC970_DGroup_Cracked, isPPC64;
776 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
777 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
778 "std $rT, $dst", LdStSTD,
779 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
780 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
781 "stdx $rT, $dst", LdStSTD,
782 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
783 PPC970_DGroup_Cracked;
788 //===----------------------------------------------------------------------===//
789 // Floating point instructions.
793 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
794 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
795 "fcfid $frD, $frB", FPGeneral,
796 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
797 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
798 "fctidz $frD, $frB", FPGeneral,
799 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
803 //===----------------------------------------------------------------------===//
804 // Instruction Patterns
807 // Extensions and truncates to/from 32-bit regs.
808 def : Pat<(i64 (zext GPRC:$in)),
809 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32),
811 def : Pat<(i64 (anyext GPRC:$in)),
812 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>;
813 def : Pat<(i32 (trunc G8RC:$in)),
814 (EXTRACT_SUBREG G8RC:$in, sub_32)>;
816 // Extending loads with i64 targets.
817 def : Pat<(zextloadi1 iaddr:$src),
819 def : Pat<(zextloadi1 xaddr:$src),
821 def : Pat<(extloadi1 iaddr:$src),
823 def : Pat<(extloadi1 xaddr:$src),
825 def : Pat<(extloadi8 iaddr:$src),
827 def : Pat<(extloadi8 xaddr:$src),
829 def : Pat<(extloadi16 iaddr:$src),
831 def : Pat<(extloadi16 xaddr:$src),
833 def : Pat<(extloadi32 iaddr:$src),
835 def : Pat<(extloadi32 xaddr:$src),
838 // Standard shifts. These are represented separately from the real shifts above
839 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
841 def : Pat<(sra G8RC:$rS, GPRC:$rB),
842 (SRAD G8RC:$rS, GPRC:$rB)>;
843 def : Pat<(srl G8RC:$rS, GPRC:$rB),
844 (SRD G8RC:$rS, GPRC:$rB)>;
845 def : Pat<(shl G8RC:$rS, GPRC:$rB),
846 (SLD G8RC:$rS, GPRC:$rB)>;
849 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
850 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
851 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
852 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
855 def : Pat<(rotl G8RC:$in, GPRC:$sh),
856 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
857 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
858 (RLDICL G8RC:$in, imm:$imm, 0)>;
860 // Hi and Lo for Darwin Global Addresses.
861 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
862 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
863 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
864 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
865 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
866 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
867 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
868 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
869 def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in),
870 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>;
871 def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in),
872 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>;
873 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
874 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
875 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
876 (ADDIS8 G8RC:$in, tconstpool:$g)>;
877 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
878 (ADDIS8 G8RC:$in, tjumptable:$g)>;
879 def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
880 (ADDIS8 G8RC:$in, tblockaddress:$g)>;