1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue());
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
67 def HI32_48 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
72 def HI48_64 : SDNodeXForm<imm, [{
73 // Transformation function: shift the immediate value down into the low bits.
74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
78 //===----------------------------------------------------------------------===//
82 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
83 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
84 let isReturn = 1, Uses = [LR8, RM] in
85 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
86 [(retflag)]>, Requires<[In64BitMode]>;
87 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
88 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
90 Requires<[In64BitMode]>;
91 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
92 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
94 Requires<[In64BitMode]>;
96 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
97 "bcctr 12, $bi, 0", IIC_BrB, []>,
98 Requires<[In64BitMode]>;
99 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
100 "bcctr 4, $bi, 0", IIC_BrB, []>,
101 Requires<[In64BitMode]>;
106 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
109 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
110 let Defs = [CTR8], Uses = [CTR8] in {
111 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
113 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
117 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
118 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
119 "bdzlr", IIC_BrB, []>;
120 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
121 "bdnzlr", IIC_BrB, []>;
127 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
128 // Convenient aliases for call instructions
130 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
131 "bl $func", IIC_BrB, []>; // See Pat patterns below.
133 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
134 "bl $func", IIC_BrB, []>;
136 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
137 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
139 let Uses = [RM], isCodeGenOnly = 1 in {
140 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
141 (outs), (ins calltarget:$func),
142 "bl $func\n\tnop", IIC_BrB, []>;
144 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
145 (outs), (ins tlscall:$func),
146 "bl $func\n\tnop", IIC_BrB, []>;
148 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
149 (outs), (ins abscalltarget:$func),
150 "bla $func\n\tnop", IIC_BrB,
151 [(PPCcall_nop (i64 imm:$func))]>;
153 let Uses = [CTR8, RM] in {
154 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
155 "bctrl", IIC_BrB, [(PPCbctrl)]>,
156 Requires<[In64BitMode]>;
158 let isCodeGenOnly = 1 in {
159 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
160 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
162 Requires<[In64BitMode]>;
164 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
165 "bcctrl 12, $bi, 0", IIC_BrB, []>,
166 Requires<[In64BitMode]>;
167 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
168 "bcctrl 4, $bi, 0", IIC_BrB, []>,
169 Requires<[In64BitMode]>;
174 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
175 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {
176 def BCTRL8_LDinto_toc :
177 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
179 "bctrl\n\tld 2, $src", IIC_BrB,
180 [(PPCbctrl_load_toc ixaddr:$src)]>,
181 Requires<[In64BitMode]>;
184 } // Interpretation64Bit
186 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
187 // previous definition must be marked as CodeGen only to prevent decoding
189 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
190 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
191 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
192 "bl $func", IIC_BrB, []>;
195 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
196 (BL8 tglobaladdr:$dst)>;
197 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
198 (BL8_NOP tglobaladdr:$dst)>;
200 def : Pat<(PPCcall (i64 texternalsym:$dst)),
201 (BL8 texternalsym:$dst)>;
202 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
203 (BL8_NOP texternalsym:$dst)>;
206 let usesCustomInserter = 1 in {
207 let Defs = [CR0] in {
208 def ATOMIC_LOAD_ADD_I64 : Pseudo<
209 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
210 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
211 def ATOMIC_LOAD_SUB_I64 : Pseudo<
212 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
213 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
214 def ATOMIC_LOAD_OR_I64 : Pseudo<
215 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
216 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
217 def ATOMIC_LOAD_XOR_I64 : Pseudo<
218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
219 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
220 def ATOMIC_LOAD_AND_I64 : Pseudo<
221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
222 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
223 def ATOMIC_LOAD_NAND_I64 : Pseudo<
224 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
225 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
227 def ATOMIC_CMP_SWAP_I64 : Pseudo<
228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
229 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
231 def ATOMIC_SWAP_I64 : Pseudo<
232 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
233 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
237 // Instructions to support atomic operations
238 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
239 "ldarx $rD, $ptr", IIC_LdStLDARX,
240 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
243 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
244 "stdcx. $rS, $dst", IIC_LdStSTDCX,
245 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
248 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
249 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
250 def TCRETURNdi8 :Pseudo< (outs),
251 (ins calltarget:$dst, i32imm:$offset),
252 "#TC_RETURNd8 $dst $offset",
255 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
256 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
257 "#TC_RETURNa8 $func $offset",
258 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
260 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
261 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
262 "#TC_RETURNr8 $dst $offset",
265 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
266 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
267 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
269 Requires<[In64BitMode]>;
271 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
272 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
273 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
277 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
278 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
279 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
282 } // Interpretation64Bit
284 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
285 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
287 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
288 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
290 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
291 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
294 // 64-bit CR instructions
295 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
296 let hasSideEffects = 0 in {
297 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
298 "mtocrf $FXM, $ST", IIC_BrMCRX>,
299 PPC970_DGroup_First, PPC970_Unit_CRU;
301 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
302 "mtcrf $FXM, $rS", IIC_BrMCRX>,
303 PPC970_MicroCode, PPC970_Unit_CRU;
305 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
306 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
307 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
308 PPC970_DGroup_First, PPC970_Unit_CRU;
310 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
311 "mfcr $rT", IIC_SprMFCR>,
312 PPC970_MicroCode, PPC970_Unit_CRU;
313 } // hasSideEffects = 0
315 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
317 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
319 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
320 Requires<[In64BitMode]>;
321 let isTerminator = 1 in
322 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
323 "#EH_SJLJ_LONGJMP64",
324 [(PPCeh_sjlj_longjmp addr:$buf)]>,
325 Requires<[In64BitMode]>;
328 //===----------------------------------------------------------------------===//
329 // 64-bit SPR manipulation instrs.
331 let Uses = [CTR8] in {
332 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
333 "mfctr $rT", IIC_SprMFSPR>,
334 PPC970_DGroup_First, PPC970_Unit_FXU;
336 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
337 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
338 "mtctr $rS", IIC_SprMTSPR>,
339 PPC970_DGroup_First, PPC970_Unit_FXU;
341 let hasSideEffects = 1, Defs = [CTR8] in {
342 let Pattern = [(int_ppc_mtctr i64:$rS)] in
343 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
344 "mtctr $rS", IIC_SprMTSPR>,
345 PPC970_DGroup_First, PPC970_Unit_FXU;
348 let Pattern = [(set i64:$rT, readcyclecounter)] in
349 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
350 "mfspr $rT, 268", IIC_SprMFTB>,
351 PPC970_DGroup_First, PPC970_Unit_FXU;
352 // Note that encoding mftb using mfspr is now the preferred form,
353 // and has been since at least ISA v2.03. The mftb instruction has
354 // now been phased out. Using mfspr, however, is known not to work on
357 let Defs = [X1], Uses = [X1] in
358 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
360 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
362 let Defs = [LR8] in {
363 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
364 "mtlr $rS", IIC_SprMTSPR>,
365 PPC970_DGroup_First, PPC970_Unit_FXU;
367 let Uses = [LR8] in {
368 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
369 "mflr $rT", IIC_SprMFSPR>,
370 PPC970_DGroup_First, PPC970_Unit_FXU;
372 } // Interpretation64Bit
374 //===----------------------------------------------------------------------===//
375 // Fixed point instructions.
378 let PPC970_Unit = 1 in { // FXU Operations.
379 let Interpretation64Bit = 1 in {
380 let hasSideEffects = 0 in {
381 let isCodeGenOnly = 1 in {
383 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
384 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
385 "li $rD, $imm", IIC_IntSimple,
386 [(set i64:$rD, imm64SExt16:$imm)]>;
387 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
388 "lis $rD, $imm", IIC_IntSimple,
389 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
393 let isCommutable = 1 in {
394 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
395 "nand", "$rA, $rS, $rB", IIC_IntSimple,
396 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
397 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
398 "and", "$rA, $rS, $rB", IIC_IntSimple,
399 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
401 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
402 "andc", "$rA, $rS, $rB", IIC_IntSimple,
403 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
404 let isCommutable = 1 in {
405 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
406 "or", "$rA, $rS, $rB", IIC_IntSimple,
407 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
408 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
409 "nor", "$rA, $rS, $rB", IIC_IntSimple,
410 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
412 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
413 "orc", "$rA, $rS, $rB", IIC_IntSimple,
414 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
415 let isCommutable = 1 in {
416 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
417 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
418 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
419 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
420 "xor", "$rA, $rS, $rB", IIC_IntSimple,
421 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
422 } // let isCommutable = 1
424 // Logical ops with immediate.
425 let Defs = [CR0] in {
426 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
427 "andi. $dst, $src1, $src2", IIC_IntGeneral,
428 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
430 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
431 "andis. $dst, $src1, $src2", IIC_IntGeneral,
432 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
435 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
436 "ori $dst, $src1, $src2", IIC_IntSimple,
437 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
438 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
439 "oris $dst, $src1, $src2", IIC_IntSimple,
440 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
441 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
442 "xori $dst, $src1, $src2", IIC_IntSimple,
443 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
444 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
445 "xoris $dst, $src1, $src2", IIC_IntSimple,
446 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
448 let isCommutable = 1 in
449 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
450 "add", "$rT, $rA, $rB", IIC_IntSimple,
451 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
452 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
453 // initial-exec thread-local storage model.
454 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
455 "add $rT, $rA, $rB", IIC_IntSimple,
456 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
458 let isCommutable = 1 in
459 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
460 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
461 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
462 PPC970_DGroup_Cracked;
464 let Defs = [CARRY] in
465 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
466 "addic $rD, $rA, $imm", IIC_IntGeneral,
467 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
468 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
469 "addi $rD, $rA, $imm", IIC_IntSimple,
470 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
471 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
472 "addis $rD, $rA, $imm", IIC_IntSimple,
473 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
475 let Defs = [CARRY] in {
476 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
477 "subfic $rD, $rA, $imm", IIC_IntGeneral,
478 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
479 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
480 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
481 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
482 PPC970_DGroup_Cracked;
484 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
485 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
486 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
487 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
488 "neg", "$rT, $rA", IIC_IntSimple,
489 [(set i64:$rT, (ineg i64:$rA))]>;
490 let Uses = [CARRY] in {
491 let isCommutable = 1 in
492 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
493 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
494 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
495 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
496 "addme", "$rT, $rA", IIC_IntGeneral,
497 [(set i64:$rT, (adde i64:$rA, -1))]>;
498 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
499 "addze", "$rT, $rA", IIC_IntGeneral,
500 [(set i64:$rT, (adde i64:$rA, 0))]>;
501 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
502 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
503 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
504 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
505 "subfme", "$rT, $rA", IIC_IntGeneral,
506 [(set i64:$rT, (sube -1, i64:$rA))]>;
507 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
508 "subfze", "$rT, $rA", IIC_IntGeneral,
509 [(set i64:$rT, (sube 0, i64:$rA))]>;
513 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
514 // previous definition must be marked as CodeGen only to prevent decoding
516 let isAsmParserOnly = 1 in
517 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
518 "add $rT, $rA, $rB", IIC_IntSimple, []>;
520 let isCommutable = 1 in {
521 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
522 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
523 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
524 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
525 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
526 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
529 } // Interpretation64Bit
531 let isCompare = 1, hasSideEffects = 0 in {
532 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
533 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
534 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
535 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
536 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
537 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
538 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
539 "cmpldi $dst, $src1, $src2",
540 IIC_IntCompare>, isPPC64;
543 let hasSideEffects = 0 in {
544 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
545 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
546 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
547 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
548 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
549 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
550 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
551 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
552 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
554 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
555 defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS),
556 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>;
558 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
559 "extsb", "$rA, $rS", IIC_IntSimple,
560 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
561 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
562 "extsh", "$rA, $rS", IIC_IntSimple,
563 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
565 defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
566 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
567 defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
568 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
569 } // Interpretation64Bit
572 let isCodeGenOnly = 1 in {
573 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
574 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
575 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
576 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
577 } // isCodeGenOnly for fast-isel
579 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
580 "extsw", "$rA, $rS", IIC_IntSimple,
581 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
582 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
583 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
584 "extsw", "$rA, $rS", IIC_IntSimple,
585 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
587 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
588 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
589 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
590 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
591 "cntlzd", "$rA, $rS", IIC_IntGeneral,
592 [(set i64:$rA, (ctlz i64:$rS))]>;
593 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
594 "popcntd $rA, $rS", IIC_IntGeneral,
595 [(set i64:$rA, (ctpop i64:$rS))]>;
597 let isCodeGenOnly = 1, isCommutable = 1 in
598 def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
599 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
600 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>;
602 // popcntw also does a population count on the high 32 bits (storing the
603 // results in the high 32-bits of the output). We'll ignore that here (which is
604 // safe because we never separately use the high part of the 64-bit registers).
605 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
606 "popcntw $rA, $rS", IIC_IntGeneral,
607 [(set i32:$rA, (ctpop i32:$rS))]>;
609 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
610 "divd", "$rT, $rA, $rB", IIC_IntDivD,
611 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
612 PPC970_DGroup_First, PPC970_DGroup_Cracked;
613 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
614 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
615 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
616 PPC970_DGroup_First, PPC970_DGroup_Cracked;
617 let isCommutable = 1 in
618 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
619 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
620 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
621 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
622 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
623 "mulli $rD, $rA, $imm", IIC_IntMulLI,
624 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
627 let hasSideEffects = 0 in {
628 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
629 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
630 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
631 []>, isPPC64, RegConstraint<"$rSi = $rA">,
634 // Rotate instructions.
635 defm RLDCL : MDSForm_1r<30, 8,
636 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
637 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
639 defm RLDCR : MDSForm_1r<30, 9,
640 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
641 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
643 defm RLDICL : MDForm_1r<30, 0,
644 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
645 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
648 let isCodeGenOnly = 1 in
649 def RLDICL_32_64 : MDForm_1<30, 0,
651 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
652 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
655 defm RLDICR : MDForm_1r<30, 1,
656 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
657 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
659 defm RLDIC : MDForm_1r<30, 2,
660 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
661 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
664 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
665 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
666 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
667 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
670 defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA),
671 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME),
672 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
675 // RLWIMI can be commuted if the rotate amount is zero.
676 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
677 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
678 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
679 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
680 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
681 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
684 def ISEL8 : AForm_4<31, 15,
685 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
686 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
688 } // Interpretation64Bit
689 } // hasSideEffects = 0
690 } // End FXU Operations.
693 //===----------------------------------------------------------------------===//
694 // Load/Store instructions.
698 // Sign extending loads.
699 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
700 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
701 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
702 "lha $rD, $src", IIC_LdStLHA,
703 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
704 PPC970_DGroup_Cracked;
705 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
706 "lwa $rD, $src", IIC_LdStLWA,
708 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
709 PPC970_DGroup_Cracked;
710 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
711 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
712 "lhax $rD, $src", IIC_LdStLHA,
713 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
714 PPC970_DGroup_Cracked;
715 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
716 "lwax $rD, $src", IIC_LdStLHA,
717 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
718 PPC970_DGroup_Cracked;
720 let isCodeGenOnly = 1, mayLoad = 1 in {
721 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
722 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
723 PPC970_DGroup_Cracked;
724 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
725 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
726 PPC970_DGroup_Cracked;
727 } // end fast-isel isCodeGenOnly
730 let mayLoad = 1, hasSideEffects = 0 in {
731 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
732 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
734 "lhau $rD, $addr", IIC_LdStLHAU,
735 []>, RegConstraint<"$addr.reg = $ea_result">,
736 NoEncode<"$ea_result">;
739 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
740 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
742 "lhaux $rD, $addr", IIC_LdStLHAUX,
743 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
744 NoEncode<"$ea_result">;
745 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
747 "lwaux $rD, $addr", IIC_LdStLHAUX,
748 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
749 NoEncode<"$ea_result">, isPPC64;
753 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
754 // Zero extending loads.
755 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
756 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
757 "lbz $rD, $src", IIC_LdStLoad,
758 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
759 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
760 "lhz $rD, $src", IIC_LdStLoad,
761 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
762 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
763 "lwz $rD, $src", IIC_LdStLoad,
764 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
766 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
767 "lbzx $rD, $src", IIC_LdStLoad,
768 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
769 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
770 "lhzx $rD, $src", IIC_LdStLoad,
771 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
772 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
773 "lwzx $rD, $src", IIC_LdStLoad,
774 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
778 let mayLoad = 1, hasSideEffects = 0 in {
779 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
780 "lbzu $rD, $addr", IIC_LdStLoadUpd,
781 []>, RegConstraint<"$addr.reg = $ea_result">,
782 NoEncode<"$ea_result">;
783 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
784 "lhzu $rD, $addr", IIC_LdStLoadUpd,
785 []>, RegConstraint<"$addr.reg = $ea_result">,
786 NoEncode<"$ea_result">;
787 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
788 "lwzu $rD, $addr", IIC_LdStLoadUpd,
789 []>, RegConstraint<"$addr.reg = $ea_result">,
790 NoEncode<"$ea_result">;
792 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
794 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
795 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
796 NoEncode<"$ea_result">;
797 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
799 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
800 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
801 NoEncode<"$ea_result">;
802 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
804 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
805 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
806 NoEncode<"$ea_result">;
809 } // Interpretation64Bit
812 // Full 8-byte loads.
813 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
814 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
815 "ld $rD, $src", IIC_LdStLD,
816 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
817 // The following four definitions are selected for small code model only.
818 // Otherwise, we need to create two instructions to form a 32-bit offset,
819 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
820 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
823 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
824 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
827 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
828 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
831 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
832 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
835 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
837 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
838 "ldx $rD, $src", IIC_LdStLD,
839 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
840 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
841 "ldbrx $rD, $src", IIC_LdStLoad,
842 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
844 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
845 def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src),
846 "lhbrx $rD, $src", IIC_LdStLoad, []>;
847 def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src),
848 "lwbrx $rD, $src", IIC_LdStLoad, []>;
851 let mayLoad = 1, hasSideEffects = 0 in {
852 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
853 "ldu $rD, $addr", IIC_LdStLDU,
854 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
855 NoEncode<"$ea_result">;
857 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
859 "ldux $rD, $addr", IIC_LdStLDUX,
860 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
861 NoEncode<"$ea_result">, isPPC64;
865 // Support for medium and large code model.
866 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
869 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
871 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
874 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
875 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
878 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
880 // Support for thread-local storage.
881 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
884 (PPCaddisGotTprelHA i64:$reg,
885 tglobaltlsaddr:$disp))]>,
887 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
890 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
892 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
893 (ADD8TLS $in, tglobaltlsaddr:$g)>;
894 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
897 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
899 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
902 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
904 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is
905 // explicitly defined when this op is created, so not mentioned here.
906 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
907 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
908 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
911 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
913 // Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8
914 // are true defines while the rest of the Defs are clobbers.
915 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
916 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
918 def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD),
919 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
922 (PPCaddiTlsgdLAddr i64:$reg,
923 tglobaltlsaddr:$disp,
924 tglobaltlsaddr:$sym))]>,
926 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
929 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
931 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
934 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
936 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is
937 // explicitly defined when this op is created, so not mentioned here.
938 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
939 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
940 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
943 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
945 // Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8
946 // are true defines, while the rest of the Defs are clobbers.
947 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
948 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
950 def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD),
951 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
954 (PPCaddiTlsldLAddr i64:$reg,
955 tglobaltlsaddr:$disp,
956 tglobaltlsaddr:$sym))]>,
958 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
961 (PPCaddisDtprelHA i64:$reg,
962 tglobaltlsaddr:$disp))]>,
964 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
967 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
970 let PPC970_Unit = 2 in {
971 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
972 // Truncating stores.
973 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
974 "stb $rS, $src", IIC_LdStStore,
975 [(truncstorei8 i64:$rS, iaddr:$src)]>;
976 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
977 "sth $rS, $src", IIC_LdStStore,
978 [(truncstorei16 i64:$rS, iaddr:$src)]>;
979 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
980 "stw $rS, $src", IIC_LdStStore,
981 [(truncstorei32 i64:$rS, iaddr:$src)]>;
982 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
983 "stbx $rS, $dst", IIC_LdStStore,
984 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
985 PPC970_DGroup_Cracked;
986 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
987 "sthx $rS, $dst", IIC_LdStStore,
988 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
989 PPC970_DGroup_Cracked;
990 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
991 "stwx $rS, $dst", IIC_LdStStore,
992 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
993 PPC970_DGroup_Cracked;
994 } // Interpretation64Bit
996 // Normal 8-byte stores.
997 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
998 "std $rS, $dst", IIC_LdStSTD,
999 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
1000 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
1001 "stdx $rS, $dst", IIC_LdStSTD,
1002 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
1003 PPC970_DGroup_Cracked;
1004 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
1005 "stdbrx $rS, $dst", IIC_LdStStore,
1006 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
1007 PPC970_DGroup_Cracked;
1010 // Stores with Update (pre-inc).
1011 let PPC970_Unit = 2, mayStore = 1 in {
1012 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1013 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1014 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1015 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1016 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1017 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1018 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1019 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1020 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1021 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1023 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1024 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1025 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1026 PPC970_DGroup_Cracked;
1027 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1028 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1029 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1030 PPC970_DGroup_Cracked;
1031 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1032 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1033 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1034 PPC970_DGroup_Cracked;
1035 } // Interpretation64Bit
1037 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
1038 "stdu $rS, $dst", IIC_LdStSTDU, []>,
1039 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
1042 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1043 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
1044 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1045 PPC970_DGroup_Cracked, isPPC64;
1048 // Patterns to match the pre-inc stores. We can't put the patterns on
1049 // the instruction definitions directly as ISel wants the address base
1050 // and offset to be separate operands, not a single complex operand.
1051 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1052 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1053 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1054 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1055 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1056 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1057 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1058 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
1060 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1061 (STBUX8 $rS, $ptrreg, $ptroff)>;
1062 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1063 (STHUX8 $rS, $ptrreg, $ptroff)>;
1064 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1065 (STWUX8 $rS, $ptrreg, $ptroff)>;
1066 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1067 (STDUX $rS, $ptrreg, $ptroff)>;
1070 //===----------------------------------------------------------------------===//
1071 // Floating point instructions.
1075 let PPC970_Unit = 3, hasSideEffects = 0,
1076 Uses = [RM] in { // FPU Operations.
1077 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
1078 "fcfid", "$frD, $frB", IIC_FPGeneral,
1079 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
1080 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
1081 "fctid", "$frD, $frB", IIC_FPGeneral,
1083 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
1084 "fctidz", "$frD, $frB", IIC_FPGeneral,
1085 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1087 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
1088 "fcfidu", "$frD, $frB", IIC_FPGeneral,
1089 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
1090 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1091 "fcfids", "$frD, $frB", IIC_FPGeneral,
1092 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1093 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1094 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1095 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1096 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1097 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1098 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1099 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1100 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1101 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1105 //===----------------------------------------------------------------------===//
1106 // Instruction Patterns
1109 // Extensions and truncates to/from 32-bit regs.
1110 def : Pat<(i64 (zext i32:$in)),
1111 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1113 def : Pat<(i64 (anyext i32:$in)),
1114 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1115 def : Pat<(i32 (trunc i64:$in)),
1116 (EXTRACT_SUBREG $in, sub_32)>;
1118 // Implement the 'not' operation with the NOR instruction.
1119 // (we could use the default xori pattern, but nor has lower latency on some
1120 // cores (such as the A2)).
1121 def i64not : OutPatFrag<(ops node:$in),
1123 def : Pat<(not i64:$in),
1126 // Extending loads with i64 targets.
1127 def : Pat<(zextloadi1 iaddr:$src),
1129 def : Pat<(zextloadi1 xaddr:$src),
1130 (LBZX8 xaddr:$src)>;
1131 def : Pat<(extloadi1 iaddr:$src),
1133 def : Pat<(extloadi1 xaddr:$src),
1134 (LBZX8 xaddr:$src)>;
1135 def : Pat<(extloadi8 iaddr:$src),
1137 def : Pat<(extloadi8 xaddr:$src),
1138 (LBZX8 xaddr:$src)>;
1139 def : Pat<(extloadi16 iaddr:$src),
1141 def : Pat<(extloadi16 xaddr:$src),
1142 (LHZX8 xaddr:$src)>;
1143 def : Pat<(extloadi32 iaddr:$src),
1145 def : Pat<(extloadi32 xaddr:$src),
1146 (LWZX8 xaddr:$src)>;
1148 // Standard shifts. These are represented separately from the real shifts above
1149 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1151 def : Pat<(sra i64:$rS, i32:$rB),
1153 def : Pat<(srl i64:$rS, i32:$rB),
1155 def : Pat<(shl i64:$rS, i32:$rB),
1159 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1160 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1161 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1162 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1165 def : Pat<(rotl i64:$in, i32:$sh),
1166 (RLDCL $in, $sh, 0)>;
1167 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1168 (RLDICL $in, imm:$imm, 0)>;
1170 // Hi and Lo for Darwin Global Addresses.
1171 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1172 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1173 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1174 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1175 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1176 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1177 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1178 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1179 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1180 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1181 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1182 (ADDI8 $in, tglobaltlsaddr:$g)>;
1183 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1184 (ADDIS8 $in, tglobaladdr:$g)>;
1185 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1186 (ADDIS8 $in, tconstpool:$g)>;
1187 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1188 (ADDIS8 $in, tjumptable:$g)>;
1189 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1190 (ADDIS8 $in, tblockaddress:$g)>;
1192 // Patterns to match r+r indexed loads and stores for
1193 // addresses without at least 4-byte alignment.
1194 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1195 (LWAX xoaddr:$src)>;
1196 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1198 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1199 (STDX $rS, xoaddr:$dst)>;
1201 // 64-bits atomic loads and stores
1202 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>;
1203 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>;
1205 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>;
1206 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>;