1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
23 def u16imm64 : Operand<i64> {
24 let PrintMethod = "printU16ImmOperand";
25 let EncoderMethod = "getImm16Encoding";
26 let ParserMatchClass = PPCU16ImmAsmOperand;
28 def s17imm64 : Operand<i64> {
29 // This operand type is used for addis/lis to allow the assembler parser
30 // to accept immediates in the range -65536..65535 for compatibility with
31 // the GNU assembler. The operand is treated as 16-bit otherwise.
32 let PrintMethod = "printS16ImmOperand";
33 let EncoderMethod = "getImm16Encoding";
34 let ParserMatchClass = PPCS17ImmAsmOperand;
36 def tocentry : Operand<iPTR> {
37 let MIOperandInfo = (ops i64imm:$imm);
39 def PPCTLSRegOperand : AsmOperandClass {
40 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
41 let RenderMethod = "addTLSRegOperands";
43 def tlsreg : Operand<i64> {
44 let EncoderMethod = "getTLSRegEncoding";
45 let ParserMatchClass = PPCTLSRegOperand;
47 def tlsgd : Operand<i64> {}
48 def tlscall : Operand<i64> {
49 let PrintMethod = "printTLSCall";
50 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
51 let EncoderMethod = "getTLSCallEncoding";
54 //===----------------------------------------------------------------------===//
55 // 64-bit transformation functions.
58 def SHL64 : SDNodeXForm<imm, [{
59 // Transformation function: 63 - imm
60 return getI32Imm(63 - N->getZExtValue());
63 def SRL64 : SDNodeXForm<imm, [{
64 // Transformation function: 64 - imm
65 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
68 def HI32_48 : SDNodeXForm<imm, [{
69 // Transformation function: shift the immediate value down into the low bits.
70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
73 def HI48_64 : SDNodeXForm<imm, [{
74 // Transformation function: shift the immediate value down into the low bits.
75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
79 //===----------------------------------------------------------------------===//
83 let Interpretation64Bit = 1 in {
84 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
85 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
86 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
87 Requires<[In64BitMode]>;
89 let isCodeGenOnly = 1 in
90 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
91 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>,
92 Requires<[In64BitMode]>;
97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
100 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
101 let Defs = [CTR8], Uses = [CTR8] in {
102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
118 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
119 // Convenient aliases for call instructions
121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
122 "bl $func", BrB, []>; // See Pat patterns below.
124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
125 "bl $func", BrB, []>;
127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
128 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
130 let Uses = [RM], isCodeGenOnly = 1 in {
131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
132 (outs), (ins calltarget:$func),
133 "bl $func\n\tnop", BrB, []>;
135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
136 (outs), (ins tlscall:$func),
137 "bl $func\n\tnop", BrB, []>;
139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
140 (outs), (ins abscalltarget:$func),
141 "bla $func\n\tnop", BrB,
142 [(PPCcall_nop (i64 imm:$func))]>;
144 let Uses = [CTR8, RM] in {
145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
146 "bctrl", BrB, [(PPCbctrl)]>,
147 Requires<[In64BitMode]>;
149 let isCodeGenOnly = 1 in
150 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>,
152 Requires<[In64BitMode]>;
155 } // Interpretation64Bit
158 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
159 (BL8 tglobaladdr:$dst)>;
160 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
161 (BL8_NOP tglobaladdr:$dst)>;
163 def : Pat<(PPCcall (i64 texternalsym:$dst)),
164 (BL8 texternalsym:$dst)>;
165 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
166 (BL8_NOP texternalsym:$dst)>;
169 let usesCustomInserter = 1 in {
170 let Defs = [CR0] in {
171 def ATOMIC_LOAD_ADD_I64 : Pseudo<
172 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
173 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
174 def ATOMIC_LOAD_SUB_I64 : Pseudo<
175 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
176 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
177 def ATOMIC_LOAD_OR_I64 : Pseudo<
178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
179 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
180 def ATOMIC_LOAD_XOR_I64 : Pseudo<
181 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
182 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
183 def ATOMIC_LOAD_AND_I64 : Pseudo<
184 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
185 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
186 def ATOMIC_LOAD_NAND_I64 : Pseudo<
187 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
188 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
190 def ATOMIC_CMP_SWAP_I64 : Pseudo<
191 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
192 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
194 def ATOMIC_SWAP_I64 : Pseudo<
195 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
196 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
200 // Instructions to support atomic operations
201 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
202 "ldarx $rD, $ptr", LdStLDARX,
203 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
206 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
207 "stdcx. $rS, $dst", LdStSTDCX,
208 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
211 let Interpretation64Bit = 1 in {
212 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
213 def TCRETURNdi8 :Pseudo< (outs),
214 (ins calltarget:$dst, i32imm:$offset),
215 "#TC_RETURNd8 $dst $offset",
218 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
219 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
220 "#TC_RETURNa8 $func $offset",
221 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
223 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
224 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
225 "#TC_RETURNr8 $dst $offset",
228 let isCodeGenOnly = 1 in {
230 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
231 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
232 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
233 Requires<[In64BitMode]>;
236 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
237 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
238 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
243 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
244 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
245 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
250 } // Interpretation64Bit
252 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
253 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
255 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
256 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
258 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
259 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
262 // 64-bit CR instructions
263 let Interpretation64Bit = 1 in {
264 let neverHasSideEffects = 1 in {
265 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
266 "mtocrf $FXM, $ST", BrMCRX>,
267 PPC970_DGroup_First, PPC970_Unit_CRU;
269 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
270 "mtcrf $FXM, $rS", BrMCRX>,
271 PPC970_MicroCode, PPC970_Unit_CRU;
273 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
274 "mfocrf $rT, $FXM", SprMFCR>,
275 PPC970_DGroup_First, PPC970_Unit_CRU;
277 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
278 "mfcr $rT", SprMFCR>,
279 PPC970_MicroCode, PPC970_Unit_CRU;
280 } // neverHasSideEffects = 1
282 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
284 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
286 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
287 Requires<[In64BitMode]>;
288 let isTerminator = 1 in
289 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
290 "#EH_SJLJ_LONGJMP64",
291 [(PPCeh_sjlj_longjmp addr:$buf)]>,
292 Requires<[In64BitMode]>;
295 //===----------------------------------------------------------------------===//
296 // 64-bit SPR manipulation instrs.
298 let Uses = [CTR8] in {
299 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
300 "mfctr $rT", SprMFSPR>,
301 PPC970_DGroup_First, PPC970_Unit_FXU;
303 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
304 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
305 "mtctr $rS", SprMTSPR>,
306 PPC970_DGroup_First, PPC970_Unit_FXU;
308 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in {
309 let Pattern = [(int_ppc_mtctr i64:$rS)] in
310 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
311 "mtctr $rS", SprMTSPR>,
312 PPC970_DGroup_First, PPC970_Unit_FXU;
315 let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in
316 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
317 "mfspr $rT, 268", SprMFTB>,
318 PPC970_DGroup_First, PPC970_Unit_FXU;
319 // Note that encoding mftb using mfspr is now the preferred form,
320 // and has been since at least ISA v2.03. The mftb instruction has
321 // now been phased out. Using mfspr, however, is known not to work on
324 let Defs = [X1], Uses = [X1] in
325 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
327 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
329 let Defs = [LR8] in {
330 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
331 "mtlr $rS", SprMTSPR>,
332 PPC970_DGroup_First, PPC970_Unit_FXU;
334 let Uses = [LR8] in {
335 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
336 "mflr $rT", SprMFSPR>,
337 PPC970_DGroup_First, PPC970_Unit_FXU;
339 } // Interpretation64Bit
341 //===----------------------------------------------------------------------===//
342 // Fixed point instructions.
345 let PPC970_Unit = 1 in { // FXU Operations.
346 let Interpretation64Bit = 1 in {
347 let neverHasSideEffects = 1 in {
349 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
350 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
351 "li $rD, $imm", IntSimple,
352 [(set i64:$rD, imm64SExt16:$imm)]>;
353 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
354 "lis $rD, $imm", IntSimple,
355 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
359 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
360 "nand", "$rA, $rS, $rB", IntSimple,
361 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
362 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
363 "and", "$rA, $rS, $rB", IntSimple,
364 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
365 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
366 "andc", "$rA, $rS, $rB", IntSimple,
367 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
368 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
369 "or", "$rA, $rS, $rB", IntSimple,
370 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
371 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
372 "nor", "$rA, $rS, $rB", IntSimple,
373 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
374 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
375 "orc", "$rA, $rS, $rB", IntSimple,
376 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
377 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
378 "eqv", "$rA, $rS, $rB", IntSimple,
379 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
380 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
381 "xor", "$rA, $rS, $rB", IntSimple,
382 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
384 // Logical ops with immediate.
385 let Defs = [CR0] in {
386 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
387 "andi. $dst, $src1, $src2", IntGeneral,
388 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
390 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
391 "andis. $dst, $src1, $src2", IntGeneral,
392 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
395 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
396 "ori $dst, $src1, $src2", IntSimple,
397 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
398 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
399 "oris $dst, $src1, $src2", IntSimple,
400 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
401 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
402 "xori $dst, $src1, $src2", IntSimple,
403 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
404 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
405 "xoris $dst, $src1, $src2", IntSimple,
406 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
408 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
409 "add", "$rT, $rA, $rB", IntSimple,
410 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
411 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
412 // initial-exec thread-local storage model.
413 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
414 "add $rT, $rA, $rB", IntSimple,
415 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
417 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
418 "addc", "$rT, $rA, $rB", IntGeneral,
419 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
420 PPC970_DGroup_Cracked;
421 let Defs = [CARRY] in
422 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
423 "addic $rD, $rA, $imm", IntGeneral,
424 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
425 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
426 "addi $rD, $rA, $imm", IntSimple,
427 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
428 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
429 "addis $rD, $rA, $imm", IntSimple,
430 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
432 let Defs = [CARRY] in {
433 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
434 "subfic $rD, $rA, $imm", IntGeneral,
435 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
436 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
437 "subfc", "$rT, $rA, $rB", IntGeneral,
438 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
439 PPC970_DGroup_Cracked;
441 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
442 "subf", "$rT, $rA, $rB", IntGeneral,
443 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
444 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
445 "neg", "$rT, $rA", IntSimple,
446 [(set i64:$rT, (ineg i64:$rA))]>;
447 let Uses = [CARRY] in {
448 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
449 "adde", "$rT, $rA, $rB", IntGeneral,
450 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
451 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
452 "addme", "$rT, $rA", IntGeneral,
453 [(set i64:$rT, (adde i64:$rA, -1))]>;
454 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
455 "addze", "$rT, $rA", IntGeneral,
456 [(set i64:$rT, (adde i64:$rA, 0))]>;
457 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
458 "subfe", "$rT, $rA, $rB", IntGeneral,
459 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
460 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
461 "subfme", "$rT, $rA", IntGeneral,
462 [(set i64:$rT, (sube -1, i64:$rA))]>;
463 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
464 "subfze", "$rT, $rA", IntGeneral,
465 [(set i64:$rT, (sube 0, i64:$rA))]>;
469 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
470 "mulhd", "$rT, $rA, $rB", IntMulHW,
471 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
472 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
473 "mulhdu", "$rT, $rA, $rB", IntMulHWU,
474 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
476 } // Interpretation64Bit
478 let isCompare = 1, neverHasSideEffects = 1 in {
479 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
480 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
481 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
482 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
483 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
484 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
485 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
486 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
489 let neverHasSideEffects = 1 in {
490 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
491 "sld", "$rA, $rS, $rB", IntRotateD,
492 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
493 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
494 "srd", "$rA, $rS, $rB", IntRotateD,
495 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
496 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
497 "srad", "$rA, $rS, $rB", IntRotateD,
498 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
500 let Interpretation64Bit = 1 in {
501 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
502 "extsb", "$rA, $rS", IntSimple,
503 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
504 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
505 "extsh", "$rA, $rS", IntSimple,
506 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
507 } // Interpretation64Bit
510 let isCodeGenOnly = 1 in {
511 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
512 "extsb $rA, $rS", IntSimple, []>, isPPC64;
513 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
514 "extsh $rA, $rS", IntSimple, []>, isPPC64;
515 } // isCodeGenOnly for fast-isel
517 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
518 "extsw", "$rA, $rS", IntSimple,
519 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
520 let Interpretation64Bit = 1 in
521 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
522 "extsw", "$rA, $rS", IntSimple,
523 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
525 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
526 "sradi", "$rA, $rS, $SH", IntRotateDI,
527 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
528 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
529 "cntlzd", "$rA, $rS", IntGeneral,
530 [(set i64:$rA, (ctlz i64:$rS))]>;
531 defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
532 "popcntd", "$rA, $rS", IntGeneral,
533 [(set i64:$rA, (ctpop i64:$rS))]>;
535 // popcntw also does a population count on the high 32 bits (storing the
536 // results in the high 32-bits of the output). We'll ignore that here (which is
537 // safe because we never separately use the high part of the 64-bit registers).
538 defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
539 "popcntw", "$rA, $rS", IntGeneral,
540 [(set i32:$rA, (ctpop i32:$rS))]>;
542 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
543 "divd", "$rT, $rA, $rB", IntDivD,
544 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
545 PPC970_DGroup_First, PPC970_DGroup_Cracked;
546 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
547 "divdu", "$rT, $rA, $rB", IntDivD,
548 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
549 PPC970_DGroup_First, PPC970_DGroup_Cracked;
550 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
551 "mulld", "$rT, $rA, $rB", IntMulHD,
552 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
553 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
554 "mulli $rD, $rA, $imm", IntMulLI,
555 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
558 let neverHasSideEffects = 1 in {
559 let isCommutable = 1 in {
560 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
561 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
562 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
563 []>, isPPC64, RegConstraint<"$rSi = $rA">,
567 // Rotate instructions.
568 defm RLDCL : MDSForm_1r<30, 8,
569 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
570 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
572 defm RLDCR : MDSForm_1r<30, 9,
573 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
574 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD,
576 defm RLDICL : MDForm_1r<30, 0,
577 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
578 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
581 let isCodeGenOnly = 1 in
582 def RLDICL_32_64 : MDForm_1<30, 0,
584 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
585 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
588 defm RLDICR : MDForm_1r<30, 1,
589 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
590 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
592 defm RLDIC : MDForm_1r<30, 2,
593 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
594 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI,
597 let Interpretation64Bit = 1 in {
598 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
599 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
600 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
604 def ISEL8 : AForm_4<31, 15,
605 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
606 "isel $rT, $rA, $rB, $cond", IntGeneral,
608 } // Interpretation64Bit
609 } // neverHasSideEffects = 1
610 } // End FXU Operations.
613 //===----------------------------------------------------------------------===//
614 // Load/Store instructions.
618 // Sign extending loads.
619 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
620 let Interpretation64Bit = 1 in
621 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
622 "lha $rD, $src", LdStLHA,
623 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
624 PPC970_DGroup_Cracked;
625 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
626 "lwa $rD, $src", LdStLWA,
628 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
629 PPC970_DGroup_Cracked;
630 let Interpretation64Bit = 1 in
631 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
632 "lhax $rD, $src", LdStLHA,
633 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
634 PPC970_DGroup_Cracked;
635 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
636 "lwax $rD, $src", LdStLHA,
637 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
638 PPC970_DGroup_Cracked;
640 let isCodeGenOnly = 1, mayLoad = 1 in {
641 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
642 "lwa $rD, $src", LdStLWA, []>, isPPC64,
643 PPC970_DGroup_Cracked;
644 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
645 "lwax $rD, $src", LdStLHA, []>, isPPC64,
646 PPC970_DGroup_Cracked;
647 } // end fast-isel isCodeGenOnly
650 let mayLoad = 1, neverHasSideEffects = 1 in {
651 let Interpretation64Bit = 1 in
652 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
654 "lhau $rD, $addr", LdStLHAU,
655 []>, RegConstraint<"$addr.reg = $ea_result">,
656 NoEncode<"$ea_result">;
659 let Interpretation64Bit = 1 in
660 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
662 "lhaux $rD, $addr", LdStLHAU,
663 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
664 NoEncode<"$ea_result">;
665 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
667 "lwaux $rD, $addr", LdStLHAU,
668 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
669 NoEncode<"$ea_result">, isPPC64;
673 let Interpretation64Bit = 1 in {
674 // Zero extending loads.
675 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
676 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
677 "lbz $rD, $src", LdStLoad,
678 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
679 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
680 "lhz $rD, $src", LdStLoad,
681 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
682 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
683 "lwz $rD, $src", LdStLoad,
684 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
686 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
687 "lbzx $rD, $src", LdStLoad,
688 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
689 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
690 "lhzx $rD, $src", LdStLoad,
691 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
692 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
693 "lwzx $rD, $src", LdStLoad,
694 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
698 let mayLoad = 1, neverHasSideEffects = 1 in {
699 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
700 "lbzu $rD, $addr", LdStLoadUpd,
701 []>, RegConstraint<"$addr.reg = $ea_result">,
702 NoEncode<"$ea_result">;
703 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
704 "lhzu $rD, $addr", LdStLoadUpd,
705 []>, RegConstraint<"$addr.reg = $ea_result">,
706 NoEncode<"$ea_result">;
707 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
708 "lwzu $rD, $addr", LdStLoadUpd,
709 []>, RegConstraint<"$addr.reg = $ea_result">,
710 NoEncode<"$ea_result">;
712 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
714 "lbzux $rD, $addr", LdStLoadUpd,
715 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
716 NoEncode<"$ea_result">;
717 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
719 "lhzux $rD, $addr", LdStLoadUpd,
720 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
721 NoEncode<"$ea_result">;
722 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
724 "lwzux $rD, $addr", LdStLoadUpd,
725 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
726 NoEncode<"$ea_result">;
729 } // Interpretation64Bit
732 // Full 8-byte loads.
733 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
734 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
735 "ld $rD, $src", LdStLD,
736 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
737 // The following three definitions are selected for small code model only.
738 // Otherwise, we need to create two instructions to form a 32-bit offset,
739 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
740 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
743 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
744 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
747 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
748 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
751 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
753 let hasSideEffects = 1, isCodeGenOnly = 1 in {
754 let RST = 2, DS = 2 in
755 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
756 "ld 2, 8($reg)", LdStLD,
757 [(PPCload_toc i64:$reg)]>, isPPC64;
759 let RST = 2, DS = 10, RA = 1 in
760 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
761 "ld 2, 40(1)", LdStLD,
762 [(PPCtoc_restore)]>, isPPC64;
764 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
765 "ldx $rD, $src", LdStLD,
766 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
767 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
768 "ldbrx $rD, $src", LdStLoad,
769 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
771 let mayLoad = 1, neverHasSideEffects = 1 in {
772 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
773 "ldu $rD, $addr", LdStLDU,
774 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
775 NoEncode<"$ea_result">;
777 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
779 "ldux $rD, $addr", LdStLDU,
780 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
781 NoEncode<"$ea_result">, isPPC64;
785 def : Pat<(PPCload ixaddr:$src),
787 def : Pat<(PPCload xaddr:$src),
790 // Support for medium and large code model.
791 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
794 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
796 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
799 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
800 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
803 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
805 // Support for thread-local storage.
806 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
809 (PPCaddisGotTprelHA i64:$reg,
810 tglobaltlsaddr:$disp))]>,
812 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
815 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
817 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
818 (ADD8TLS $in, tglobaltlsaddr:$g)>;
819 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
822 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
824 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
827 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
829 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
832 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
834 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
837 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
839 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
842 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
844 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
847 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
849 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
852 (PPCaddisDtprelHA i64:$reg,
853 tglobaltlsaddr:$disp))]>,
855 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
858 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
861 let PPC970_Unit = 2 in {
862 let Interpretation64Bit = 1 in {
863 // Truncating stores.
864 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
865 "stb $rS, $src", LdStStore,
866 [(truncstorei8 i64:$rS, iaddr:$src)]>;
867 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
868 "sth $rS, $src", LdStStore,
869 [(truncstorei16 i64:$rS, iaddr:$src)]>;
870 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
871 "stw $rS, $src", LdStStore,
872 [(truncstorei32 i64:$rS, iaddr:$src)]>;
873 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
874 "stbx $rS, $dst", LdStStore,
875 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
876 PPC970_DGroup_Cracked;
877 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
878 "sthx $rS, $dst", LdStStore,
879 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
880 PPC970_DGroup_Cracked;
881 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
882 "stwx $rS, $dst", LdStStore,
883 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
884 PPC970_DGroup_Cracked;
885 } // Interpretation64Bit
887 // Normal 8-byte stores.
888 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
889 "std $rS, $dst", LdStSTD,
890 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
891 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
892 "stdx $rS, $dst", LdStSTD,
893 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
894 PPC970_DGroup_Cracked;
895 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
896 "stdbrx $rS, $dst", LdStStore,
897 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
898 PPC970_DGroup_Cracked;
901 // Stores with Update (pre-inc).
902 let PPC970_Unit = 2, mayStore = 1 in {
903 let Interpretation64Bit = 1 in {
904 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
905 "stbu $rS, $dst", LdStStoreUpd, []>,
906 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
907 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
908 "sthu $rS, $dst", LdStStoreUpd, []>,
909 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
910 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
911 "stwu $rS, $dst", LdStStoreUpd, []>,
912 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
913 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
914 "stdu $rS, $dst", LdStSTDU, []>,
915 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
918 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
919 "stbux $rS, $dst", LdStStoreUpd, []>,
920 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
921 PPC970_DGroup_Cracked;
922 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
923 "sthux $rS, $dst", LdStStoreUpd, []>,
924 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
925 PPC970_DGroup_Cracked;
926 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
927 "stwux $rS, $dst", LdStStoreUpd, []>,
928 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
929 PPC970_DGroup_Cracked;
930 } // Interpretation64Bit
932 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
933 "stdux $rS, $dst", LdStSTDU, []>,
934 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
935 PPC970_DGroup_Cracked, isPPC64;
938 // Patterns to match the pre-inc stores. We can't put the patterns on
939 // the instruction definitions directly as ISel wants the address base
940 // and offset to be separate operands, not a single complex operand.
941 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
942 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
943 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
944 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
945 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
946 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
947 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
948 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
950 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
951 (STBUX8 $rS, $ptrreg, $ptroff)>;
952 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
953 (STHUX8 $rS, $ptrreg, $ptroff)>;
954 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
955 (STWUX8 $rS, $ptrreg, $ptroff)>;
956 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
957 (STDUX $rS, $ptrreg, $ptroff)>;
960 //===----------------------------------------------------------------------===//
961 // Floating point instructions.
965 let PPC970_Unit = 3, neverHasSideEffects = 1,
966 Uses = [RM] in { // FPU Operations.
967 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
968 "fcfid", "$frD, $frB", FPGeneral,
969 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
970 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
971 "fctidz", "$frD, $frB", FPGeneral,
972 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
974 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
975 "fcfidu", "$frD, $frB", FPGeneral,
976 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
977 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
978 "fcfids", "$frD, $frB", FPGeneral,
979 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
980 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
981 "fcfidus", "$frD, $frB", FPGeneral,
982 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
983 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
984 "fctiduz", "$frD, $frB", FPGeneral,
985 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
986 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
987 "fctiwuz", "$frD, $frB", FPGeneral,
988 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
992 //===----------------------------------------------------------------------===//
993 // Instruction Patterns
996 // Extensions and truncates to/from 32-bit regs.
997 def : Pat<(i64 (zext i32:$in)),
998 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1000 def : Pat<(i64 (anyext i32:$in)),
1001 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1002 def : Pat<(i32 (trunc i64:$in)),
1003 (EXTRACT_SUBREG $in, sub_32)>;
1005 // Extending loads with i64 targets.
1006 def : Pat<(zextloadi1 iaddr:$src),
1008 def : Pat<(zextloadi1 xaddr:$src),
1009 (LBZX8 xaddr:$src)>;
1010 def : Pat<(extloadi1 iaddr:$src),
1012 def : Pat<(extloadi1 xaddr:$src),
1013 (LBZX8 xaddr:$src)>;
1014 def : Pat<(extloadi8 iaddr:$src),
1016 def : Pat<(extloadi8 xaddr:$src),
1017 (LBZX8 xaddr:$src)>;
1018 def : Pat<(extloadi16 iaddr:$src),
1020 def : Pat<(extloadi16 xaddr:$src),
1021 (LHZX8 xaddr:$src)>;
1022 def : Pat<(extloadi32 iaddr:$src),
1024 def : Pat<(extloadi32 xaddr:$src),
1025 (LWZX8 xaddr:$src)>;
1027 // Standard shifts. These are represented separately from the real shifts above
1028 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1030 def : Pat<(sra i64:$rS, i32:$rB),
1032 def : Pat<(srl i64:$rS, i32:$rB),
1034 def : Pat<(shl i64:$rS, i32:$rB),
1038 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1039 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1040 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1041 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1044 def : Pat<(rotl i64:$in, i32:$sh),
1045 (RLDCL $in, $sh, 0)>;
1046 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1047 (RLDICL $in, imm:$imm, 0)>;
1049 // Hi and Lo for Darwin Global Addresses.
1050 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1051 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1052 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1053 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1054 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1055 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1056 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1057 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1058 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1059 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1060 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1061 (ADDI8 $in, tglobaltlsaddr:$g)>;
1062 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1063 (ADDIS8 $in, tglobaladdr:$g)>;
1064 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1065 (ADDIS8 $in, tconstpool:$g)>;
1066 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1067 (ADDIS8 $in, tjumptable:$g)>;
1068 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1069 (ADDIS8 $in, tblockaddress:$g)>;
1071 // Patterns to match r+r indexed loads and stores for
1072 // addresses without at least 4-byte alignment.
1073 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1074 (LWAX xoaddr:$src)>;
1075 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1077 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1078 (STDX $rS, xoaddr:$dst)>;