1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
32 def tocentry : Operand<iPTR> {
33 let MIOperandInfo = (ops i64imm:$imm);
35 def tlsreg : Operand<i64> {
36 let EncoderMethod = "getTLSRegEncoding";
38 def tlsgd : Operand<i64> {}
40 //===----------------------------------------------------------------------===//
41 // 64-bit transformation functions.
44 def SHL64 : SDNodeXForm<imm, [{
45 // Transformation function: 63 - imm
46 return getI32Imm(63 - N->getZExtValue());
49 def SRL64 : SDNodeXForm<imm, [{
50 // Transformation function: 64 - imm
51 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
54 def HI32_48 : SDNodeXForm<imm, [{
55 // Transformation function: shift the immediate value down into the low bits.
56 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
59 def HI48_64 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
65 //===----------------------------------------------------------------------===//
69 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
70 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in
71 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
72 Requires<[In64BitMode]>;
76 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
79 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
80 let Defs = [CTR8], Uses = [CTR8] in {
81 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
83 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
87 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
88 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
90 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
97 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
98 // Convenient aliases for call instructions
100 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
101 "bl $func", BrB, []>; // See Pat patterns below.
103 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func),
104 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
106 let Uses = [RM], isCodeGenOnly = 1 in {
107 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
108 (outs), (ins calltarget:$func),
109 "bl $func\n\tnop", BrB, []>;
111 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
112 (outs), (ins calltarget:$func, tlsgd:$sym),
113 "bl $func($sym)\n\tnop", BrB, []>;
115 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
116 (outs), (ins calltarget:$func, tlsgd:$sym),
117 "bl $func($sym)\n\tnop", BrB, []>;
119 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
120 (outs), (ins aaddr:$func),
121 "bla $func\n\tnop", BrB,
122 [(PPCcall_nop (i64 imm:$func))]>;
124 let Uses = [CTR8, RM] in {
125 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
126 "bctrl", BrB, [(PPCbctrl)]>,
127 Requires<[In64BitMode]>;
133 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
134 (BL8 tglobaladdr:$dst)>;
135 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
136 (BL8_NOP tglobaladdr:$dst)>;
138 def : Pat<(PPCcall (i64 texternalsym:$dst)),
139 (BL8 texternalsym:$dst)>;
140 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
141 (BL8_NOP texternalsym:$dst)>;
144 let usesCustomInserter = 1 in {
145 let Defs = [CR0] in {
146 def ATOMIC_LOAD_ADD_I64 : Pseudo<
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
148 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
149 def ATOMIC_LOAD_SUB_I64 : Pseudo<
150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
151 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
152 def ATOMIC_LOAD_OR_I64 : Pseudo<
153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
154 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
155 def ATOMIC_LOAD_XOR_I64 : Pseudo<
156 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
157 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
158 def ATOMIC_LOAD_AND_I64 : Pseudo<
159 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
160 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
161 def ATOMIC_LOAD_NAND_I64 : Pseudo<
162 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
163 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
165 def ATOMIC_CMP_SWAP_I64 : Pseudo<
166 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
167 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
169 def ATOMIC_SWAP_I64 : Pseudo<
170 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
171 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
175 // Instructions to support atomic operations
176 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
177 "ldarx $rD, $ptr", LdStLDARX,
178 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
181 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
182 "stdcx. $rS, $dst", LdStSTDCX,
183 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
186 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
187 def TCRETURNdi8 :Pseudo< (outs),
188 (ins calltarget:$dst, i32imm:$offset),
189 "#TC_RETURNd8 $dst $offset",
192 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
193 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
194 "#TC_RETURNa8 $func $offset",
195 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
197 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
198 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
199 "#TC_RETURNr8 $dst $offset",
202 let isCodeGenOnly = 1 in {
204 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
205 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
206 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
207 Requires<[In64BitMode]>;
210 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
211 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
212 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
217 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
218 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
219 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
225 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
226 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
228 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
229 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
231 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
232 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
235 // 64-bit CR instructions
236 let neverHasSideEffects = 1 in {
237 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
238 "mtcrf $FXM, $rS", BrMCRX>,
239 PPC970_MicroCode, PPC970_Unit_CRU;
241 let isCodeGenOnly = 1 in
242 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
243 "#MFCR8pseud", SprMFCR>,
244 PPC970_MicroCode, PPC970_Unit_CRU;
245 } // neverHasSideEffects = 1
247 // MFCR uses all CR registers, but marking that explicitly causes
248 // problems because some of them appear to be undefined. Because
249 // this form is used only in prologue code, just mark it as having
251 let /* Uses = [CR0, CR1, CR2, CR3, CR4, CR5, CR6] */ hasSideEffects = 1 in
252 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
253 "mfcr $rT", SprMFCR>,
254 PPC970_MicroCode, PPC970_Unit_CRU;
256 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
257 def EH_SjLj_SetJmp64 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
259 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
260 Requires<[In64BitMode]>;
261 let isTerminator = 1 in
262 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
263 "#EH_SJLJ_LONGJMP64",
264 [(PPCeh_sjlj_longjmp addr:$buf)]>,
265 Requires<[In64BitMode]>;
268 //===----------------------------------------------------------------------===//
269 // 64-bit SPR manipulation instrs.
271 let Uses = [CTR8] in {
272 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
273 "mfctr $rT", SprMFSPR>,
274 PPC970_DGroup_First, PPC970_Unit_FXU;
276 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
277 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
278 "mtctr $rS", SprMTSPR>,
279 PPC970_DGroup_First, PPC970_Unit_FXU;
282 let Pattern = [(set i64:$rT, readcyclecounter)] in
283 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
284 "mfspr $rT, 268", SprMFTB>,
285 PPC970_DGroup_First, PPC970_Unit_FXU;
286 // Note that encoding mftb using mfspr is now the preferred form,
287 // and has been since at least ISA v2.03. The mftb instruction has
288 // now been phased out. Using mfspr, however, is known not to work on
291 let Defs = [X1], Uses = [X1] in
292 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
294 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
296 let Defs = [LR8] in {
297 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
298 "mtlr $rS", SprMTSPR>,
299 PPC970_DGroup_First, PPC970_Unit_FXU;
301 let Uses = [LR8] in {
302 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
303 "mflr $rT", SprMFSPR>,
304 PPC970_DGroup_First, PPC970_Unit_FXU;
307 //===----------------------------------------------------------------------===//
308 // Fixed point instructions.
311 let PPC970_Unit = 1 in { // FXU Operations.
313 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
314 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
315 "li $rD, $imm", IntSimple,
316 [(set i64:$rD, immSExt16:$imm)]>;
317 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
318 "lis $rD, $imm", IntSimple,
319 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
323 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
324 "nand $rA, $rS, $rB", IntSimple,
325 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
326 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
327 "and $rA, $rS, $rB", IntSimple,
328 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
329 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
330 "andc $rA, $rS, $rB", IntSimple,
331 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
332 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
333 "or $rA, $rS, $rB", IntSimple,
334 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
335 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
336 "nor $rA, $rS, $rB", IntSimple,
337 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
338 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
339 "orc $rA, $rS, $rB", IntSimple,
340 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
341 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
342 "eqv $rA, $rS, $rB", IntSimple,
343 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
344 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
345 "xor $rA, $rS, $rB", IntSimple,
346 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
348 // Logical ops with immediate.
349 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
350 "andi. $dst, $src1, $src2", IntGeneral,
351 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
353 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
354 "andis. $dst, $src1, $src2", IntGeneral,
355 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
357 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
358 "ori $dst, $src1, $src2", IntSimple,
359 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
360 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
361 "oris $dst, $src1, $src2", IntSimple,
362 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
363 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
364 "xori $dst, $src1, $src2", IntSimple,
365 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
366 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
367 "xoris $dst, $src1, $src2", IntSimple,
368 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
370 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
371 "add $rT, $rA, $rB", IntSimple,
372 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
373 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
374 // initial-exec thread-local storage model.
375 let isCodeGenOnly = 1 in
376 def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB),
377 "add $rT, $rA, $rB@tls", IntSimple,
378 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
380 let Defs = [CARRY] in {
381 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
382 "addc $rT, $rA, $rB", IntGeneral,
383 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
384 PPC970_DGroup_Cracked;
385 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
386 "addic $rD, $rA, $imm", IntGeneral,
387 [(set i64:$rD, (addc i64:$rA, immSExt16:$imm))]>;
389 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm),
390 "addi $rD, $rA, $imm", IntSimple,
391 [(set i64:$rD, (add i64:$rA, immSExt16:$imm))]>;
392 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm),
393 "addis $rD, $rA, $imm", IntSimple,
394 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
396 let Defs = [CARRY] in {
397 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
398 "subfic $rD, $rA, $imm", IntGeneral,
399 [(set i64:$rD, (subc immSExt16:$imm, i64:$rA))]>;
400 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
401 "subfc $rT, $rA, $rB", IntGeneral,
402 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
403 PPC970_DGroup_Cracked;
405 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
406 "subf $rT, $rA, $rB", IntGeneral,
407 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
408 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
409 "neg $rT, $rA", IntSimple,
410 [(set i64:$rT, (ineg i64:$rA))]>;
411 let Uses = [CARRY], Defs = [CARRY] in {
412 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
413 "adde $rT, $rA, $rB", IntGeneral,
414 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
415 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
416 "addme $rT, $rA", IntGeneral,
417 [(set i64:$rT, (adde i64:$rA, -1))]>;
418 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
419 "addze $rT, $rA", IntGeneral,
420 [(set i64:$rT, (adde i64:$rA, 0))]>;
421 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
422 "subfe $rT, $rA, $rB", IntGeneral,
423 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
424 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
425 "subfme $rT, $rA", IntGeneral,
426 [(set i64:$rT, (sube -1, i64:$rA))]>;
427 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
428 "subfze $rT, $rA", IntGeneral,
429 [(set i64:$rT, (sube 0, i64:$rA))]>;
433 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
434 "mulhd $rT, $rA, $rB", IntMulHW,
435 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
436 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
437 "mulhdu $rT, $rA, $rB", IntMulHWU,
438 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
440 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
441 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
442 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
443 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
444 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
445 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
446 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
447 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
449 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
450 "sld $rA, $rS, $rB", IntRotateD,
451 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
452 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
453 "srd $rA, $rS, $rB", IntRotateD,
454 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
455 let Defs = [CARRY] in {
456 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
457 "srad $rA, $rS, $rB", IntRotateD,
458 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
461 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
462 "extsb $rA, $rS", IntSimple,
463 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
464 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
465 "extsh $rA, $rS", IntSimple,
466 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
468 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
469 "extsw $rA, $rS", IntSimple,
470 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
471 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
472 "extsw $rA, $rS", IntSimple,
473 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
475 let Defs = [CARRY] in {
476 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
477 "sradi $rA, $rS, $SH", IntRotateDI,
478 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
480 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
481 "cntlzd $rA, $rS", IntGeneral,
482 [(set i64:$rA, (ctlz i64:$rS))]>;
483 def POPCNTD : XForm_11<31, 506, (outs G8RC:$rA), (ins G8RC:$rS),
484 "popcntd $rA, $rS", IntGeneral,
485 [(set i64:$rA, (ctpop i64:$rS))]>;
487 // popcntw also does a population count on the high 32 bits (storing the
488 // results in the high 32-bits of the output). We'll ignore that here (which is
489 // safe because we never separately use the high part of the 64-bit registers).
490 def POPCNTW : XForm_11<31, 378, (outs GPRC:$rA), (ins GPRC:$rS),
491 "popcntw $rA, $rS", IntGeneral,
492 [(set i32:$rA, (ctpop i32:$rS))]>;
494 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
495 "divd $rT, $rA, $rB", IntDivD,
496 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
497 PPC970_DGroup_First, PPC970_DGroup_Cracked;
498 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
499 "divdu $rT, $rA, $rB", IntDivD,
500 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
501 PPC970_DGroup_First, PPC970_DGroup_Cracked;
502 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
503 "mulld $rT, $rA, $rB", IntMulHD,
504 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
507 let neverHasSideEffects = 1 in {
508 let isCommutable = 1 in {
509 def RLDIMI : MDForm_1<30, 3,
510 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
511 "rldimi $rA, $rS, $SH, $MB", IntRotateDI,
512 []>, isPPC64, RegConstraint<"$rSi = $rA">,
516 // Rotate instructions.
517 def RLDCL : MDForm_1<30, 0,
518 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
519 "rldcl $rA, $rS, $rB, $MBE", IntRotateD,
521 def RLDICL : MDForm_1<30, 0,
522 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
523 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
525 def RLDICR : MDForm_1<30, 1,
526 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
527 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI,
530 def RLWINM8 : MForm_2<21,
531 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
532 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
536 def ISEL8 : AForm_4<31, 15,
537 (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, CRBITRC:$cond),
538 "isel $rT, $rA, $rB, $cond", IntGeneral,
540 } // neverHasSideEffects = 1
541 } // End FXU Operations.
544 //===----------------------------------------------------------------------===//
545 // Load/Store instructions.
549 // Sign extending loads.
550 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
551 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
552 "lha $rD, $src", LdStLHA,
553 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
554 PPC970_DGroup_Cracked;
555 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
556 "lwa $rD, $src", LdStLWA,
558 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
559 PPC970_DGroup_Cracked;
560 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
561 "lhax $rD, $src", LdStLHA,
562 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
563 PPC970_DGroup_Cracked;
564 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
565 "lwax $rD, $src", LdStLHA,
566 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
567 PPC970_DGroup_Cracked;
570 let mayLoad = 1, neverHasSideEffects = 1 in {
571 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
573 "lhau $rD, $addr", LdStLHAU,
574 []>, RegConstraint<"$addr.reg = $ea_result">,
575 NoEncode<"$ea_result">;
578 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
580 "lhaux $rD, $addr", LdStLHAU,
581 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
582 NoEncode<"$ea_result">;
583 def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
585 "lwaux $rD, $addr", LdStLHAU,
586 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
587 NoEncode<"$ea_result">, isPPC64;
591 // Zero extending loads.
592 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
593 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
594 "lbz $rD, $src", LdStLoad,
595 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
596 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
597 "lhz $rD, $src", LdStLoad,
598 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
599 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
600 "lwz $rD, $src", LdStLoad,
601 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
603 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
604 "lbzx $rD, $src", LdStLoad,
605 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
606 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
607 "lhzx $rD, $src", LdStLoad,
608 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
609 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
610 "lwzx $rD, $src", LdStLoad,
611 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
615 let mayLoad = 1, neverHasSideEffects = 1 in {
616 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
617 "lbzu $rD, $addr", LdStLoadUpd,
618 []>, RegConstraint<"$addr.reg = $ea_result">,
619 NoEncode<"$ea_result">;
620 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
621 "lhzu $rD, $addr", LdStLoadUpd,
622 []>, RegConstraint<"$addr.reg = $ea_result">,
623 NoEncode<"$ea_result">;
624 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
625 "lwzu $rD, $addr", LdStLoadUpd,
626 []>, RegConstraint<"$addr.reg = $ea_result">,
627 NoEncode<"$ea_result">;
629 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
631 "lbzux $rD, $addr", LdStLoadUpd,
632 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
633 NoEncode<"$ea_result">;
634 def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
636 "lhzux $rD, $addr", LdStLoadUpd,
637 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
638 NoEncode<"$ea_result">;
639 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
641 "lwzux $rD, $addr", LdStLoadUpd,
642 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
643 NoEncode<"$ea_result">;
648 // Full 8-byte loads.
649 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
650 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
651 "ld $rD, $src", LdStLD,
652 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
653 // The following three definitions are selected for small code model only.
654 // Otherwise, we need to create two instructions to form a 32-bit offset,
655 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
656 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
659 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
660 def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
663 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
664 def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
667 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
669 let hasSideEffects = 1, isCodeGenOnly = 1 in {
670 let RST = 2, DS = 2 in
671 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
672 "ld 2, 8($reg)", LdStLD,
673 [(PPCload_toc i64:$reg)]>, isPPC64;
675 let RST = 2, DS = 10, RA = 1 in
676 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
677 "ld 2, 40(1)", LdStLD,
678 [(PPCtoc_restore)]>, isPPC64;
680 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
681 "ldx $rD, $src", LdStLD,
682 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
683 def LDBRX : XForm_1<31, 532, (outs G8RC:$rD), (ins memrr:$src),
684 "ldbrx $rD, $src", LdStLoad,
685 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
687 let mayLoad = 1, neverHasSideEffects = 1 in {
688 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
689 "ldu $rD, $addr", LdStLDU,
690 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
691 NoEncode<"$ea_result">;
693 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
695 "ldux $rD, $addr", LdStLDU,
696 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
697 NoEncode<"$ea_result">, isPPC64;
701 def : Pat<(PPCload ixaddr:$src),
703 def : Pat<(PPCload xaddr:$src),
706 // Support for medium and large code model.
707 def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, tocentry:$disp),
710 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
712 def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC_NOX0:$reg),
715 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
716 def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, tocentry:$disp),
719 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
721 // Support for thread-local storage.
722 def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
725 (PPCaddisGotTprelHA i64:$reg,
726 tglobaltlsaddr:$disp))]>,
728 def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC_NOX0:$reg),
731 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
733 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
734 (ADD8TLS $in, tglobaltlsaddr:$g)>;
735 def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
738 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
740 def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
743 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
745 def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
748 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
750 def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
753 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
755 def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
758 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
760 def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
763 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
765 def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
768 (PPCaddisDtprelHA i64:$reg,
769 tglobaltlsaddr:$disp))]>,
771 def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
774 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
777 let PPC970_Unit = 2 in {
778 // Truncating stores.
779 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
780 "stb $rS, $src", LdStStore,
781 [(truncstorei8 i64:$rS, iaddr:$src)]>;
782 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
783 "sth $rS, $src", LdStStore,
784 [(truncstorei16 i64:$rS, iaddr:$src)]>;
785 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
786 "stw $rS, $src", LdStStore,
787 [(truncstorei32 i64:$rS, iaddr:$src)]>;
788 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
789 "stbx $rS, $dst", LdStStore,
790 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
791 PPC970_DGroup_Cracked;
792 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
793 "sthx $rS, $dst", LdStStore,
794 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
795 PPC970_DGroup_Cracked;
796 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
797 "stwx $rS, $dst", LdStStore,
798 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
799 PPC970_DGroup_Cracked;
800 // Normal 8-byte stores.
801 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
802 "std $rS, $dst", LdStSTD,
803 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
804 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
805 "stdx $rS, $dst", LdStSTD,
806 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
807 PPC970_DGroup_Cracked;
808 def STDBRX: XForm_8<31, 660, (outs), (ins G8RC:$rS, memrr:$dst),
809 "stdbrx $rS, $dst", LdStStore,
810 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
811 PPC970_DGroup_Cracked;
814 // Stores with Update (pre-inc).
815 let PPC970_Unit = 2, mayStore = 1 in {
816 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
817 "stbu $rS, $dst", LdStStoreUpd, []>,
818 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
819 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
820 "sthu $rS, $dst", LdStStoreUpd, []>,
821 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
822 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
823 "stwu $rS, $dst", LdStStoreUpd, []>,
824 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
825 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst),
826 "stdu $rS, $dst", LdStSTDU, []>,
827 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
830 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
831 "stbux $rS, $dst", LdStStoreUpd, []>,
832 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
833 PPC970_DGroup_Cracked;
834 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
835 "sthux $rS, $dst", LdStStoreUpd, []>,
836 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
837 PPC970_DGroup_Cracked;
838 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
839 "stwux $rS, $dst", LdStStoreUpd, []>,
840 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
841 PPC970_DGroup_Cracked;
842 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
843 "stdux $rS, $dst", LdStSTDU, []>,
844 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
845 PPC970_DGroup_Cracked, isPPC64;
848 // Patterns to match the pre-inc stores. We can't put the patterns on
849 // the instruction definitions directly as ISel wants the address base
850 // and offset to be separate operands, not a single complex operand.
851 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
852 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
853 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
854 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
855 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
856 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
857 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
858 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
860 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
861 (STBUX8 $rS, $ptrreg, $ptroff)>;
862 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
863 (STHUX8 $rS, $ptrreg, $ptroff)>;
864 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
865 (STWUX8 $rS, $ptrreg, $ptroff)>;
866 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
867 (STDUX $rS, $ptrreg, $ptroff)>;
870 //===----------------------------------------------------------------------===//
871 // Floating point instructions.
875 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
876 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
877 "fcfid $frD, $frB", FPGeneral,
878 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
879 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
880 "fctidz $frD, $frB", FPGeneral,
881 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
883 def FCFIDU : XForm_26<63, 974, (outs F8RC:$frD), (ins F8RC:$frB),
884 "fcfidu $frD, $frB", FPGeneral,
885 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
886 def FCFIDS : XForm_26<59, 846, (outs F4RC:$frD), (ins F8RC:$frB),
887 "fcfids $frD, $frB", FPGeneral,
888 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
889 def FCFIDUS : XForm_26<59, 974, (outs F4RC:$frD), (ins F8RC:$frB),
890 "fcfidus $frD, $frB", FPGeneral,
891 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
892 def FCTIDUZ : XForm_26<63, 943, (outs F8RC:$frD), (ins F8RC:$frB),
893 "fctiduz $frD, $frB", FPGeneral,
894 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
895 def FCTIWUZ : XForm_26<63, 143, (outs F8RC:$frD), (ins F8RC:$frB),
896 "fctiwuz $frD, $frB", FPGeneral,
897 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
901 //===----------------------------------------------------------------------===//
902 // Instruction Patterns
905 // Extensions and truncates to/from 32-bit regs.
906 def : Pat<(i64 (zext i32:$in)),
907 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
909 def : Pat<(i64 (anyext i32:$in)),
910 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
911 def : Pat<(i32 (trunc i64:$in)),
912 (EXTRACT_SUBREG $in, sub_32)>;
914 // Extending loads with i64 targets.
915 def : Pat<(zextloadi1 iaddr:$src),
917 def : Pat<(zextloadi1 xaddr:$src),
919 def : Pat<(extloadi1 iaddr:$src),
921 def : Pat<(extloadi1 xaddr:$src),
923 def : Pat<(extloadi8 iaddr:$src),
925 def : Pat<(extloadi8 xaddr:$src),
927 def : Pat<(extloadi16 iaddr:$src),
929 def : Pat<(extloadi16 xaddr:$src),
931 def : Pat<(extloadi32 iaddr:$src),
933 def : Pat<(extloadi32 xaddr:$src),
936 // Standard shifts. These are represented separately from the real shifts above
937 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
939 def : Pat<(sra i64:$rS, i32:$rB),
941 def : Pat<(srl i64:$rS, i32:$rB),
943 def : Pat<(shl i64:$rS, i32:$rB),
947 def : Pat<(shl i64:$in, (i32 imm:$imm)),
948 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
949 def : Pat<(srl i64:$in, (i32 imm:$imm)),
950 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
953 def : Pat<(rotl i64:$in, i32:$sh),
954 (RLDCL $in, $sh, 0)>;
955 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
956 (RLDICL $in, imm:$imm, 0)>;
958 // Hi and Lo for Darwin Global Addresses.
959 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
960 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
961 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
962 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
963 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
964 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
965 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
966 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
967 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
968 (ADDIS8 $in, tglobaltlsaddr:$g)>;
969 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
970 (ADDI8 $in, tglobaltlsaddr:$g)>;
971 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
972 (ADDIS8 $in, tglobaladdr:$g)>;
973 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
974 (ADDIS8 $in, tconstpool:$g)>;
975 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
976 (ADDIS8 $in, tjumptable:$g)>;
977 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
978 (ADDIS8 $in, tblockaddress:$g)>;
980 // Patterns to match r+r indexed loads and stores for
981 // addresses without at least 4-byte alignment.
982 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
984 def : Pat<(i64 (unaligned4load xoaddr:$src)),
986 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
987 (STDX $rS, xoaddr:$dst)>;