1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
33 //===----------------------------------------------------------------------===//
34 // 64-bit transformation functions.
37 def SHL64 : SDNodeXForm<imm, [{
38 // Transformation function: 63 - imm
39 return getI32Imm(63 - N->getZExtValue());
42 def SRL64 : SDNodeXForm<imm, [{
43 // Transformation function: 64 - imm
44 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
47 def HI32_48 : SDNodeXForm<imm, [{
48 // Transformation function: shift the immediate value down into the low bits.
49 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
52 def HI48_64 : SDNodeXForm<imm, [{
53 // Transformation function: shift the immediate value down into the low bits.
54 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
58 //===----------------------------------------------------------------------===//
63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>,
67 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
68 // Convenient aliases for call instructions
70 def BL8_Darwin : IForm<18, 0, 1,
71 (outs), (ins calltarget:$func),
72 "bl $func", BrB, []>; // See Pat patterns below.
73 def BLA8_Darwin : IForm<18, 1, 1,
74 (outs), (ins aaddr:$func),
75 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>;
77 let Uses = [CTR8, RM] in {
78 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
81 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>;
85 // ELF 64 ABI Calls = Darwin ABI Calls
86 // Used to define BL8_ELF and BLA8_ELF
87 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
88 // Convenient aliases for call instructions
90 def BL8_ELF : IForm<18, 0, 1,
91 (outs), (ins calltarget:$func),
92 "bl $func", BrB, []>; // See Pat patterns below.
94 let isCodeGenOnly = 1 in
95 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24,
96 (outs), (ins calltarget:$func),
97 "bl $func\n\tnop", BrB, []>;
99 def BLA8_ELF : IForm<18, 1, 1,
100 (outs), (ins aaddr:$func),
101 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>;
103 let isCodeGenOnly = 1 in
104 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24,
105 (outs), (ins aaddr:$func),
106 "bla $func\n\tnop", BrB,
107 [(PPCcall_nop_SVR4 (i64 imm:$func))]>;
109 let Uses = [X11, CTR8, RM] in {
110 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
113 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>;
119 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
120 (BL8_Darwin tglobaladdr:$dst)>;
121 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
122 (BL8_Darwin texternalsym:$dst)>;
124 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
125 (BL8_ELF tglobaladdr:$dst)>;
126 def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)),
127 (BL8_NOP_ELF tglobaladdr:$dst)>;
129 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
130 (BL8_ELF texternalsym:$dst)>;
131 def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)),
132 (BL8_NOP_ELF texternalsym:$dst)>;
138 let usesCustomInserter = 1 in {
139 let Defs = [CR0] in {
140 def ATOMIC_LOAD_ADD_I64 : Pseudo<
141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
142 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
143 def ATOMIC_LOAD_SUB_I64 : Pseudo<
144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
145 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
146 def ATOMIC_LOAD_OR_I64 : Pseudo<
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
148 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
149 def ATOMIC_LOAD_XOR_I64 : Pseudo<
150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
151 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
152 def ATOMIC_LOAD_AND_I64 : Pseudo<
153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
154 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
155 def ATOMIC_LOAD_NAND_I64 : Pseudo<
156 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
157 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
159 def ATOMIC_CMP_SWAP_I64 : Pseudo<
160 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "",
162 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
164 def ATOMIC_SWAP_I64 : Pseudo<
165 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "",
166 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
170 // Instructions to support atomic operations
171 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
172 "ldarx $rD, $ptr", LdStLDARX,
173 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
176 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
177 "stdcx. $rS, $dst", LdStSTDCX,
178 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
181 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
182 def TCRETURNdi8 :Pseudo< (outs),
183 (ins calltarget:$dst, i32imm:$offset),
184 "#TC_RETURNd8 $dst $offset",
187 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
188 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
189 "#TC_RETURNa8 $func $offset",
190 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
192 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
193 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
194 "#TC_RETURNr8 $dst $offset",
198 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
199 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in {
200 let isReturn = 1 in {
201 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
202 Requires<[In64BitMode]>;
205 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
206 Requires<[In64BitMode]>;
210 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
211 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
212 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
217 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
218 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
219 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
223 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
224 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
226 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
227 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
229 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
230 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
232 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
233 let Defs = [CTR8], Uses = [CTR8] in {
234 def BDZ8 : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
235 "bdz $dst", BrB, []>;
236 def BDNZ8 : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
237 "bdnz $dst", BrB, []>;
241 // 64-but CR instructions
242 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
243 "mtcrf $FXM, $rS", BrMCRX>,
244 PPC970_MicroCode, PPC970_Unit_CRU;
246 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
248 PPC970_MicroCode, PPC970_Unit_CRU;
250 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
251 "mfcr $rT", SprMFCR>,
252 PPC970_MicroCode, PPC970_Unit_CRU;
254 //===----------------------------------------------------------------------===//
255 // 64-bit SPR manipulation instrs.
257 let Uses = [CTR8] in {
258 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
259 "mfctr $rT", SprMFSPR>,
260 PPC970_DGroup_First, PPC970_Unit_FXU;
262 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in {
263 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
264 "mtctr $rS", SprMTSPR>,
265 PPC970_DGroup_First, PPC970_Unit_FXU;
268 let Pattern = [(set G8RC:$rT, readcyclecounter)] in
269 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
270 "mfspr $rT, 268", SprMFTB>,
271 PPC970_DGroup_First, PPC970_Unit_FXU;
272 // Note that encoding mftb using mfspr is now the preferred form,
273 // and has been since at least ISA v2.03. The mftb instruction has
274 // now been phased out. Using mfspr, however, is known not to work on
277 let Defs = [X1], Uses = [X1] in
278 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"",
280 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
282 let Defs = [LR8] in {
283 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
284 "mtlr $rS", SprMTSPR>,
285 PPC970_DGroup_First, PPC970_Unit_FXU;
287 let Uses = [LR8] in {
288 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
289 "mflr $rT", SprMFSPR>,
290 PPC970_DGroup_First, PPC970_Unit_FXU;
293 //===----------------------------------------------------------------------===//
294 // Fixed point instructions.
297 let PPC970_Unit = 1 in { // FXU Operations.
299 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
300 "li $rD, $imm", IntSimple,
301 [(set G8RC:$rD, immSExt16:$imm)]>;
302 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
303 "lis $rD, $imm", IntSimple,
304 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
307 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
308 "nand $rA, $rS, $rB", IntSimple,
309 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
310 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
311 "and $rA, $rS, $rB", IntSimple,
312 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
313 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
314 "andc $rA, $rS, $rB", IntSimple,
315 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
316 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
317 "or $rA, $rS, $rB", IntSimple,
318 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
319 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
320 "nor $rA, $rS, $rB", IntSimple,
321 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
322 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
323 "orc $rA, $rS, $rB", IntSimple,
324 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
325 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
326 "eqv $rA, $rS, $rB", IntSimple,
327 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
328 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
329 "xor $rA, $rS, $rB", IntSimple,
330 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
332 // Logical ops with immediate.
333 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
334 "andi. $dst, $src1, $src2", IntGeneral,
335 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
337 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
338 "andis. $dst, $src1, $src2", IntGeneral,
339 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
341 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
342 "ori $dst, $src1, $src2", IntSimple,
343 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
344 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
345 "oris $dst, $src1, $src2", IntSimple,
346 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
347 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
348 "xori $dst, $src1, $src2", IntSimple,
349 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
350 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
351 "xoris $dst, $src1, $src2", IntSimple,
352 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
354 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
355 "add $rT, $rA, $rB", IntSimple,
356 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
358 let Defs = [CARRY] in {
359 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
360 "addc $rT, $rA, $rB", IntGeneral,
361 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
362 PPC970_DGroup_Cracked;
363 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
364 "addic $rD, $rA, $imm", IntGeneral,
365 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
367 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
368 "addi $rD, $rA, $imm", IntSimple,
369 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
370 def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, symbolLo64:$imm),
371 "addi $rD, $rA, $imm", IntSimple,
372 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
373 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
374 "addis $rD, $rA, $imm", IntSimple,
375 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
377 let Defs = [CARRY] in {
378 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
379 "subfic $rD, $rA, $imm", IntGeneral,
380 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
381 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
382 "subfc $rT, $rA, $rB", IntGeneral,
383 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
384 PPC970_DGroup_Cracked;
386 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
387 "subf $rT, $rA, $rB", IntGeneral,
388 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
389 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
390 "neg $rT, $rA", IntSimple,
391 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
392 let Uses = [CARRY], Defs = [CARRY] in {
393 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
394 "adde $rT, $rA, $rB", IntGeneral,
395 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
396 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
397 "addme $rT, $rA", IntGeneral,
398 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>;
399 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
400 "addze $rT, $rA", IntGeneral,
401 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
402 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
403 "subfe $rT, $rA, $rB", IntGeneral,
404 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
405 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
406 "subfme $rT, $rA", IntGeneral,
407 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>;
408 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
409 "subfze $rT, $rA", IntGeneral,
410 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
414 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
415 "mulhd $rT, $rA, $rB", IntMulHW,
416 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
417 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
418 "mulhdu $rT, $rA, $rB", IntMulHWU,
419 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
421 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
422 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
423 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
424 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
425 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
426 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
427 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
428 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
430 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
431 "sld $rA, $rS, $rB", IntRotateD,
432 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
433 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
434 "srd $rA, $rS, $rB", IntRotateD,
435 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
436 let Defs = [CARRY] in {
437 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
438 "srad $rA, $rS, $rB", IntRotateD,
439 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
442 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
443 "extsb $rA, $rS", IntSimple,
444 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
445 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
446 "extsh $rA, $rS", IntSimple,
447 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
449 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
450 "extsw $rA, $rS", IntSimple,
451 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
452 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
453 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
454 "extsw $rA, $rS", IntSimple,
455 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
456 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
457 "extsw $rA, $rS", IntSimple,
458 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
460 let Defs = [CARRY] in {
461 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
462 "sradi $rA, $rS, $SH", IntRotateD,
463 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
465 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
466 "cntlzd $rA, $rS", IntGeneral,
467 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
469 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
470 "divd $rT, $rA, $rB", IntDivD,
471 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
472 PPC970_DGroup_First, PPC970_DGroup_Cracked;
473 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
474 "divdu $rT, $rA, $rB", IntDivD,
475 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
476 PPC970_DGroup_First, PPC970_DGroup_Cracked;
477 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
478 "mulld $rT, $rA, $rB", IntMulHD,
479 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
482 let isCommutable = 1 in {
483 def RLDIMI : MDForm_1<30, 3,
484 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
485 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
486 []>, isPPC64, RegConstraint<"$rSi = $rA">,
490 // Rotate instructions.
491 def RLDCL : MDForm_1<30, 0,
492 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
493 "rldcl $rA, $rS, $rB, $MB", IntRotateD,
495 def RLDICL : MDForm_1<30, 0,
496 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
497 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
499 def RLDICR : MDForm_1<30, 1,
500 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
501 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
504 def RLWINM8 : MForm_2<21,
505 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
506 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
509 def ISEL8 : AForm_1<31, 15,
510 (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB, pred:$cond),
511 "isel $rT, $rA, $rB, $cond", IntGeneral,
513 } // End FXU Operations.
516 //===----------------------------------------------------------------------===//
517 // Load/Store instructions.
521 // Sign extending loads.
522 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
523 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
524 "lha $rD, $src", LdStLHA,
525 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
526 PPC970_DGroup_Cracked;
527 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
528 "lwa $rD, $src", LdStLWA,
529 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
530 PPC970_DGroup_Cracked;
531 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
532 "lhax $rD, $src", LdStLHA,
533 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
534 PPC970_DGroup_Cracked;
535 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
536 "lwax $rD, $src", LdStLHA,
537 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
538 PPC970_DGroup_Cracked;
542 def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
544 "lhau $rD, $disp($rA)", LdStLoad,
545 []>, RegConstraint<"$rA = $ea_result">,
546 NoEncode<"$ea_result">;
549 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result),
551 "lhaux $rD, $addr", LdStLoad,
552 []>, RegConstraint<"$addr.offreg = $ea_result">,
553 NoEncode<"$ea_result">;
554 def LWAUX : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result),
556 "lwaux $rD, $addr", LdStLoad,
557 []>, RegConstraint<"$addr.offreg = $ea_result">,
558 NoEncode<"$ea_result">, isPPC64;
561 // Zero extending loads.
562 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
563 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
564 "lbz $rD, $src", LdStLoad,
565 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
566 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
567 "lhz $rD, $src", LdStLoad,
568 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
569 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
570 "lwz $rD, $src", LdStLoad,
571 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
573 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
574 "lbzx $rD, $src", LdStLoad,
575 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
576 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
577 "lhzx $rD, $src", LdStLoad,
578 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
579 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
580 "lwzx $rD, $src", LdStLoad,
581 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
586 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
587 "lbzu $rD, $addr", LdStLoad,
588 []>, RegConstraint<"$addr.reg = $ea_result">,
589 NoEncode<"$ea_result">;
590 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
591 "lhzu $rD, $addr", LdStLoad,
592 []>, RegConstraint<"$addr.reg = $ea_result">,
593 NoEncode<"$ea_result">;
594 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
595 "lwzu $rD, $addr", LdStLoad,
596 []>, RegConstraint<"$addr.reg = $ea_result">,
597 NoEncode<"$ea_result">;
599 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc:$ea_result),
601 "lbzux $rD, $addr", LdStLoad,
602 []>, RegConstraint<"$addr.offreg = $ea_result">,
603 NoEncode<"$ea_result">;
604 def LHZUX8 : XForm_1<31, 331, (outs G8RC:$rD, ptr_rc:$ea_result),
606 "lhzux $rD, $addr", LdStLoad,
607 []>, RegConstraint<"$addr.offreg = $ea_result">,
608 NoEncode<"$ea_result">;
609 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc:$ea_result),
611 "lwzux $rD, $addr", LdStLoad,
612 []>, RegConstraint<"$addr.offreg = $ea_result">,
613 NoEncode<"$ea_result">;
618 // Full 8-byte loads.
619 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
620 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
621 "ld $rD, $src", LdStLD,
622 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
623 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
626 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
628 let hasSideEffects = 1 in {
629 let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
630 def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg),
631 "ld 2, 8($reg)", LdStLD,
632 [(PPCload_toc G8RC:$reg)]>, isPPC64;
634 let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
635 def LDtoc_restore : DSForm_1<58, 0, (outs), (ins),
636 "ld 2, 40(1)", LdStLD,
637 [(PPCtoc_restore)]>, isPPC64;
639 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
640 "ldx $rD, $src", LdStLD,
641 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
644 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
645 "ldu $rD, $addr", LdStLD,
646 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
647 NoEncode<"$ea_result">;
649 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc:$ea_result),
651 "ldux $rD, $addr", LdStLoad,
652 []>, RegConstraint<"$addr.offreg = $ea_result">,
653 NoEncode<"$ea_result">, isPPC64;
656 def : Pat<(PPCload ixaddr:$src),
658 def : Pat<(PPCload xaddr:$src),
661 let PPC970_Unit = 2 in {
662 // Truncating stores.
663 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
664 "stb $rS, $src", LdStStore,
665 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
666 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
667 "sth $rS, $src", LdStStore,
668 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
669 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
670 "stw $rS, $src", LdStStore,
671 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
672 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
673 "stbx $rS, $dst", LdStStore,
674 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
675 PPC970_DGroup_Cracked;
676 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
677 "sthx $rS, $dst", LdStStore,
678 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
679 PPC970_DGroup_Cracked;
680 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
681 "stwx $rS, $dst", LdStStore,
682 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
683 PPC970_DGroup_Cracked;
684 // Normal 8-byte stores.
685 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
686 "std $rS, $dst", LdStSTD,
687 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
688 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
689 "stdx $rS, $dst", LdStSTD,
690 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
691 PPC970_DGroup_Cracked;
694 let PPC970_Unit = 2 in {
696 def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
697 symbolLo:$ptroff, ptr_rc:$ptrreg),
698 "stbu $rS, $ptroff($ptrreg)", LdStStore,
699 [(set ptr_rc:$ea_res,
700 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
701 iaddroff:$ptroff))]>,
702 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
703 def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
704 symbolLo:$ptroff, ptr_rc:$ptrreg),
705 "sthu $rS, $ptroff($ptrreg)", LdStStore,
706 [(set ptr_rc:$ea_res,
707 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
708 iaddroff:$ptroff))]>,
709 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
711 def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
712 symbolLo:$ptroff, ptr_rc:$ptrreg),
713 "stwu $rS, $ptroff($ptrreg)", LdStStore,
714 [(set ptr_rc:$ea_res,
715 (pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg,
716 iaddroff:$ptroff))]>,
717 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
719 def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
720 s16immX4:$ptroff, ptr_rc:$ptrreg),
721 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
722 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
723 iaddroff:$ptroff))]>,
724 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
728 def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res),
729 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
730 "stbux $rS, $ptroff, $ptrreg", LdStStore,
731 [(set ptr_rc:$ea_res,
732 (pre_truncsti8 G8RC:$rS,
733 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
734 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
735 PPC970_DGroup_Cracked;
737 def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res),
738 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
739 "sthux $rS, $ptroff, $ptrreg", LdStStore,
740 [(set ptr_rc:$ea_res,
741 (pre_truncsti16 G8RC:$rS,
742 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
743 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
744 PPC970_DGroup_Cracked;
746 def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res),
747 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
748 "stwux $rS, $ptroff, $ptrreg", LdStStore,
749 [(set ptr_rc:$ea_res,
750 (pre_truncsti32 G8RC:$rS,
751 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
752 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
753 PPC970_DGroup_Cracked;
755 def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res),
756 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
757 "stdux $rS, $ptroff, $ptrreg", LdStStore,
758 [(set ptr_rc:$ea_res,
759 (pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
760 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
761 PPC970_DGroup_Cracked, isPPC64;
763 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
764 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
765 "std $rT, $dst", LdStSTD,
766 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
767 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
768 "stdx $rT, $dst", LdStSTD,
769 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
770 PPC970_DGroup_Cracked;
775 //===----------------------------------------------------------------------===//
776 // Floating point instructions.
780 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
781 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
782 "fcfid $frD, $frB", FPGeneral,
783 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
784 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
785 "fctidz $frD, $frB", FPGeneral,
786 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
790 //===----------------------------------------------------------------------===//
791 // Instruction Patterns
794 // Extensions and truncates to/from 32-bit regs.
795 def : Pat<(i64 (zext GPRC:$in)),
796 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32),
798 def : Pat<(i64 (anyext GPRC:$in)),
799 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>;
800 def : Pat<(i32 (trunc G8RC:$in)),
801 (EXTRACT_SUBREG G8RC:$in, sub_32)>;
803 // Extending loads with i64 targets.
804 def : Pat<(zextloadi1 iaddr:$src),
806 def : Pat<(zextloadi1 xaddr:$src),
808 def : Pat<(extloadi1 iaddr:$src),
810 def : Pat<(extloadi1 xaddr:$src),
812 def : Pat<(extloadi8 iaddr:$src),
814 def : Pat<(extloadi8 xaddr:$src),
816 def : Pat<(extloadi16 iaddr:$src),
818 def : Pat<(extloadi16 xaddr:$src),
820 def : Pat<(extloadi32 iaddr:$src),
822 def : Pat<(extloadi32 xaddr:$src),
825 // Standard shifts. These are represented separately from the real shifts above
826 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
828 def : Pat<(sra G8RC:$rS, GPRC:$rB),
829 (SRAD G8RC:$rS, GPRC:$rB)>;
830 def : Pat<(srl G8RC:$rS, GPRC:$rB),
831 (SRD G8RC:$rS, GPRC:$rB)>;
832 def : Pat<(shl G8RC:$rS, GPRC:$rB),
833 (SLD G8RC:$rS, GPRC:$rB)>;
836 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
837 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
838 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
839 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
842 def : Pat<(rotl G8RC:$in, GPRC:$sh),
843 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
844 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
845 (RLDICL G8RC:$in, imm:$imm, 0)>;
847 // Hi and Lo for Darwin Global Addresses.
848 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
849 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
850 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
851 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
852 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
853 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
854 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
855 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
856 def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in),
857 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>;
858 def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in),
859 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>;
860 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
861 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
862 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
863 (ADDIS8 G8RC:$in, tconstpool:$g)>;
864 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
865 (ADDIS8 G8RC:$in, tjumptable:$g)>;
866 def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
867 (ADDIS8 G8RC:$in, tblockaddress:$g)>;