1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
32 def tocentry : Operand<iPTR> {
33 let MIOperandInfo = (ops i64imm:$imm);
35 def tlsreg : Operand<i64> {
36 let EncoderMethod = "getTLSRegEncoding";
38 def tlsgd : Operand<i64> {}
40 //===----------------------------------------------------------------------===//
41 // 64-bit transformation functions.
44 def SHL64 : SDNodeXForm<imm, [{
45 // Transformation function: 63 - imm
46 return getI32Imm(63 - N->getZExtValue());
49 def SRL64 : SDNodeXForm<imm, [{
50 // Transformation function: 64 - imm
51 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
54 def HI32_48 : SDNodeXForm<imm, [{
55 // Transformation function: shift the immediate value down into the low bits.
56 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
59 def HI48_64 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
65 //===----------------------------------------------------------------------===//
69 let Interpretation64Bit = 1 in {
70 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
71 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
72 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
73 Requires<[In64BitMode]>;
75 let isCodeGenOnly = 1 in
76 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
77 "b${cond:cc}ctr ${cond:reg}", BrB, []>,
78 Requires<[In64BitMode]>;
83 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
86 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
87 let Defs = [CTR8], Uses = [CTR8] in {
88 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
90 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
94 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
95 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
97 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
104 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
105 // Convenient aliases for call instructions
107 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
108 "bl $func", BrB, []>; // See Pat patterns below.
110 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func),
111 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
113 let Uses = [RM], isCodeGenOnly = 1 in {
114 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
115 (outs), (ins calltarget:$func),
116 "bl $func\n\tnop", BrB, []>;
118 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
119 (outs), (ins calltarget:$func, tlsgd:$sym),
120 "bl $func($sym)\n\tnop", BrB, []>;
122 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
123 (outs), (ins calltarget:$func, tlsgd:$sym),
124 "bl $func($sym)\n\tnop", BrB, []>;
126 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
127 (outs), (ins aaddr:$func),
128 "bla $func\n\tnop", BrB,
129 [(PPCcall_nop (i64 imm:$func))]>;
131 let Uses = [CTR8, RM] in {
132 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
133 "bctrl", BrB, [(PPCbctrl)]>,
134 Requires<[In64BitMode]>;
136 let isCodeGenOnly = 1 in
137 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
138 "b${cond:cc}ctrl ${cond:reg}", BrB, []>,
139 Requires<[In64BitMode]>;
142 } // Interpretation64Bit
145 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
146 (BL8 tglobaladdr:$dst)>;
147 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
148 (BL8_NOP tglobaladdr:$dst)>;
150 def : Pat<(PPCcall (i64 texternalsym:$dst)),
151 (BL8 texternalsym:$dst)>;
152 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
153 (BL8_NOP texternalsym:$dst)>;
156 let usesCustomInserter = 1 in {
157 let Defs = [CR0] in {
158 def ATOMIC_LOAD_ADD_I64 : Pseudo<
159 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
160 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
161 def ATOMIC_LOAD_SUB_I64 : Pseudo<
162 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
163 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
164 def ATOMIC_LOAD_OR_I64 : Pseudo<
165 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
166 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
167 def ATOMIC_LOAD_XOR_I64 : Pseudo<
168 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
169 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
170 def ATOMIC_LOAD_AND_I64 : Pseudo<
171 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
172 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
173 def ATOMIC_LOAD_NAND_I64 : Pseudo<
174 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
175 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
177 def ATOMIC_CMP_SWAP_I64 : Pseudo<
178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
179 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
181 def ATOMIC_SWAP_I64 : Pseudo<
182 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
183 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
187 // Instructions to support atomic operations
188 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
189 "ldarx $rD, $ptr", LdStLDARX,
190 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
193 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
194 "stdcx. $rS, $dst", LdStSTDCX,
195 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
198 let Interpretation64Bit = 1 in {
199 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
200 def TCRETURNdi8 :Pseudo< (outs),
201 (ins calltarget:$dst, i32imm:$offset),
202 "#TC_RETURNd8 $dst $offset",
205 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
206 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
207 "#TC_RETURNa8 $func $offset",
208 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
210 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
211 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
212 "#TC_RETURNr8 $dst $offset",
215 let isCodeGenOnly = 1 in {
217 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
218 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
219 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
220 Requires<[In64BitMode]>;
223 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
224 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
225 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
230 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
231 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
232 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
237 } // Interpretation64Bit
239 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
240 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
242 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
243 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
245 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
246 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
249 // 64-bit CR instructions
250 let Interpretation64Bit = 1 in {
251 let neverHasSideEffects = 1 in {
252 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS),
253 "mtcrf $FXM, $rS", BrMCRX>,
254 PPC970_MicroCode, PPC970_Unit_CRU;
256 let isCodeGenOnly = 1 in
257 def MFCR8pseud: XFXForm_3<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
258 "#MFCR8pseud", SprMFCR>,
259 PPC970_MicroCode, PPC970_Unit_CRU;
260 } // neverHasSideEffects = 1
262 let neverHasSideEffects = 1 in
263 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
264 "mfcr $rT", SprMFCR>,
265 PPC970_MicroCode, PPC970_Unit_CRU;
267 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
268 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
270 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
271 Requires<[In64BitMode]>;
272 let isTerminator = 1 in
273 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
274 "#EH_SJLJ_LONGJMP64",
275 [(PPCeh_sjlj_longjmp addr:$buf)]>,
276 Requires<[In64BitMode]>;
279 //===----------------------------------------------------------------------===//
280 // 64-bit SPR manipulation instrs.
282 let Uses = [CTR8] in {
283 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
284 "mfctr $rT", SprMFSPR>,
285 PPC970_DGroup_First, PPC970_Unit_FXU;
287 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
288 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
289 "mtctr $rS", SprMTSPR>,
290 PPC970_DGroup_First, PPC970_Unit_FXU;
293 let Pattern = [(set i64:$rT, readcyclecounter)] in
294 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
295 "mfspr $rT, 268", SprMFTB>,
296 PPC970_DGroup_First, PPC970_Unit_FXU;
297 // Note that encoding mftb using mfspr is now the preferred form,
298 // and has been since at least ISA v2.03. The mftb instruction has
299 // now been phased out. Using mfspr, however, is known not to work on
302 let Defs = [X1], Uses = [X1] in
303 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
305 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
307 let Defs = [LR8] in {
308 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
309 "mtlr $rS", SprMTSPR>,
310 PPC970_DGroup_First, PPC970_Unit_FXU;
312 let Uses = [LR8] in {
313 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
314 "mflr $rT", SprMFSPR>,
315 PPC970_DGroup_First, PPC970_Unit_FXU;
317 } // Interpretation64Bit
319 //===----------------------------------------------------------------------===//
320 // Fixed point instructions.
323 let PPC970_Unit = 1 in { // FXU Operations.
324 let Interpretation64Bit = 1 in {
325 let neverHasSideEffects = 1 in {
327 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
328 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins symbolLo64:$imm),
329 "li $rD, $imm", IntSimple,
330 [(set i64:$rD, immSExt16:$imm)]>;
331 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins symbolHi64:$imm),
332 "lis $rD, $imm", IntSimple,
333 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
337 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
338 "nand", "$rA, $rS, $rB", IntSimple,
339 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
340 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
341 "and", "$rA, $rS, $rB", IntSimple,
342 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
343 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
344 "andc", "$rA, $rS, $rB", IntSimple,
345 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
346 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
347 "or", "$rA, $rS, $rB", IntSimple,
348 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
349 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
350 "nor", "$rA, $rS, $rB", IntSimple,
351 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
352 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
353 "orc", "$rA, $rS, $rB", IntSimple,
354 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
355 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
356 "eqv", "$rA, $rS, $rB", IntSimple,
357 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
358 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
359 "xor", "$rA, $rS, $rB", IntSimple,
360 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
362 // Logical ops with immediate.
363 let Defs = [CR0] in {
364 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
365 "andi. $dst, $src1, $src2", IntGeneral,
366 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
368 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
369 "andis. $dst, $src1, $src2", IntGeneral,
370 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
373 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
374 "ori $dst, $src1, $src2", IntSimple,
375 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
376 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
377 "oris $dst, $src1, $src2", IntSimple,
378 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
379 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
380 "xori $dst, $src1, $src2", IntSimple,
381 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
382 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
383 "xoris $dst, $src1, $src2", IntSimple,
384 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
386 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
387 "add", "$rT, $rA, $rB", IntSimple,
388 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
389 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
390 // initial-exec thread-local storage model.
391 let isCodeGenOnly = 1 in
392 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
393 "add $rT, $rA, $rB@tls", IntSimple,
394 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
396 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
397 "addc", "$rT, $rA, $rB", IntGeneral,
398 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
399 PPC970_DGroup_Cracked;
400 let Defs = [CARRY] in
401 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
402 "addic $rD, $rA, $imm", IntGeneral,
403 [(set i64:$rD, (addc i64:$rA, immSExt16:$imm))]>;
404 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, symbolLo64:$imm),
405 "addi $rD, $rA, $imm", IntSimple,
406 [(set i64:$rD, (add i64:$rA, immSExt16:$imm))]>;
407 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, symbolHi64:$imm),
408 "addis $rD, $rA, $imm", IntSimple,
409 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
411 let Defs = [CARRY] in {
412 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
413 "subfic $rD, $rA, $imm", IntGeneral,
414 [(set i64:$rD, (subc immSExt16:$imm, i64:$rA))]>;
415 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
416 "subfc", "$rT, $rA, $rB", IntGeneral,
417 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
418 PPC970_DGroup_Cracked;
420 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
421 "subf", "$rT, $rA, $rB", IntGeneral,
422 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
423 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
424 "neg", "$rT, $rA", IntSimple,
425 [(set i64:$rT, (ineg i64:$rA))]>;
426 let Uses = [CARRY] in {
427 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
428 "adde", "$rT, $rA, $rB", IntGeneral,
429 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
430 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
431 "addme", "$rT, $rA", IntGeneral,
432 [(set i64:$rT, (adde i64:$rA, -1))]>;
433 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
434 "addze", "$rT, $rA", IntGeneral,
435 [(set i64:$rT, (adde i64:$rA, 0))]>;
436 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
437 "subfe", "$rT, $rA, $rB", IntGeneral,
438 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
439 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
440 "subfme", "$rT, $rA", IntGeneral,
441 [(set i64:$rT, (sube -1, i64:$rA))]>;
442 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
443 "subfze", "$rT, $rA", IntGeneral,
444 [(set i64:$rT, (sube 0, i64:$rA))]>;
448 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
449 "mulhd", "$rT, $rA, $rB", IntMulHW,
450 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
451 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
452 "mulhdu", "$rT, $rA, $rB", IntMulHWU,
453 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
455 } // Interpretation64Bit
457 let isCompare = 1, neverHasSideEffects = 1 in {
458 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
459 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
460 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
461 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
462 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
463 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
464 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
465 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
468 let neverHasSideEffects = 1 in {
469 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
470 "sld", "$rA, $rS, $rB", IntRotateD,
471 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
472 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
473 "srd", "$rA, $rS, $rB", IntRotateD,
474 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
475 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
476 "srad", "$rA, $rS, $rB", IntRotateD,
477 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
479 let Interpretation64Bit = 1 in {
480 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
481 "extsb", "$rA, $rS", IntSimple,
482 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
483 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
484 "extsh", "$rA, $rS", IntSimple,
485 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
486 } // Interpretation64Bit
488 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
489 "extsw", "$rA, $rS", IntSimple,
490 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
491 let Interpretation64Bit = 1 in
492 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
493 "extsw", "$rA, $rS", IntSimple,
494 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
496 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
497 "sradi", "$rA, $rS, $SH", IntRotateDI,
498 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
499 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
500 "cntlzd", "$rA, $rS", IntGeneral,
501 [(set i64:$rA, (ctlz i64:$rS))]>;
502 defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
503 "popcntd", "$rA, $rS", IntGeneral,
504 [(set i64:$rA, (ctpop i64:$rS))]>;
506 // popcntw also does a population count on the high 32 bits (storing the
507 // results in the high 32-bits of the output). We'll ignore that here (which is
508 // safe because we never separately use the high part of the 64-bit registers).
509 defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
510 "popcntw", "$rA, $rS", IntGeneral,
511 [(set i32:$rA, (ctpop i32:$rS))]>;
513 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
514 "divd", "$rT, $rA, $rB", IntDivD,
515 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
516 PPC970_DGroup_First, PPC970_DGroup_Cracked;
517 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
518 "divdu", "$rT, $rA, $rB", IntDivD,
519 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
520 PPC970_DGroup_First, PPC970_DGroup_Cracked;
521 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
522 "mulld", "$rT, $rA, $rB", IntMulHD,
523 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
526 let neverHasSideEffects = 1 in {
527 let isCommutable = 1 in {
528 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
529 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
530 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
531 []>, isPPC64, RegConstraint<"$rSi = $rA">,
535 // Rotate instructions.
536 defm RLDCL : MDSForm_1r<30, 8,
537 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
538 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
540 defm RLDICL : MDForm_1r<30, 0,
541 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
542 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
544 defm RLDICR : MDForm_1r<30, 1,
545 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
546 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
549 let Interpretation64Bit = 1 in {
550 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
551 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
552 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
556 def ISEL8 : AForm_4<31, 15,
557 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
558 "isel $rT, $rA, $rB, $cond", IntGeneral,
560 } // Interpretation64Bit
561 } // neverHasSideEffects = 1
562 } // End FXU Operations.
565 //===----------------------------------------------------------------------===//
566 // Load/Store instructions.
570 // Sign extending loads.
571 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
572 let Interpretation64Bit = 1 in
573 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
574 "lha $rD, $src", LdStLHA,
575 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
576 PPC970_DGroup_Cracked;
577 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
578 "lwa $rD, $src", LdStLWA,
580 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
581 PPC970_DGroup_Cracked;
582 let Interpretation64Bit = 1 in
583 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
584 "lhax $rD, $src", LdStLHA,
585 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
586 PPC970_DGroup_Cracked;
587 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
588 "lwax $rD, $src", LdStLHA,
589 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
590 PPC970_DGroup_Cracked;
593 let mayLoad = 1, neverHasSideEffects = 1 in {
594 let Interpretation64Bit = 1 in
595 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
597 "lhau $rD, $addr", LdStLHAU,
598 []>, RegConstraint<"$addr.reg = $ea_result">,
599 NoEncode<"$ea_result">;
602 let Interpretation64Bit = 1 in
603 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
605 "lhaux $rD, $addr", LdStLHAU,
606 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
607 NoEncode<"$ea_result">;
608 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
610 "lwaux $rD, $addr", LdStLHAU,
611 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
612 NoEncode<"$ea_result">, isPPC64;
616 let Interpretation64Bit = 1 in {
617 // Zero extending loads.
618 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
619 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
620 "lbz $rD, $src", LdStLoad,
621 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
622 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
623 "lhz $rD, $src", LdStLoad,
624 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
625 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
626 "lwz $rD, $src", LdStLoad,
627 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
629 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
630 "lbzx $rD, $src", LdStLoad,
631 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
632 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
633 "lhzx $rD, $src", LdStLoad,
634 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
635 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
636 "lwzx $rD, $src", LdStLoad,
637 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
641 let mayLoad = 1, neverHasSideEffects = 1 in {
642 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
643 "lbzu $rD, $addr", LdStLoadUpd,
644 []>, RegConstraint<"$addr.reg = $ea_result">,
645 NoEncode<"$ea_result">;
646 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
647 "lhzu $rD, $addr", LdStLoadUpd,
648 []>, RegConstraint<"$addr.reg = $ea_result">,
649 NoEncode<"$ea_result">;
650 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
651 "lwzu $rD, $addr", LdStLoadUpd,
652 []>, RegConstraint<"$addr.reg = $ea_result">,
653 NoEncode<"$ea_result">;
655 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
657 "lbzux $rD, $addr", LdStLoadUpd,
658 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
659 NoEncode<"$ea_result">;
660 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
662 "lhzux $rD, $addr", LdStLoadUpd,
663 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
664 NoEncode<"$ea_result">;
665 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
667 "lwzux $rD, $addr", LdStLoadUpd,
668 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
669 NoEncode<"$ea_result">;
672 } // Interpretation64Bit
675 // Full 8-byte loads.
676 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
677 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
678 "ld $rD, $src", LdStLD,
679 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
680 // The following three definitions are selected for small code model only.
681 // Otherwise, we need to create two instructions to form a 32-bit offset,
682 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
683 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
686 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
687 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
690 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
691 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
694 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
696 let hasSideEffects = 1, isCodeGenOnly = 1 in {
697 let RST = 2, DS = 2 in
698 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
699 "ld 2, 8($reg)", LdStLD,
700 [(PPCload_toc i64:$reg)]>, isPPC64;
702 let RST = 2, DS = 10, RA = 1 in
703 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
704 "ld 2, 40(1)", LdStLD,
705 [(PPCtoc_restore)]>, isPPC64;
707 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
708 "ldx $rD, $src", LdStLD,
709 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
710 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
711 "ldbrx $rD, $src", LdStLoad,
712 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
714 let mayLoad = 1, neverHasSideEffects = 1 in {
715 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
716 "ldu $rD, $addr", LdStLDU,
717 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
718 NoEncode<"$ea_result">;
720 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
722 "ldux $rD, $addr", LdStLDU,
723 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
724 NoEncode<"$ea_result">, isPPC64;
728 def : Pat<(PPCload ixaddr:$src),
730 def : Pat<(PPCload xaddr:$src),
733 // Support for medium and large code model.
734 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
737 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
739 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
742 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
743 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
746 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
748 // Support for thread-local storage.
749 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
752 (PPCaddisGotTprelHA i64:$reg,
753 tglobaltlsaddr:$disp))]>,
755 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins symbolLo64:$disp, g8rc_nox0:$reg),
758 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
760 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
761 (ADD8TLS $in, tglobaltlsaddr:$g)>;
762 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
765 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
767 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp),
770 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
772 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
775 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
777 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
780 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
782 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp),
785 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
787 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
790 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
792 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
795 (PPCaddisDtprelHA i64:$reg,
796 tglobaltlsaddr:$disp))]>,
798 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp),
801 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
804 let PPC970_Unit = 2 in {
805 let Interpretation64Bit = 1 in {
806 // Truncating stores.
807 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
808 "stb $rS, $src", LdStStore,
809 [(truncstorei8 i64:$rS, iaddr:$src)]>;
810 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
811 "sth $rS, $src", LdStStore,
812 [(truncstorei16 i64:$rS, iaddr:$src)]>;
813 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
814 "stw $rS, $src", LdStStore,
815 [(truncstorei32 i64:$rS, iaddr:$src)]>;
816 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
817 "stbx $rS, $dst", LdStStore,
818 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
819 PPC970_DGroup_Cracked;
820 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
821 "sthx $rS, $dst", LdStStore,
822 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
823 PPC970_DGroup_Cracked;
824 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
825 "stwx $rS, $dst", LdStStore,
826 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
827 PPC970_DGroup_Cracked;
828 } // Interpretation64Bit
830 // Normal 8-byte stores.
831 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
832 "std $rS, $dst", LdStSTD,
833 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
834 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
835 "stdx $rS, $dst", LdStSTD,
836 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
837 PPC970_DGroup_Cracked;
838 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
839 "stdbrx $rS, $dst", LdStStore,
840 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
841 PPC970_DGroup_Cracked;
844 // Stores with Update (pre-inc).
845 let PPC970_Unit = 2, mayStore = 1 in {
846 let Interpretation64Bit = 1 in {
847 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
848 "stbu $rS, $dst", LdStStoreUpd, []>,
849 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
850 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
851 "sthu $rS, $dst", LdStStoreUpd, []>,
852 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
853 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
854 "stwu $rS, $dst", LdStStoreUpd, []>,
855 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
856 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
857 "stdu $rS, $dst", LdStSTDU, []>,
858 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
861 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
862 "stbux $rS, $dst", LdStStoreUpd, []>,
863 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
864 PPC970_DGroup_Cracked;
865 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
866 "sthux $rS, $dst", LdStStoreUpd, []>,
867 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
868 PPC970_DGroup_Cracked;
869 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
870 "stwux $rS, $dst", LdStStoreUpd, []>,
871 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
872 PPC970_DGroup_Cracked;
873 } // Interpretation64Bit
875 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
876 "stdux $rS, $dst", LdStSTDU, []>,
877 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
878 PPC970_DGroup_Cracked, isPPC64;
881 // Patterns to match the pre-inc stores. We can't put the patterns on
882 // the instruction definitions directly as ISel wants the address base
883 // and offset to be separate operands, not a single complex operand.
884 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
885 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
886 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
887 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
888 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
889 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
890 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
891 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
893 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
894 (STBUX8 $rS, $ptrreg, $ptroff)>;
895 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
896 (STHUX8 $rS, $ptrreg, $ptroff)>;
897 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
898 (STWUX8 $rS, $ptrreg, $ptroff)>;
899 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
900 (STDUX $rS, $ptrreg, $ptroff)>;
903 //===----------------------------------------------------------------------===//
904 // Floating point instructions.
908 let PPC970_Unit = 3, neverHasSideEffects = 1,
909 Uses = [RM] in { // FPU Operations.
910 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
911 "fcfid", "$frD, $frB", FPGeneral,
912 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
913 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
914 "fctidz", "$frD, $frB", FPGeneral,
915 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
917 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
918 "fcfidu", "$frD, $frB", FPGeneral,
919 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
920 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
921 "fcfids", "$frD, $frB", FPGeneral,
922 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
923 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
924 "fcfidus", "$frD, $frB", FPGeneral,
925 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
926 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
927 "fctiduz", "$frD, $frB", FPGeneral,
928 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
929 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
930 "fctiwuz", "$frD, $frB", FPGeneral,
931 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
935 //===----------------------------------------------------------------------===//
936 // Instruction Patterns
939 // Extensions and truncates to/from 32-bit regs.
940 def : Pat<(i64 (zext i32:$in)),
941 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
943 def : Pat<(i64 (anyext i32:$in)),
944 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
945 def : Pat<(i32 (trunc i64:$in)),
946 (EXTRACT_SUBREG $in, sub_32)>;
948 // Extending loads with i64 targets.
949 def : Pat<(zextloadi1 iaddr:$src),
951 def : Pat<(zextloadi1 xaddr:$src),
953 def : Pat<(extloadi1 iaddr:$src),
955 def : Pat<(extloadi1 xaddr:$src),
957 def : Pat<(extloadi8 iaddr:$src),
959 def : Pat<(extloadi8 xaddr:$src),
961 def : Pat<(extloadi16 iaddr:$src),
963 def : Pat<(extloadi16 xaddr:$src),
965 def : Pat<(extloadi32 iaddr:$src),
967 def : Pat<(extloadi32 xaddr:$src),
970 // Standard shifts. These are represented separately from the real shifts above
971 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
973 def : Pat<(sra i64:$rS, i32:$rB),
975 def : Pat<(srl i64:$rS, i32:$rB),
977 def : Pat<(shl i64:$rS, i32:$rB),
981 def : Pat<(shl i64:$in, (i32 imm:$imm)),
982 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
983 def : Pat<(srl i64:$in, (i32 imm:$imm)),
984 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
987 def : Pat<(rotl i64:$in, i32:$sh),
988 (RLDCL $in, $sh, 0)>;
989 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
990 (RLDICL $in, imm:$imm, 0)>;
992 // Hi and Lo for Darwin Global Addresses.
993 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
994 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
995 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
996 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
997 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
998 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
999 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1000 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1001 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1002 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1003 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1004 (ADDI8 $in, tglobaltlsaddr:$g)>;
1005 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1006 (ADDIS8 $in, tglobaladdr:$g)>;
1007 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1008 (ADDIS8 $in, tconstpool:$g)>;
1009 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1010 (ADDIS8 $in, tjumptable:$g)>;
1011 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1012 (ADDIS8 $in, tblockaddress:$g)>;
1014 // Patterns to match r+r indexed loads and stores for
1015 // addresses without at least 4-byte alignment.
1016 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1017 (LWAX xoaddr:$src)>;
1018 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1020 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1021 (STDX $rS, xoaddr:$dst)>;