1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue());
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
67 def HI32_48 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
72 def HI48_64 : SDNodeXForm<imm, [{
73 // Transformation function: shift the immediate value down into the low bits.
74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
78 //===----------------------------------------------------------------------===//
82 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
83 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
84 let isReturn = 1, Uses = [LR8, RM] in
85 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
86 [(retflag)]>, Requires<[In64BitMode]>;
87 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
88 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
90 Requires<[In64BitMode]>;
91 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
92 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
94 Requires<[In64BitMode]>;
96 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
97 "bcctr 12, $bi, 0", IIC_BrB, []>,
98 Requires<[In64BitMode]>;
99 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
100 "bcctr 4, $bi, 0", IIC_BrB, []>,
101 Requires<[In64BitMode]>;
106 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
109 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
110 let Defs = [CTR8], Uses = [CTR8] in {
111 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
113 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
117 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
118 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
119 "bdzlr", IIC_BrB, []>;
120 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
121 "bdnzlr", IIC_BrB, []>;
127 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
128 // Convenient aliases for call instructions
130 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
131 "bl $func", IIC_BrB, []>; // See Pat patterns below.
133 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
134 "bl $func", IIC_BrB, []>;
136 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
137 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
139 let Uses = [RM], isCodeGenOnly = 1 in {
140 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
141 (outs), (ins calltarget:$func),
142 "bl $func\n\tnop", IIC_BrB, []>;
144 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
145 (outs), (ins tlscall:$func),
146 "bl $func\n\tnop", IIC_BrB, []>;
148 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
149 (outs), (ins abscalltarget:$func),
150 "bla $func\n\tnop", IIC_BrB,
151 [(PPCcall_nop (i64 imm:$func))]>;
153 let Uses = [CTR8, RM] in {
154 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
155 "bctrl", IIC_BrB, [(PPCbctrl)]>,
156 Requires<[In64BitMode]>;
158 let isCodeGenOnly = 1 in {
159 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
160 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
162 Requires<[In64BitMode]>;
164 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
165 "bcctrl 12, $bi, 0", IIC_BrB, []>,
166 Requires<[In64BitMode]>;
167 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
168 "bcctrl 4, $bi, 0", IIC_BrB, []>,
169 Requires<[In64BitMode]>;
174 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
175 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {
176 def BCTRL8_LDinto_toc :
177 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
179 "bctrl\n\tld 2, $src", IIC_BrB,
180 [(PPCbctrl_load_toc ixaddr:$src)]>,
181 Requires<[In64BitMode]>;
184 } // Interpretation64Bit
186 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
187 // previous definition must be marked as CodeGen only to prevent decoding
189 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
190 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
191 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
192 "bl $func", IIC_BrB, []>;
195 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
196 (BL8 tglobaladdr:$dst)>;
197 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
198 (BL8_NOP tglobaladdr:$dst)>;
200 def : Pat<(PPCcall (i64 texternalsym:$dst)),
201 (BL8 texternalsym:$dst)>;
202 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
203 (BL8_NOP texternalsym:$dst)>;
206 let usesCustomInserter = 1 in {
207 let Defs = [CR0] in {
208 def ATOMIC_LOAD_ADD_I64 : Pseudo<
209 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
210 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
211 def ATOMIC_LOAD_SUB_I64 : Pseudo<
212 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
213 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
214 def ATOMIC_LOAD_OR_I64 : Pseudo<
215 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
216 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
217 def ATOMIC_LOAD_XOR_I64 : Pseudo<
218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
219 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
220 def ATOMIC_LOAD_AND_I64 : Pseudo<
221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
222 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
223 def ATOMIC_LOAD_NAND_I64 : Pseudo<
224 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
225 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
227 def ATOMIC_CMP_SWAP_I64 : Pseudo<
228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
229 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
231 def ATOMIC_SWAP_I64 : Pseudo<
232 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
233 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
237 // Instructions to support atomic operations
238 let mayLoad = 1, hasSideEffects = 0 in {
239 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
240 "ldarx $rD, $ptr", IIC_LdStLDARX, []>;
242 // Instruction to support lock versions of atomics
243 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
244 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
245 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
248 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
249 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
250 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
252 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
253 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
254 def TCRETURNdi8 :Pseudo< (outs),
255 (ins calltarget:$dst, i32imm:$offset),
256 "#TC_RETURNd8 $dst $offset",
259 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
260 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
261 "#TC_RETURNa8 $func $offset",
262 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
264 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
265 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
266 "#TC_RETURNr8 $dst $offset",
269 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
270 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
271 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
273 Requires<[In64BitMode]>;
275 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
276 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
277 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
281 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
282 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
283 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
286 } // Interpretation64Bit
288 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
289 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
291 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
292 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
294 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
295 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
298 // 64-bit CR instructions
299 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
300 let hasSideEffects = 0 in {
301 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
302 "mtocrf $FXM, $ST", IIC_BrMCRX>,
303 PPC970_DGroup_First, PPC970_Unit_CRU;
305 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
306 "mtcrf $FXM, $rS", IIC_BrMCRX>,
307 PPC970_MicroCode, PPC970_Unit_CRU;
309 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
310 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
311 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
312 PPC970_DGroup_First, PPC970_Unit_CRU;
314 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
315 "mfcr $rT", IIC_SprMFCR>,
316 PPC970_MicroCode, PPC970_Unit_CRU;
317 } // hasSideEffects = 0
319 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
321 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
323 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
324 Requires<[In64BitMode]>;
325 let isTerminator = 1 in
326 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
327 "#EH_SJLJ_LONGJMP64",
328 [(PPCeh_sjlj_longjmp addr:$buf)]>,
329 Requires<[In64BitMode]>;
332 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR),
333 "mfspr $RT, $SPR", IIC_SprMFSPR>;
334 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT),
335 "mtspr $SPR, $RT", IIC_SprMTSPR>;
338 //===----------------------------------------------------------------------===//
339 // 64-bit SPR manipulation instrs.
341 let Uses = [CTR8] in {
342 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
343 "mfctr $rT", IIC_SprMFSPR>,
344 PPC970_DGroup_First, PPC970_Unit_FXU;
346 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
347 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
348 "mtctr $rS", IIC_SprMTSPR>,
349 PPC970_DGroup_First, PPC970_Unit_FXU;
351 let hasSideEffects = 1, Defs = [CTR8] in {
352 let Pattern = [(int_ppc_mtctr i64:$rS)] in
353 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
354 "mtctr $rS", IIC_SprMTSPR>,
355 PPC970_DGroup_First, PPC970_Unit_FXU;
358 let Pattern = [(set i64:$rT, readcyclecounter)] in
359 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
360 "mfspr $rT, 268", IIC_SprMFTB>,
361 PPC970_DGroup_First, PPC970_Unit_FXU;
362 // Note that encoding mftb using mfspr is now the preferred form,
363 // and has been since at least ISA v2.03. The mftb instruction has
364 // now been phased out. Using mfspr, however, is known not to work on
367 let Defs = [X1], Uses = [X1] in
368 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
370 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
372 let Defs = [LR8] in {
373 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
374 "mtlr $rS", IIC_SprMTSPR>,
375 PPC970_DGroup_First, PPC970_Unit_FXU;
377 let Uses = [LR8] in {
378 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
379 "mflr $rT", IIC_SprMFSPR>,
380 PPC970_DGroup_First, PPC970_Unit_FXU;
382 } // Interpretation64Bit
384 //===----------------------------------------------------------------------===//
385 // Fixed point instructions.
388 let PPC970_Unit = 1 in { // FXU Operations.
389 let Interpretation64Bit = 1 in {
390 let hasSideEffects = 0 in {
391 let isCodeGenOnly = 1 in {
393 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
394 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
395 "li $rD, $imm", IIC_IntSimple,
396 [(set i64:$rD, imm64SExt16:$imm)]>;
397 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
398 "lis $rD, $imm", IIC_IntSimple,
399 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
403 let isCommutable = 1 in {
404 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
405 "nand", "$rA, $rS, $rB", IIC_IntSimple,
406 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
407 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
408 "and", "$rA, $rS, $rB", IIC_IntSimple,
409 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
411 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
412 "andc", "$rA, $rS, $rB", IIC_IntSimple,
413 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
414 let isCommutable = 1 in {
415 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
416 "or", "$rA, $rS, $rB", IIC_IntSimple,
417 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
418 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
419 "nor", "$rA, $rS, $rB", IIC_IntSimple,
420 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
422 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
423 "orc", "$rA, $rS, $rB", IIC_IntSimple,
424 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
425 let isCommutable = 1 in {
426 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
427 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
428 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
429 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
430 "xor", "$rA, $rS, $rB", IIC_IntSimple,
431 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
432 } // let isCommutable = 1
434 // Logical ops with immediate.
435 let Defs = [CR0] in {
436 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
437 "andi. $dst, $src1, $src2", IIC_IntGeneral,
438 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
440 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
441 "andis. $dst, $src1, $src2", IIC_IntGeneral,
442 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
445 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
446 "ori $dst, $src1, $src2", IIC_IntSimple,
447 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
448 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
449 "oris $dst, $src1, $src2", IIC_IntSimple,
450 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
451 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
452 "xori $dst, $src1, $src2", IIC_IntSimple,
453 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
454 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
455 "xoris $dst, $src1, $src2", IIC_IntSimple,
456 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
458 let isCommutable = 1 in
459 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
460 "add", "$rT, $rA, $rB", IIC_IntSimple,
461 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
462 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
463 // initial-exec thread-local storage model.
464 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
465 "add $rT, $rA, $rB", IIC_IntSimple,
466 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
468 let isCommutable = 1 in
469 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
470 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
471 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
472 PPC970_DGroup_Cracked;
474 let Defs = [CARRY] in
475 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
476 "addic $rD, $rA, $imm", IIC_IntGeneral,
477 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
478 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
479 "addi $rD, $rA, $imm", IIC_IntSimple,
480 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
481 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
482 "addis $rD, $rA, $imm", IIC_IntSimple,
483 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
485 let Defs = [CARRY] in {
486 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
487 "subfic $rD, $rA, $imm", IIC_IntGeneral,
488 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
489 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
490 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
491 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
492 PPC970_DGroup_Cracked;
494 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
495 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
496 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
497 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
498 "neg", "$rT, $rA", IIC_IntSimple,
499 [(set i64:$rT, (ineg i64:$rA))]>;
500 let Uses = [CARRY] in {
501 let isCommutable = 1 in
502 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
503 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
504 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
505 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
506 "addme", "$rT, $rA", IIC_IntGeneral,
507 [(set i64:$rT, (adde i64:$rA, -1))]>;
508 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
509 "addze", "$rT, $rA", IIC_IntGeneral,
510 [(set i64:$rT, (adde i64:$rA, 0))]>;
511 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
512 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
513 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
514 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
515 "subfme", "$rT, $rA", IIC_IntGeneral,
516 [(set i64:$rT, (sube -1, i64:$rA))]>;
517 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
518 "subfze", "$rT, $rA", IIC_IntGeneral,
519 [(set i64:$rT, (sube 0, i64:$rA))]>;
523 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
524 // previous definition must be marked as CodeGen only to prevent decoding
526 let isAsmParserOnly = 1 in
527 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
528 "add $rT, $rA, $rB", IIC_IntSimple, []>;
530 let isCommutable = 1 in {
531 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
532 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
533 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
534 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
535 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
536 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
539 } // Interpretation64Bit
541 let isCompare = 1, hasSideEffects = 0 in {
542 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
543 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
544 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
545 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
546 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
547 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
548 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
549 "cmpldi $dst, $src1, $src2",
550 IIC_IntCompare>, isPPC64;
553 let hasSideEffects = 0 in {
554 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
555 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
556 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
557 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
558 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
559 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
560 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
561 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
562 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
564 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
565 defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS),
566 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>;
568 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
569 "extsb", "$rA, $rS", IIC_IntSimple,
570 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
571 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
572 "extsh", "$rA, $rS", IIC_IntSimple,
573 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
575 defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
576 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
577 defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
578 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
579 } // Interpretation64Bit
582 let isCodeGenOnly = 1 in {
583 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
584 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
585 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
586 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
587 } // isCodeGenOnly for fast-isel
589 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
590 "extsw", "$rA, $rS", IIC_IntSimple,
591 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
592 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
593 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
594 "extsw", "$rA, $rS", IIC_IntSimple,
595 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
597 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
598 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
599 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
600 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
601 "cntlzd", "$rA, $rS", IIC_IntGeneral,
602 [(set i64:$rA, (ctlz i64:$rS))]>;
603 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
604 "popcntd $rA, $rS", IIC_IntGeneral,
605 [(set i64:$rA, (ctpop i64:$rS))]>;
607 let isCodeGenOnly = 1, isCommutable = 1 in
608 def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
609 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
610 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>;
612 // popcntw also does a population count on the high 32 bits (storing the
613 // results in the high 32-bits of the output). We'll ignore that here (which is
614 // safe because we never separately use the high part of the 64-bit registers).
615 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
616 "popcntw $rA, $rS", IIC_IntGeneral,
617 [(set i32:$rA, (ctpop i32:$rS))]>;
619 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
620 "divd", "$rT, $rA, $rB", IIC_IntDivD,
621 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
622 PPC970_DGroup_First, PPC970_DGroup_Cracked;
623 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
624 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
625 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
626 PPC970_DGroup_First, PPC970_DGroup_Cracked;
627 let isCommutable = 1 in
628 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
629 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
630 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
631 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
632 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
633 "mulli $rD, $rA, $imm", IIC_IntMulLI,
634 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
637 let hasSideEffects = 0 in {
638 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
639 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
640 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
641 []>, isPPC64, RegConstraint<"$rSi = $rA">,
644 // Rotate instructions.
645 defm RLDCL : MDSForm_1r<30, 8,
646 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
647 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
649 defm RLDCR : MDSForm_1r<30, 9,
650 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
651 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
653 defm RLDICL : MDForm_1r<30, 0,
654 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
655 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
658 let isCodeGenOnly = 1 in
659 def RLDICL_32_64 : MDForm_1<30, 0,
661 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
662 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
665 defm RLDICR : MDForm_1r<30, 1,
666 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
667 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
669 defm RLDIC : MDForm_1r<30, 2,
670 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
671 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
674 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
675 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
676 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
677 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
680 defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA),
681 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME),
682 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
685 // RLWIMI can be commuted if the rotate amount is zero.
686 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
687 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
688 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
689 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
690 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
691 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
694 def ISEL8 : AForm_4<31, 15,
695 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
696 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
698 } // Interpretation64Bit
699 } // hasSideEffects = 0
700 } // End FXU Operations.
703 //===----------------------------------------------------------------------===//
704 // Load/Store instructions.
708 // Sign extending loads.
709 let PPC970_Unit = 2 in {
710 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
711 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
712 "lha $rD, $src", IIC_LdStLHA,
713 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
714 PPC970_DGroup_Cracked;
715 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
716 "lwa $rD, $src", IIC_LdStLWA,
718 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
719 PPC970_DGroup_Cracked;
720 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
721 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
722 "lhax $rD, $src", IIC_LdStLHA,
723 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
724 PPC970_DGroup_Cracked;
725 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
726 "lwax $rD, $src", IIC_LdStLHA,
727 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
728 PPC970_DGroup_Cracked;
730 let isCodeGenOnly = 1, mayLoad = 1 in {
731 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
732 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
733 PPC970_DGroup_Cracked;
734 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
735 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
736 PPC970_DGroup_Cracked;
737 } // end fast-isel isCodeGenOnly
740 let mayLoad = 1, hasSideEffects = 0 in {
741 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
742 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
744 "lhau $rD, $addr", IIC_LdStLHAU,
745 []>, RegConstraint<"$addr.reg = $ea_result">,
746 NoEncode<"$ea_result">;
749 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
750 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
752 "lhaux $rD, $addr", IIC_LdStLHAUX,
753 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
754 NoEncode<"$ea_result">;
755 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
757 "lwaux $rD, $addr", IIC_LdStLHAUX,
758 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
759 NoEncode<"$ea_result">, isPPC64;
763 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
764 // Zero extending loads.
765 let PPC970_Unit = 2 in {
766 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
767 "lbz $rD, $src", IIC_LdStLoad,
768 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
769 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
770 "lhz $rD, $src", IIC_LdStLoad,
771 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
772 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
773 "lwz $rD, $src", IIC_LdStLoad,
774 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
776 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
777 "lbzx $rD, $src", IIC_LdStLoad,
778 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
779 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
780 "lhzx $rD, $src", IIC_LdStLoad,
781 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
782 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
783 "lwzx $rD, $src", IIC_LdStLoad,
784 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
788 let mayLoad = 1, hasSideEffects = 0 in {
789 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
790 "lbzu $rD, $addr", IIC_LdStLoadUpd,
791 []>, RegConstraint<"$addr.reg = $ea_result">,
792 NoEncode<"$ea_result">;
793 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
794 "lhzu $rD, $addr", IIC_LdStLoadUpd,
795 []>, RegConstraint<"$addr.reg = $ea_result">,
796 NoEncode<"$ea_result">;
797 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
798 "lwzu $rD, $addr", IIC_LdStLoadUpd,
799 []>, RegConstraint<"$addr.reg = $ea_result">,
800 NoEncode<"$ea_result">;
802 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
804 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
805 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
806 NoEncode<"$ea_result">;
807 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
809 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
810 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
811 NoEncode<"$ea_result">;
812 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
814 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
815 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
816 NoEncode<"$ea_result">;
819 } // Interpretation64Bit
822 // Full 8-byte loads.
823 let PPC970_Unit = 2 in {
824 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
825 "ld $rD, $src", IIC_LdStLD,
826 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
827 // The following four definitions are selected for small code model only.
828 // Otherwise, we need to create two instructions to form a 32-bit offset,
829 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
830 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
833 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
834 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
837 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
838 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
841 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
842 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
845 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
847 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
848 "ldx $rD, $src", IIC_LdStLD,
849 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
850 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
851 "ldbrx $rD, $src", IIC_LdStLoad,
852 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
854 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
855 def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src),
856 "lhbrx $rD, $src", IIC_LdStLoad, []>;
857 def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src),
858 "lwbrx $rD, $src", IIC_LdStLoad, []>;
861 let mayLoad = 1, hasSideEffects = 0 in {
862 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
863 "ldu $rD, $addr", IIC_LdStLDU,
864 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
865 NoEncode<"$ea_result">;
867 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
869 "ldux $rD, $addr", IIC_LdStLDUX,
870 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
871 NoEncode<"$ea_result">, isPPC64;
875 // Support for medium and large code model.
876 let hasSideEffects = 0 in {
877 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
878 "#ADDIStocHA", []>, isPPC64;
880 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
881 "#LDtocL", []>, isPPC64;
882 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
883 "#ADDItocL", []>, isPPC64;
886 // Support for thread-local storage.
887 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
890 (PPCaddisGotTprelHA i64:$reg,
891 tglobaltlsaddr:$disp))]>,
893 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
896 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
898 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
899 (ADD8TLS $in, tglobaltlsaddr:$g)>;
900 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
903 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
905 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
908 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
910 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is
911 // explicitly defined when this op is created, so not mentioned here.
912 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
913 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
914 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
917 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
919 // Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8
920 // are true defines while the rest of the Defs are clobbers.
921 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
922 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
924 def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD),
925 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
928 (PPCaddiTlsgdLAddr i64:$reg,
929 tglobaltlsaddr:$disp,
930 tglobaltlsaddr:$sym))]>,
932 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
935 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
937 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
940 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
942 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is
943 // explicitly defined when this op is created, so not mentioned here.
944 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
945 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
946 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
949 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
951 // Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8
952 // are true defines, while the rest of the Defs are clobbers.
953 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
954 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
956 def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD),
957 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
960 (PPCaddiTlsldLAddr i64:$reg,
961 tglobaltlsaddr:$disp,
962 tglobaltlsaddr:$sym))]>,
964 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
967 (PPCaddisDtprelHA i64:$reg,
968 tglobaltlsaddr:$disp))]>,
970 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
973 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
976 let PPC970_Unit = 2 in {
977 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
978 // Truncating stores.
979 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
980 "stb $rS, $src", IIC_LdStStore,
981 [(truncstorei8 i64:$rS, iaddr:$src)]>;
982 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
983 "sth $rS, $src", IIC_LdStStore,
984 [(truncstorei16 i64:$rS, iaddr:$src)]>;
985 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
986 "stw $rS, $src", IIC_LdStStore,
987 [(truncstorei32 i64:$rS, iaddr:$src)]>;
988 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
989 "stbx $rS, $dst", IIC_LdStStore,
990 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
991 PPC970_DGroup_Cracked;
992 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
993 "sthx $rS, $dst", IIC_LdStStore,
994 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
995 PPC970_DGroup_Cracked;
996 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
997 "stwx $rS, $dst", IIC_LdStStore,
998 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
999 PPC970_DGroup_Cracked;
1000 } // Interpretation64Bit
1002 // Normal 8-byte stores.
1003 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
1004 "std $rS, $dst", IIC_LdStSTD,
1005 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
1006 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
1007 "stdx $rS, $dst", IIC_LdStSTD,
1008 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
1009 PPC970_DGroup_Cracked;
1010 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
1011 "stdbrx $rS, $dst", IIC_LdStStore,
1012 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
1013 PPC970_DGroup_Cracked;
1016 // Stores with Update (pre-inc).
1017 let PPC970_Unit = 2, mayStore = 1 in {
1018 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1019 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1020 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1021 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1022 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1023 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1024 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1025 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
1026 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1027 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1029 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1030 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1031 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1032 PPC970_DGroup_Cracked;
1033 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1034 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1035 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1036 PPC970_DGroup_Cracked;
1037 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1038 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1039 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1040 PPC970_DGroup_Cracked;
1041 } // Interpretation64Bit
1043 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
1044 "stdu $rS, $dst", IIC_LdStSTDU, []>,
1045 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
1048 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1049 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
1050 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1051 PPC970_DGroup_Cracked, isPPC64;
1054 // Patterns to match the pre-inc stores. We can't put the patterns on
1055 // the instruction definitions directly as ISel wants the address base
1056 // and offset to be separate operands, not a single complex operand.
1057 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1058 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1059 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1060 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1061 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1062 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1063 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1064 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
1066 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1067 (STBUX8 $rS, $ptrreg, $ptroff)>;
1068 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1069 (STHUX8 $rS, $ptrreg, $ptroff)>;
1070 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1071 (STWUX8 $rS, $ptrreg, $ptroff)>;
1072 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1073 (STDUX $rS, $ptrreg, $ptroff)>;
1076 //===----------------------------------------------------------------------===//
1077 // Floating point instructions.
1081 let PPC970_Unit = 3, hasSideEffects = 0,
1082 Uses = [RM] in { // FPU Operations.
1083 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
1084 "fcfid", "$frD, $frB", IIC_FPGeneral,
1085 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
1086 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
1087 "fctid", "$frD, $frB", IIC_FPGeneral,
1089 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
1090 "fctidz", "$frD, $frB", IIC_FPGeneral,
1091 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1093 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
1094 "fcfidu", "$frD, $frB", IIC_FPGeneral,
1095 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
1096 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1097 "fcfids", "$frD, $frB", IIC_FPGeneral,
1098 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1099 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1100 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1101 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1102 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1103 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1104 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1105 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1106 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1107 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1111 //===----------------------------------------------------------------------===//
1112 // Instruction Patterns
1115 // Extensions and truncates to/from 32-bit regs.
1116 def : Pat<(i64 (zext i32:$in)),
1117 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1119 def : Pat<(i64 (anyext i32:$in)),
1120 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1121 def : Pat<(i32 (trunc i64:$in)),
1122 (EXTRACT_SUBREG $in, sub_32)>;
1124 // Implement the 'not' operation with the NOR instruction.
1125 // (we could use the default xori pattern, but nor has lower latency on some
1126 // cores (such as the A2)).
1127 def i64not : OutPatFrag<(ops node:$in),
1129 def : Pat<(not i64:$in),
1132 // Extending loads with i64 targets.
1133 def : Pat<(zextloadi1 iaddr:$src),
1135 def : Pat<(zextloadi1 xaddr:$src),
1136 (LBZX8 xaddr:$src)>;
1137 def : Pat<(extloadi1 iaddr:$src),
1139 def : Pat<(extloadi1 xaddr:$src),
1140 (LBZX8 xaddr:$src)>;
1141 def : Pat<(extloadi8 iaddr:$src),
1143 def : Pat<(extloadi8 xaddr:$src),
1144 (LBZX8 xaddr:$src)>;
1145 def : Pat<(extloadi16 iaddr:$src),
1147 def : Pat<(extloadi16 xaddr:$src),
1148 (LHZX8 xaddr:$src)>;
1149 def : Pat<(extloadi32 iaddr:$src),
1151 def : Pat<(extloadi32 xaddr:$src),
1152 (LWZX8 xaddr:$src)>;
1154 // Standard shifts. These are represented separately from the real shifts above
1155 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1157 def : Pat<(sra i64:$rS, i32:$rB),
1159 def : Pat<(srl i64:$rS, i32:$rB),
1161 def : Pat<(shl i64:$rS, i32:$rB),
1165 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1166 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1167 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1168 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1171 def : Pat<(rotl i64:$in, i32:$sh),
1172 (RLDCL $in, $sh, 0)>;
1173 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1174 (RLDICL $in, imm:$imm, 0)>;
1176 // Hi and Lo for Darwin Global Addresses.
1177 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1178 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1179 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1180 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1181 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1182 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1183 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1184 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1185 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1186 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1187 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1188 (ADDI8 $in, tglobaltlsaddr:$g)>;
1189 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1190 (ADDIS8 $in, tglobaladdr:$g)>;
1191 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1192 (ADDIS8 $in, tconstpool:$g)>;
1193 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1194 (ADDIS8 $in, tjumptable:$g)>;
1195 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1196 (ADDIS8 $in, tblockaddress:$g)>;
1198 // Patterns to match r+r indexed loads and stores for
1199 // addresses without at least 4-byte alignment.
1200 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1201 (LWAX xoaddr:$src)>;
1202 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1204 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1205 (STDX $rS, xoaddr:$dst)>;
1207 // 64-bits atomic loads and stores
1208 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>;
1209 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>;
1211 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>;
1212 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>;