1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
32 def tocentry : Operand<iPTR> {
33 let MIOperandInfo = (ops i64imm:$imm);
35 def tlsreg : Operand<i64> {
36 let EncoderMethod = "getTLSRegEncoding";
38 def tlsgd : Operand<i64> {}
40 //===----------------------------------------------------------------------===//
41 // 64-bit transformation functions.
44 def SHL64 : SDNodeXForm<imm, [{
45 // Transformation function: 63 - imm
46 return getI32Imm(63 - N->getZExtValue());
49 def SRL64 : SDNodeXForm<imm, [{
50 // Transformation function: 64 - imm
51 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
54 def HI32_48 : SDNodeXForm<imm, [{
55 // Transformation function: shift the immediate value down into the low bits.
56 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
59 def HI48_64 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
65 //===----------------------------------------------------------------------===//
69 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
70 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in
71 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
72 Requires<[In64BitMode]>;
76 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
79 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
80 let Defs = [CTR8], Uses = [CTR8] in {
81 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
83 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
88 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
89 // Convenient aliases for call instructions
91 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
92 "bl $func", BrB, []>; // See Pat patterns below.
94 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func),
95 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
97 let Uses = [RM], isCodeGenOnly = 1 in {
98 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
99 (outs), (ins calltarget:$func),
100 "bl $func\n\tnop", BrB, []>;
102 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
103 (outs), (ins calltarget:$func, tlsgd:$sym),
104 "bl $func($sym)\n\tnop", BrB, []>;
106 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
107 (outs), (ins calltarget:$func, tlsgd:$sym),
108 "bl $func($sym)\n\tnop", BrB, []>;
110 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
111 (outs), (ins aaddr:$func),
112 "bla $func\n\tnop", BrB,
113 [(PPCcall_nop (i64 imm:$func))]>;
115 let Uses = [CTR8, RM] in {
116 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
117 "bctrl", BrB, [(PPCbctrl)]>,
118 Requires<[In64BitMode]>;
124 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
125 (BL8 tglobaladdr:$dst)>;
126 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
127 (BL8_NOP tglobaladdr:$dst)>;
129 def : Pat<(PPCcall (i64 texternalsym:$dst)),
130 (BL8 texternalsym:$dst)>;
131 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
132 (BL8_NOP texternalsym:$dst)>;
135 let usesCustomInserter = 1 in {
136 let Defs = [CR0] in {
137 def ATOMIC_LOAD_ADD_I64 : Pseudo<
138 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
139 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
140 def ATOMIC_LOAD_SUB_I64 : Pseudo<
141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
142 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
143 def ATOMIC_LOAD_OR_I64 : Pseudo<
144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
145 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
146 def ATOMIC_LOAD_XOR_I64 : Pseudo<
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
148 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
149 def ATOMIC_LOAD_AND_I64 : Pseudo<
150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
151 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
152 def ATOMIC_LOAD_NAND_I64 : Pseudo<
153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
154 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
156 def ATOMIC_CMP_SWAP_I64 : Pseudo<
157 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
158 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
160 def ATOMIC_SWAP_I64 : Pseudo<
161 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
162 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
166 // Instructions to support atomic operations
167 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
168 "ldarx $rD, $ptr", LdStLDARX,
169 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
172 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
173 "stdcx. $rS, $dst", LdStSTDCX,
174 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
178 def TCRETURNdi8 :Pseudo< (outs),
179 (ins calltarget:$dst, i32imm:$offset),
180 "#TC_RETURNd8 $dst $offset",
183 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
184 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
185 "#TC_RETURNa8 $func $offset",
186 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
188 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
189 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
190 "#TC_RETURNr8 $dst $offset",
194 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
195 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
196 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
197 Requires<[In64BitMode]>;
200 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
201 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
202 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
207 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
208 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
209 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
213 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
214 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
216 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
217 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
219 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
220 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
223 // 64-but CR instructions
224 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
225 "mtcrf $FXM, $rS", BrMCRX>,
226 PPC970_MicroCode, PPC970_Unit_CRU;
228 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
229 "#MFCR8pseud", SprMFCR>,
230 PPC970_MicroCode, PPC970_Unit_CRU;
232 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
233 "mfcr $rT", SprMFCR>,
234 PPC970_MicroCode, PPC970_Unit_CRU;
236 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
237 usesCustomInserter = 1 in {
238 def EH_SjLj_SetJmp64 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
240 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
241 Requires<[In64BitMode]>;
242 let isTerminator = 1 in
243 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
244 "#EH_SJLJ_LONGJMP64",
245 [(PPCeh_sjlj_longjmp addr:$buf)]>,
246 Requires<[In64BitMode]>;
249 //===----------------------------------------------------------------------===//
250 // 64-bit SPR manipulation instrs.
252 let Uses = [CTR8] in {
253 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
254 "mfctr $rT", SprMFSPR>,
255 PPC970_DGroup_First, PPC970_Unit_FXU;
257 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
258 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
259 "mtctr $rS", SprMTSPR>,
260 PPC970_DGroup_First, PPC970_Unit_FXU;
263 let Pattern = [(set i64:$rT, readcyclecounter)] in
264 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
265 "mfspr $rT, 268", SprMFTB>,
266 PPC970_DGroup_First, PPC970_Unit_FXU;
267 // Note that encoding mftb using mfspr is now the preferred form,
268 // and has been since at least ISA v2.03. The mftb instruction has
269 // now been phased out. Using mfspr, however, is known not to work on
272 let Defs = [X1], Uses = [X1] in
273 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
275 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
277 let Defs = [LR8] in {
278 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
279 "mtlr $rS", SprMTSPR>,
280 PPC970_DGroup_First, PPC970_Unit_FXU;
282 let Uses = [LR8] in {
283 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
284 "mflr $rT", SprMFSPR>,
285 PPC970_DGroup_First, PPC970_Unit_FXU;
288 //===----------------------------------------------------------------------===//
289 // Fixed point instructions.
292 let PPC970_Unit = 1 in { // FXU Operations.
294 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
295 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
296 "li $rD, $imm", IntSimple,
297 [(set i64:$rD, immSExt16:$imm)]>;
298 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
299 "lis $rD, $imm", IntSimple,
300 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
304 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
305 "nand $rA, $rS, $rB", IntSimple,
306 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
307 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
308 "and $rA, $rS, $rB", IntSimple,
309 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
310 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
311 "andc $rA, $rS, $rB", IntSimple,
312 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
313 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
314 "or $rA, $rS, $rB", IntSimple,
315 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
316 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
317 "nor $rA, $rS, $rB", IntSimple,
318 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
319 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
320 "orc $rA, $rS, $rB", IntSimple,
321 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
322 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
323 "eqv $rA, $rS, $rB", IntSimple,
324 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
325 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
326 "xor $rA, $rS, $rB", IntSimple,
327 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
329 // Logical ops with immediate.
330 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
331 "andi. $dst, $src1, $src2", IntGeneral,
332 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
334 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
335 "andis. $dst, $src1, $src2", IntGeneral,
336 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
338 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
339 "ori $dst, $src1, $src2", IntSimple,
340 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
341 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
342 "oris $dst, $src1, $src2", IntSimple,
343 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
344 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
345 "xori $dst, $src1, $src2", IntSimple,
346 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
347 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
348 "xoris $dst, $src1, $src2", IntSimple,
349 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
351 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
352 "add $rT, $rA, $rB", IntSimple,
353 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
354 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
355 // initial-exec thread-local storage model.
356 def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB),
357 "add $rT, $rA, $rB@tls", IntSimple,
358 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
360 let Defs = [CARRY] in {
361 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
362 "addc $rT, $rA, $rB", IntGeneral,
363 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
364 PPC970_DGroup_Cracked;
365 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
366 "addic $rD, $rA, $imm", IntGeneral,
367 [(set i64:$rD, (addc i64:$rA, immSExt16:$imm))]>;
369 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm),
370 "addi $rD, $rA, $imm", IntSimple,
371 [(set i64:$rD, (add i64:$rA, immSExt16:$imm))]>;
372 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm),
373 "addis $rD, $rA, $imm", IntSimple,
374 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
376 let Defs = [CARRY] in {
377 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
378 "subfic $rD, $rA, $imm", IntGeneral,
379 [(set i64:$rD, (subc immSExt16:$imm, i64:$rA))]>;
380 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
381 "subfc $rT, $rA, $rB", IntGeneral,
382 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
383 PPC970_DGroup_Cracked;
385 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
386 "subf $rT, $rA, $rB", IntGeneral,
387 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
388 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
389 "neg $rT, $rA", IntSimple,
390 [(set i64:$rT, (ineg i64:$rA))]>;
391 let Uses = [CARRY], Defs = [CARRY] in {
392 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
393 "adde $rT, $rA, $rB", IntGeneral,
394 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
395 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
396 "addme $rT, $rA", IntGeneral,
397 [(set i64:$rT, (adde i64:$rA, -1))]>;
398 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
399 "addze $rT, $rA", IntGeneral,
400 [(set i64:$rT, (adde i64:$rA, 0))]>;
401 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
402 "subfe $rT, $rA, $rB", IntGeneral,
403 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
404 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
405 "subfme $rT, $rA", IntGeneral,
406 [(set i64:$rT, (sube -1, i64:$rA))]>;
407 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
408 "subfze $rT, $rA", IntGeneral,
409 [(set i64:$rT, (sube 0, i64:$rA))]>;
413 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
414 "mulhd $rT, $rA, $rB", IntMulHW,
415 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
416 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
417 "mulhdu $rT, $rA, $rB", IntMulHWU,
418 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
420 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
421 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
422 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
423 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
424 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
425 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
426 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
427 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
429 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
430 "sld $rA, $rS, $rB", IntRotateD,
431 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
432 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
433 "srd $rA, $rS, $rB", IntRotateD,
434 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
435 let Defs = [CARRY] in {
436 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
437 "srad $rA, $rS, $rB", IntRotateD,
438 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
441 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
442 "extsb $rA, $rS", IntSimple,
443 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
444 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
445 "extsh $rA, $rS", IntSimple,
446 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
448 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
449 "extsw $rA, $rS", IntSimple,
450 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
451 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
452 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
453 "extsw $rA, $rS", IntSimple,
454 [(set i32:$rA, (PPCextsw_32 i32:$rS))]>, isPPC64;
455 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
456 "extsw $rA, $rS", IntSimple,
457 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
459 let Defs = [CARRY] in {
460 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
461 "sradi $rA, $rS, $SH", IntRotateDI,
462 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
464 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
465 "cntlzd $rA, $rS", IntGeneral,
466 [(set i64:$rA, (ctlz i64:$rS))]>;
468 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
469 "divd $rT, $rA, $rB", IntDivD,
470 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
471 PPC970_DGroup_First, PPC970_DGroup_Cracked;
472 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
473 "divdu $rT, $rA, $rB", IntDivD,
474 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
475 PPC970_DGroup_First, PPC970_DGroup_Cracked;
476 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
477 "mulld $rT, $rA, $rB", IntMulHD,
478 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
481 let isCommutable = 1 in {
482 def RLDIMI : MDForm_1<30, 3,
483 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
484 "rldimi $rA, $rS, $SH, $MB", IntRotateDI,
485 []>, isPPC64, RegConstraint<"$rSi = $rA">,
489 // Rotate instructions.
490 def RLDCL : MDForm_1<30, 0,
491 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
492 "rldcl $rA, $rS, $rB, $MBE", IntRotateD,
494 def RLDICL : MDForm_1<30, 0,
495 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
496 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
498 def RLDICR : MDForm_1<30, 1,
499 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
500 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI,
503 def RLWINM8 : MForm_2<21,
504 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
505 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
508 def ISEL8 : AForm_4<31, 15,
509 (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, CRBITRC:$cond),
510 "isel $rT, $rA, $rB, $cond", IntGeneral,
512 } // End FXU Operations.
515 //===----------------------------------------------------------------------===//
516 // Load/Store instructions.
520 // Sign extending loads.
521 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
522 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
523 "lha $rD, $src", LdStLHA,
524 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
525 PPC970_DGroup_Cracked;
526 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
527 "lwa $rD, $src", LdStLWA,
529 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
530 PPC970_DGroup_Cracked;
531 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
532 "lhax $rD, $src", LdStLHA,
533 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
534 PPC970_DGroup_Cracked;
535 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
536 "lwax $rD, $src", LdStLHA,
537 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
538 PPC970_DGroup_Cracked;
542 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
544 "lhau $rD, $addr", LdStLHAU,
545 []>, RegConstraint<"$addr.reg = $ea_result">,
546 NoEncode<"$ea_result">;
549 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
551 "lhaux $rD, $addr", LdStLHAU,
552 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
553 NoEncode<"$ea_result">;
554 def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
556 "lwaux $rD, $addr", LdStLHAU,
557 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
558 NoEncode<"$ea_result">, isPPC64;
562 // Zero extending loads.
563 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
564 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
565 "lbz $rD, $src", LdStLoad,
566 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
567 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
568 "lhz $rD, $src", LdStLoad,
569 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
570 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
571 "lwz $rD, $src", LdStLoad,
572 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
574 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
575 "lbzx $rD, $src", LdStLoad,
576 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
577 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
578 "lhzx $rD, $src", LdStLoad,
579 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
580 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
581 "lwzx $rD, $src", LdStLoad,
582 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
587 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
588 "lbzu $rD, $addr", LdStLoadUpd,
589 []>, RegConstraint<"$addr.reg = $ea_result">,
590 NoEncode<"$ea_result">;
591 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
592 "lhzu $rD, $addr", LdStLoadUpd,
593 []>, RegConstraint<"$addr.reg = $ea_result">,
594 NoEncode<"$ea_result">;
595 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
596 "lwzu $rD, $addr", LdStLoadUpd,
597 []>, RegConstraint<"$addr.reg = $ea_result">,
598 NoEncode<"$ea_result">;
600 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
602 "lbzux $rD, $addr", LdStLoadUpd,
603 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
604 NoEncode<"$ea_result">;
605 def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
607 "lhzux $rD, $addr", LdStLoadUpd,
608 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
609 NoEncode<"$ea_result">;
610 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
612 "lwzux $rD, $addr", LdStLoadUpd,
613 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
614 NoEncode<"$ea_result">;
619 // Full 8-byte loads.
620 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
621 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
622 "ld $rD, $src", LdStLD,
623 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
624 // The following three definitions are selected for small code model only.
625 // Otherwise, we need to create two instructions to form a 32-bit offset,
626 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
627 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
630 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
631 def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
634 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
635 def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
638 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
640 let hasSideEffects = 1 in {
641 let RST = 2, DS = 2 in
642 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
643 "ld 2, 8($reg)", LdStLD,
644 [(PPCload_toc i64:$reg)]>, isPPC64;
646 let RST = 2, DS = 10, RA = 1 in
647 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
648 "ld 2, 40(1)", LdStLD,
649 [(PPCtoc_restore)]>, isPPC64;
651 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
652 "ldx $rD, $src", LdStLD,
653 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
656 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
657 "ldu $rD, $addr", LdStLDU,
658 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
659 NoEncode<"$ea_result">;
661 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
663 "ldux $rD, $addr", LdStLDU,
664 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
665 NoEncode<"$ea_result">, isPPC64;
668 def : Pat<(PPCload ixaddr:$src),
670 def : Pat<(PPCload xaddr:$src),
673 // Support for medium and large code model.
674 def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
677 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
679 def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
682 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
683 def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
686 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
688 // Support for thread-local storage.
689 def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
692 (PPCaddisGotTprelHA i64:$reg,
693 tglobaltlsaddr:$disp))]>,
695 def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg),
698 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
700 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
701 (ADD8TLS $in, tglobaltlsaddr:$g)>;
702 def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
705 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
707 def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
710 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
712 def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
715 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
717 def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
720 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
722 def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
725 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
727 def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
730 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
732 def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
735 (PPCaddisDtprelHA i64:$reg,
736 tglobaltlsaddr:$disp))]>,
738 def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
741 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
744 let PPC970_Unit = 2 in {
745 // Truncating stores.
746 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
747 "stb $rS, $src", LdStStore,
748 [(truncstorei8 i64:$rS, iaddr:$src)]>;
749 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
750 "sth $rS, $src", LdStStore,
751 [(truncstorei16 i64:$rS, iaddr:$src)]>;
752 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
753 "stw $rS, $src", LdStStore,
754 [(truncstorei32 i64:$rS, iaddr:$src)]>;
755 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
756 "stbx $rS, $dst", LdStStore,
757 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
758 PPC970_DGroup_Cracked;
759 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
760 "sthx $rS, $dst", LdStStore,
761 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
762 PPC970_DGroup_Cracked;
763 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
764 "stwx $rS, $dst", LdStStore,
765 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
766 PPC970_DGroup_Cracked;
767 // Normal 8-byte stores.
768 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
769 "std $rS, $dst", LdStSTD,
770 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
771 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
772 "stdx $rS, $dst", LdStSTD,
773 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
774 PPC970_DGroup_Cracked;
775 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
776 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
777 "std $rT, $dst", LdStSTD,
778 [(PPCstd_32 i32:$rT, ixaddr:$dst)]>, isPPC64;
779 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
780 "stdx $rT, $dst", LdStSTD,
781 [(PPCstd_32 i32:$rT, xaddr:$dst)]>, isPPC64,
782 PPC970_DGroup_Cracked;
785 // Stores with Update (pre-inc).
786 let PPC970_Unit = 2, mayStore = 1 in {
787 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
788 "stbu $rS, $dst", LdStStoreUpd, []>,
789 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
790 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
791 "sthu $rS, $dst", LdStStoreUpd, []>,
792 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
793 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
794 "stwu $rS, $dst", LdStStoreUpd, []>,
795 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
796 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst),
797 "stdu $rS, $dst", LdStSTDU, []>,
798 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
801 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
802 "stbux $rS, $dst", LdStStoreUpd, []>,
803 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
804 PPC970_DGroup_Cracked;
805 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
806 "sthux $rS, $dst", LdStStoreUpd, []>,
807 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
808 PPC970_DGroup_Cracked;
809 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
810 "stwux $rS, $dst", LdStStoreUpd, []>,
811 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
812 PPC970_DGroup_Cracked;
813 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
814 "stdux $rS, $dst", LdStSTDU, []>,
815 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
816 PPC970_DGroup_Cracked, isPPC64;
819 // Patterns to match the pre-inc stores. We can't put the patterns on
820 // the instruction definitions directly as ISel wants the address base
821 // and offset to be separate operands, not a single complex operand.
822 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
823 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
824 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
825 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
826 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
827 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
828 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
829 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
831 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
832 (STBUX8 $rS, $ptrreg, $ptroff)>;
833 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
834 (STHUX8 $rS, $ptrreg, $ptroff)>;
835 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
836 (STWUX8 $rS, $ptrreg, $ptroff)>;
837 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
838 (STDUX $rS, $ptrreg, $ptroff)>;
841 //===----------------------------------------------------------------------===//
842 // Floating point instructions.
846 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
847 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
848 "fcfid $frD, $frB", FPGeneral,
849 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
850 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
851 "fctidz $frD, $frB", FPGeneral,
852 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
856 //===----------------------------------------------------------------------===//
857 // Instruction Patterns
860 // Extensions and truncates to/from 32-bit regs.
861 def : Pat<(i64 (zext i32:$in)),
862 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
864 def : Pat<(i64 (anyext i32:$in)),
865 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
866 def : Pat<(i32 (trunc i64:$in)),
867 (EXTRACT_SUBREG $in, sub_32)>;
869 // Extending loads with i64 targets.
870 def : Pat<(zextloadi1 iaddr:$src),
872 def : Pat<(zextloadi1 xaddr:$src),
874 def : Pat<(extloadi1 iaddr:$src),
876 def : Pat<(extloadi1 xaddr:$src),
878 def : Pat<(extloadi8 iaddr:$src),
880 def : Pat<(extloadi8 xaddr:$src),
882 def : Pat<(extloadi16 iaddr:$src),
884 def : Pat<(extloadi16 xaddr:$src),
886 def : Pat<(extloadi32 iaddr:$src),
888 def : Pat<(extloadi32 xaddr:$src),
891 // Standard shifts. These are represented separately from the real shifts above
892 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
894 def : Pat<(sra i64:$rS, i32:$rB),
896 def : Pat<(srl i64:$rS, i32:$rB),
898 def : Pat<(shl i64:$rS, i32:$rB),
902 def : Pat<(shl i64:$in, (i32 imm:$imm)),
903 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
904 def : Pat<(srl i64:$in, (i32 imm:$imm)),
905 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
908 def : Pat<(rotl i64:$in, i32:$sh),
909 (RLDCL $in, $sh, 0)>;
910 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
911 (RLDICL $in, imm:$imm, 0)>;
913 // Hi and Lo for Darwin Global Addresses.
914 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
915 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
916 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
917 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
918 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
919 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
920 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
921 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
922 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
923 (ADDIS8 $in, tglobaltlsaddr:$g)>;
924 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
925 (ADDI8 $in, tglobaltlsaddr:$g)>;
926 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
927 (ADDIS8 $in, tglobaladdr:$g)>;
928 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
929 (ADDIS8 $in, tconstpool:$g)>;
930 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
931 (ADDIS8 $in, tjumptable:$g)>;
932 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
933 (ADDIS8 $in, tblockaddress:$g)>;
935 // Patterns to match r+r indexed loads and stores for
936 // addresses without at least 4-byte alignment.
937 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
939 def : Pat<(i64 (unaligned4load xoaddr:$src)),
941 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
942 (STDX $rS, xoaddr:$dst)>;