1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
20 def vnot_ppc : PatFrag<(ops node:$in),
21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
23 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
24 (vector_shuffle node:$lhs, node:$rhs), [{
25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
27 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
28 (vector_shuffle node:$lhs, node:$rhs), [{
29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
31 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
32 (vector_shuffle node:$lhs, node:$rhs), [{
33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
35 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
36 (vector_shuffle node:$lhs, node:$rhs), [{
37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
40 // These fragments are provided for little-endian, where the inputs must be
41 // swapped for correct semantics.
42 def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
43 (vector_shuffle node:$lhs, node:$rhs), [{
44 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
46 def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
47 (vector_shuffle node:$lhs, node:$rhs), [{
48 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
51 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
52 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
53 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
55 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
56 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
57 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
59 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
60 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
61 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
63 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
64 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
65 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
67 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
69 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
71 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
72 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
73 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
77 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
78 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
79 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
81 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
82 (vector_shuffle node:$lhs, node:$rhs), [{
83 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
85 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
86 (vector_shuffle node:$lhs, node:$rhs), [{
87 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
89 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
90 (vector_shuffle node:$lhs, node:$rhs), [{
91 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
93 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
94 (vector_shuffle node:$lhs, node:$rhs), [{
95 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
97 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
98 (vector_shuffle node:$lhs, node:$rhs), [{
99 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
103 // These fragments are provided for little-endian, where the inputs must be
104 // swapped for correct semantics.
105 def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
106 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
107 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
109 def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
110 (vector_shuffle node:$lhs, node:$rhs), [{
111 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
113 def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
114 (vector_shuffle node:$lhs, node:$rhs), [{
115 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
117 def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
118 (vector_shuffle node:$lhs, node:$rhs), [{
119 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
121 def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
122 (vector_shuffle node:$lhs, node:$rhs), [{
123 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
125 def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
126 (vector_shuffle node:$lhs, node:$rhs), [{
127 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
131 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
132 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG));
134 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
135 (vector_shuffle node:$lhs, node:$rhs), [{
136 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1;
140 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
141 /// vector_shuffle(X,undef,mask) by the dag combiner.
142 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
143 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG));
145 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
146 (vector_shuffle node:$lhs, node:$rhs), [{
147 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1;
148 }], VSLDOI_unary_get_imm>;
151 /// VSLDOI_swapped* - These fragments are provided for little-endian, where
152 /// the inputs must be swapped for correct semantics.
153 def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{
154 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG));
156 def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
157 (vector_shuffle node:$lhs, node:$rhs), [{
158 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1;
162 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
163 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
164 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG));
166 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
167 (vector_shuffle node:$lhs, node:$rhs), [{
168 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
170 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
171 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG));
173 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
174 (vector_shuffle node:$lhs, node:$rhs), [{
175 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
177 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
178 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG));
180 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
181 (vector_shuffle node:$lhs, node:$rhs), [{
182 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
186 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
187 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
188 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
190 def vecspltisb : PatLeaf<(build_vector), [{
191 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
192 }], VSPLTISB_get_imm>;
194 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
195 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
196 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
198 def vecspltish : PatLeaf<(build_vector), [{
199 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
200 }], VSPLTISH_get_imm>;
202 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
203 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
204 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
206 def vecspltisw : PatLeaf<(build_vector), [{
207 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
208 }], VSPLTISW_get_imm>;
210 //===----------------------------------------------------------------------===//
211 // Helpers for defining instructions that directly correspond to intrinsics.
213 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
214 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
215 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
216 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
217 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
219 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
220 // inputs doesn't match the type of the output.
221 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
223 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
224 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
225 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
227 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
228 // input types and an output type.
229 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
230 ValueType In1Ty, ValueType In2Ty>
231 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
232 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
234 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
236 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
237 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
238 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
239 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
240 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
242 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
243 // inputs doesn't match the type of the output.
244 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
246 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
247 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
248 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
250 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
251 // input types and an output type.
252 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
253 ValueType In1Ty, ValueType In2Ty>
254 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
255 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
256 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
258 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
259 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
260 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
261 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
262 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
264 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
265 // inputs doesn't match the type of the output.
266 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
268 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
269 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
270 [(set OutTy:$vD, (IntID InTy:$vB))]>;
272 class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
273 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA),
274 !strconcat(opc, " $vD, $vA"), IIC_VecFP,
275 [(set Ty:$vD, (IntID Ty:$vA))]>;
277 class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
278 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX),
279 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP,
280 [(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>;
282 //===----------------------------------------------------------------------===//
283 // Instruction Definitions.
285 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
286 let Predicates = [HasAltivec] in {
288 def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
289 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
290 Deprecated<DeprecatedDST> {
295 def DSSALL : DSS_Form<1, 822, (outs), (ins),
296 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
297 Deprecated<DeprecatedDST> {
303 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
304 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
305 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
306 Deprecated<DeprecatedDST>;
308 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
309 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
310 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
311 Deprecated<DeprecatedDST>;
313 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
314 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
315 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
316 Deprecated<DeprecatedDST>;
318 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
319 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
320 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
321 Deprecated<DeprecatedDST>;
323 let isCodeGenOnly = 1 in {
324 // The very same instructions as above, but formally matching 64bit registers.
325 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
326 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
327 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
328 Deprecated<DeprecatedDST>;
330 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
331 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
332 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
333 Deprecated<DeprecatedDST>;
335 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
336 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
337 [(int_ppc_altivec_dstst i64:$rA, i32:$rB,
339 Deprecated<DeprecatedDST>;
341 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
342 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
343 [(int_ppc_altivec_dststt i64:$rA, i32:$rB,
345 Deprecated<DeprecatedDST>;
348 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
349 "mfvscr $vD", IIC_LdStStore,
350 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
351 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
352 "mtvscr $vB", IIC_LdStLoad,
353 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
355 let PPC970_Unit = 2 in { // Loads.
356 def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
357 "lvebx $vD, $src", IIC_LdStLoad,
358 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
359 def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src),
360 "lvehx $vD, $src", IIC_LdStLoad,
361 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
362 def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src),
363 "lvewx $vD, $src", IIC_LdStLoad,
364 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
365 def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
366 "lvx $vD, $src", IIC_LdStLoad,
367 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
368 def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
369 "lvxl $vD, $src", IIC_LdStLoad,
370 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
373 def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src),
374 "lvsl $vD, $src", IIC_LdStLoad,
375 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
377 def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
378 "lvsr $vD, $src", IIC_LdStLoad,
379 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
382 let PPC970_Unit = 2 in { // Stores.
383 def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
384 "stvebx $rS, $dst", IIC_LdStStore,
385 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
386 def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
387 "stvehx $rS, $dst", IIC_LdStStore,
388 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
389 def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
390 "stvewx $rS, $dst", IIC_LdStStore,
391 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
392 def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
393 "stvx $rS, $dst", IIC_LdStStore,
394 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
395 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
396 "stvxl $rS, $dst", IIC_LdStStore,
397 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
400 let PPC970_Unit = 5 in { // VALU Operations.
401 // VA-Form instructions. 3-input AltiVec ops.
402 let isCommutable = 1 in {
403 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
404 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
406 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
408 // FIXME: The fma+fneg pattern won't match because fneg is not legal.
409 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
410 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
411 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
412 (fneg v4f32:$vB))))]>;
414 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
415 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
417 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
420 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
421 v4i32, v4i32, v16i8>;
422 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
425 def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
426 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
428 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
430 // VX-Form instructions. AltiVec arithmetic ops.
431 let isCommutable = 1 in {
432 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
433 "vaddfp $vD, $vA, $vB", IIC_VecFP,
434 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
436 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
437 "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
438 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
439 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
440 "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
441 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
442 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
443 "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
444 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
446 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
447 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
448 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
449 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
450 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
451 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
452 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
455 let isCommutable = 1 in
456 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
457 "vand $vD, $vA, $vB", IIC_VecFP,
458 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
459 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
460 "vandc $vD, $vA, $vB", IIC_VecFP,
461 [(set v4i32:$vD, (and v4i32:$vA,
462 (vnot_ppc v4i32:$vB)))]>;
464 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
465 "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
467 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
468 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
469 "vcfux $vD, $vB, $UIMM", IIC_VecFP,
471 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
472 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
473 "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
475 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
476 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
477 "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
479 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
481 // Defines with the UIM field set to 0 for floating-point
482 // to integer (fp_to_sint/fp_to_uint) conversions and integer
483 // to floating-point (sint_to_fp/uint_to_fp) conversions.
484 let isCodeGenOnly = 1, VA = 0 in {
485 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
486 "vcfsx $vD, $vB, 0", IIC_VecFP,
488 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
489 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
490 "vctuxs $vD, $vB, 0", IIC_VecFP,
492 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
493 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
494 "vcfux $vD, $vB, 0", IIC_VecFP,
496 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
497 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
498 "vctsxs $vD, $vB, 0", IIC_VecFP,
500 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
502 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
503 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;
505 let isCommutable = 1 in {
506 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
507 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
508 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
509 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
510 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
511 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
513 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
514 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
515 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
516 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
517 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
518 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
519 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
520 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
521 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
522 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
523 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
524 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
525 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
526 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
529 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
530 "vmrghb $vD, $vA, $vB", IIC_VecFP,
531 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
532 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
533 "vmrghh $vD, $vA, $vB", IIC_VecFP,
534 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
535 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
536 "vmrghw $vD, $vA, $vB", IIC_VecFP,
537 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
538 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
539 "vmrglb $vD, $vA, $vB", IIC_VecFP,
540 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
541 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
542 "vmrglh $vD, $vA, $vB", IIC_VecFP,
543 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
544 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
545 "vmrglw $vD, $vA, $vB", IIC_VecFP,
546 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
548 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
549 v4i32, v16i8, v4i32>;
550 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
551 v4i32, v8i16, v4i32>;
552 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
553 v4i32, v8i16, v4i32>;
554 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
555 v4i32, v16i8, v4i32>;
556 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
557 v4i32, v8i16, v4i32>;
558 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
559 v4i32, v8i16, v4i32>;
561 let isCommutable = 1 in {
562 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
564 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
566 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
568 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
570 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
572 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
574 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub,
576 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
580 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>;
581 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;
582 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;
583 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;
584 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;
585 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
587 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
589 def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
590 "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
591 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
592 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
593 "vsububm $vD, $vA, $vB", IIC_VecGeneral,
594 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
595 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
596 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
597 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
598 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
599 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
600 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
602 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
603 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
604 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
605 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
606 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
607 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
609 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
610 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
612 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
613 v4i32, v16i8, v4i32>;
614 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
615 v4i32, v8i16, v4i32>;
616 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
617 v4i32, v16i8, v4i32>;
619 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
620 "vnor $vD, $vA, $vB", IIC_VecFP,
621 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
623 let isCommutable = 1 in {
624 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
625 "vor $vD, $vA, $vB", IIC_VecFP,
626 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
627 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
628 "vxor $vD, $vA, $vB", IIC_VecFP,
629 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
632 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
633 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
634 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
636 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;
637 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
639 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
640 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
641 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
643 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
644 "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
646 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
647 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
648 "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
650 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
651 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
652 "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
654 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
656 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
657 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
659 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
660 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
661 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
662 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
663 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
664 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
667 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
668 "vspltisb $vD, $SIMM", IIC_VecPerm,
669 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
670 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
671 "vspltish $vD, $SIMM", IIC_VecPerm,
672 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
673 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
674 "vspltisw $vD, $SIMM", IIC_VecPerm,
675 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
678 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
680 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
682 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
684 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
686 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
688 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
689 "vpkuhum $vD, $vA, $vB", IIC_VecFP,
691 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
692 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
694 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
695 "vpkuwum $vD, $vA, $vB", IIC_VecFP,
697 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
698 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
702 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
704 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
706 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
708 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
710 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
712 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
716 // Altivec Comparisons.
718 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
719 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
721 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
722 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
723 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
725 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
730 // f32 element comparisons.0
731 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
732 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
733 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
734 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
735 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
736 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
737 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
738 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
740 // i8 element comparisons.
741 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
742 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
743 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
744 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
745 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
746 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
748 // i16 element comparisons.
749 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
750 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
751 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
752 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
753 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
754 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
756 // i32 element comparisons.
757 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
758 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
759 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
760 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
761 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
762 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
764 let isCodeGenOnly = 1 in {
765 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
766 "vxor $vD, $vD, $vD", IIC_VecFP,
767 [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
768 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
769 "vxor $vD, $vD, $vD", IIC_VecFP,
770 [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
771 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
772 "vxor $vD, $vD, $vD", IIC_VecFP,
773 [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
776 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
777 "vspltisw $vD, -1", IIC_VecFP,
778 [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
779 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
780 "vspltisw $vD, -1", IIC_VecFP,
781 [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
782 def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
783 "vspltisw $vD, -1", IIC_VecFP,
784 [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
787 } // VALU Operations.
789 //===----------------------------------------------------------------------===//
790 // Additional Altivec Patterns
794 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
797 def : Pat<(store v4i32:$rS, xoaddr:$dst),
798 (STVX $rS, xoaddr:$dst)>;
801 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
802 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
803 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
804 def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>;
806 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
807 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
808 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
809 def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>;
811 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
812 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
813 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
814 def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>;
816 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
817 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
818 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
819 def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>;
821 def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>;
822 def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>;
823 def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>;
824 def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>;
828 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
829 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
830 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;
831 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
833 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
836 // Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands.
837 // These fragments are matched for little-endian, where the inputs must
838 // be swapped for correct semantics.
839 def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB),
840 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>;
841 def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB),
843 def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB),
847 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
849 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
851 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
853 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
855 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
857 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
860 // Match vmrg*(y,x), i.e., swapped operands. These fragments
861 // are matched for little-endian, where the inputs must be
862 // swapped for correct semantics.
863 def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
865 def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
867 def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
869 def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
871 def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
873 def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
876 // Logical Operations
877 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
879 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
881 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
884 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
886 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>;
888 // Fused multiply add and multiply sub for packed float. These are represented
889 // separately from the real instructions above, for operations that must have
890 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
891 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
892 (VMADDFP $A, $B, $C)>;
893 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
894 (VNMSUBFP $A, $B, $C)>;
896 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
897 (VMADDFP $A, $B, $C)>;
898 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
899 (VNMSUBFP $A, $B, $C)>;
901 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
902 (VPERM $vA, $vB, $vC)>;
904 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
905 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
908 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
909 (v16i8 (VSLB $vA, $vB))>;
910 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
911 (v8i16 (VSLH $vA, $vB))>;
912 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
913 (v4i32 (VSLW $vA, $vB))>;
915 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
916 (v16i8 (VSRB $vA, $vB))>;
917 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
918 (v8i16 (VSRH $vA, $vB))>;
919 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
920 (v4i32 (VSRW $vA, $vB))>;
922 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
923 (v16i8 (VSRAB $vA, $vB))>;
924 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
925 (v8i16 (VSRAH $vA, $vB))>;
926 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
927 (v4i32 (VSRAW $vA, $vB))>;
929 // Float to integer and integer to float conversions
930 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
932 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
934 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
936 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
939 // Floating-point rounding
940 def : Pat<(v4f32 (ffloor v4f32:$vA)),
942 def : Pat<(v4f32 (fceil v4f32:$vA)),
944 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
946 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
951 def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
952 def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">;
953 let Predicates = [HasP8Altivec] in {
955 let isCommutable = 1 in {
956 def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw,
958 def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw,
960 def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw,
962 def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw,
964 def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
965 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral,
966 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>;
967 def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>;
968 def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>;
969 def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>;
970 def VMIDUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;
974 def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>;
975 def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
976 "vsld $vD, $vA, $vB", IIC_VecGeneral,
977 [(set v2i64:$vD, (shl v2i64:$vA, v2i64:$vB))]>;
978 def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
979 "vsrd $vD, $vA, $vB", IIC_VecGeneral,
980 [(set v2i64:$vD, (srl v2i64:$vA, v2i64:$vB))]>;
981 def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
982 "vsrad $vD, $vA, $vB", IIC_VecGeneral,
983 [(set v2i64:$vD, (sra v2i64:$vA, v2i64:$vB))]>;
985 // Vector Integer Arithmetic Instructions
986 let isCommutable = 1 in {
987 def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
988 "vaddudm $vD, $vA, $vB", IIC_VecGeneral,
989 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>;
992 def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
993 "vsubudm $vD, $vA, $vB", IIC_VecGeneral,
994 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>;
996 // Count Leading Zeros
997 def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB),
998 "vclzb $vD, $vB", IIC_VecGeneral,
999 [(set v16i8:$vD, (ctlz v16i8:$vB))]>;
1000 def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB),
1001 "vclzh $vD, $vB", IIC_VecGeneral,
1002 [(set v8i16:$vD, (ctlz v8i16:$vB))]>;
1003 def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB),
1004 "vclzw $vD, $vB", IIC_VecGeneral,
1005 [(set v4i32:$vD, (ctlz v4i32:$vB))]>;
1006 def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB),
1007 "vclzd $vD, $vB", IIC_VecGeneral,
1008 [(set v2i64:$vD, (ctlz v2i64:$vB))]>;
1011 def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB),
1012 "vpopcntb $vD, $vB", IIC_VecGeneral,
1013 [(set v16i8:$vD, (ctpop v16i8:$vB))]>;
1014 def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB),
1015 "vpopcnth $vD, $vB", IIC_VecGeneral,
1016 [(set v8i16:$vD, (ctpop v8i16:$vB))]>;
1017 def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB),
1018 "vpopcntw $vD, $vB", IIC_VecGeneral,
1019 [(set v4i32:$vD, (ctpop v4i32:$vB))]>;
1020 def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB),
1021 "vpopcntd $vD, $vB", IIC_VecGeneral,
1022 [(set v2i64:$vD, (ctpop v2i64:$vB))]>;
1024 let isCommutable = 1 in {
1025 // FIXME: Use AddedComplexity > 400 to ensure these patterns match before the
1026 // VSX equivalents. We need to fix this up at some point. Two possible
1027 // solutions for this problem:
1028 // 1. Disable Altivec patterns that compete with VSX patterns using the
1029 // !HasVSX predicate. This essentially favours VSX over Altivec, in
1030 // hopes of reducing register pressure (larger register set using VSX
1031 // instructions than VMX instructions)
1032 // 2. Employ a more disciplined use of AddedComplexity, which would provide
1033 // more fine-grained control than option 1. This would be beneficial
1034 // if we find situations where Altivec is really preferred over VSX.
1035 def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1036 "veqv $vD, $vA, $vB", IIC_VecGeneral,
1037 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>;
1038 def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1039 "vnand $vD, $vA, $vB", IIC_VecGeneral,
1040 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>;
1043 def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1044 "vorc $vD, $vA, $vB", IIC_VecGeneral,
1045 [(set v4i32:$vD, (or v4i32:$vA,
1046 (vnot_ppc v4i32:$vB)))]>;
1048 // i64 element comparisons.
1049 def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>;
1050 def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>;
1051 def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>;
1052 def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
1053 def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>;
1054 def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
1056 // The cryptography instructions that do not require Category:Vector.Crypto
1057 def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
1058 int_ppc_altivec_crypto_vpmsumb, v16i8>;
1059 def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",
1060 int_ppc_altivec_crypto_vpmsumh, v8i16>;
1061 def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",
1062 int_ppc_altivec_crypto_vpmsumw, v4i32>;
1063 def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",
1064 int_ppc_altivec_crypto_vpmsumd, v2i64>;
1065 def VPERMXOR : VA1a_Int_Ty<45, "vpermxor",
1066 int_ppc_altivec_crypto_vpermxor, v16i8>;
1068 } // end HasP8Altivec
1070 // Crypto instructions (from builtins)
1071 let Predicates = [HasP8Crypto] in {
1072 def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw",
1073 int_ppc_altivec_crypto_vshasigmaw, v4i32>;
1074 def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad",
1075 int_ppc_altivec_crypto_vshasigmad, v2i64>;
1076 def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher,
1078 def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",
1079 int_ppc_altivec_crypto_vcipherlast, v2i64>;
1080 def VNCIPHER : VX1_Int_Ty<1352, "vncipher",
1081 int_ppc_altivec_crypto_vncipher, v2i64>;
1082 def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
1083 int_ppc_altivec_crypto_vncipherlast, v2i64>;
1084 def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;