1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 /// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
19 /// shuffle mask for the VPKUHUM or VPKUWUM instructions.
20 def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
21 return PPC::isVPKUHUMShuffleMask(N);
23 def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isVPKUWUMShuffleMask(N);
27 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
28 def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
29 return getI32Imm(PPC::getVSPLTImmediate(N, 1));
31 def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
32 return PPC::isSplatShuffleMask(N, 1);
34 def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
35 return getI32Imm(PPC::getVSPLTImmediate(N, 2));
37 def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
38 return PPC::isSplatShuffleMask(N, 2);
40 def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
41 return getI32Imm(PPC::getVSPLTImmediate(N, 4));
43 def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
44 return PPC::isSplatShuffleMask(N, 4);
48 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
49 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
51 PPC::isVecSplatImm(N, 1, &Val);
52 return getI32Imm(Val);
54 def vecspltisb : PatLeaf<(build_vector), [{
55 return PPC::isVecSplatImm(N, 1);
56 }], VSPLTISB_get_imm>;
58 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
59 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
61 PPC::isVecSplatImm(N, 2, &Val);
62 return getI32Imm(Val);
64 def vecspltish : PatLeaf<(build_vector), [{
65 return PPC::isVecSplatImm(N, 2);
66 }], VSPLTISH_get_imm>;
68 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
69 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
71 PPC::isVecSplatImm(N, 4, &Val);
72 return getI32Imm(Val);
74 def vecspltisw : PatLeaf<(build_vector), [{
75 return PPC::isVecSplatImm(N, 4);
76 }], VSPLTISW_get_imm>;
78 //===----------------------------------------------------------------------===//
79 // Helpers for defining instructions that directly correspond to intrinsics.
81 // VA1a_Int - A VAForm_1a intrinsic definition.
82 class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
83 : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
84 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
85 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
87 // VX1_Int - A VXForm_1 intrinsic definition.
88 class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
89 : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
90 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
91 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
93 // VX2_Int - A VXForm_2 intrinsic definition.
94 class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
95 : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
96 !strconcat(opc, " $vD, $vB"), VecFP,
97 [(set VRRC:$vD, (IntID VRRC:$vB))]>;
99 //===----------------------------------------------------------------------===//
100 // Instruction Definitions.
102 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
103 [(set VRRC:$rD, (v4f32 (undef)))]>;
105 let noResults = 1 in {
106 def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
107 "dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
108 def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
109 "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
110 def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
111 "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
114 def MFVSCR : VXForm_4<1540, (ops VRRC:$vD),
115 "mfvcr $vD", LdStGeneral,
116 [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
117 def MTVSCR : VXForm_5<1604, (ops VRRC:$vB),
118 "mtvcr $vB", LdStGeneral,
119 [(int_ppc_altivec_mtvscr VRRC:$vB)]>;
121 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
122 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
123 "lvebx $vD, $src", LdStGeneral,
124 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
125 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
126 "lvehx $vD, $src", LdStGeneral,
127 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
128 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
129 "lvewx $vD, $src", LdStGeneral,
130 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
131 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
132 "lvx $vD, $src", LdStGeneral,
133 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
134 def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
135 "lvxl $vD, $src", LdStGeneral,
136 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
139 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src),
140 "lvsl $vD, $src", LdStGeneral,
141 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
143 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src),
144 "lvsr $vD, $src", LdStGeneral,
145 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
148 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
149 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
150 "stvebx $rS, $dst", LdStGeneral,
151 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
152 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
153 "stvehx $rS, $dst", LdStGeneral,
154 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
155 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
156 "stvewx $rS, $dst", LdStGeneral,
157 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
158 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
159 "stvx $rS, $dst", LdStGeneral,
160 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
161 def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
162 "stvxl $rS, $dst", LdStGeneral,
163 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
166 let PPC970_Unit = 5 in { // VALU Operations.
167 // VA-Form instructions. 3-input AltiVec ops.
168 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
169 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
170 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
172 Requires<[FPContractions]>;
173 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
174 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
175 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
177 Requires<[FPContractions]>;
179 def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
180 def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
181 def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>;
182 def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
183 def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
185 def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
186 "vsldoi $vD, $vA, $vB, $SH", VecFP,
188 (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
191 // VX-Form instructions. AltiVec arithmetic ops.
192 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
193 "vaddfp $vD, $vA, $vB", VecFP,
194 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
196 def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
197 "vaddubm $vD, $vA, $vB", VecGeneral,
198 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
199 def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
200 "vadduhm $vD, $vA, $vB", VecGeneral,
201 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
202 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
203 "vadduwm $vD, $vA, $vB", VecGeneral,
204 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
206 def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
207 def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
208 def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
209 def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
210 def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
211 def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
212 def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
215 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
216 "vand $vD, $vA, $vB", VecFP,
217 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
218 def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
219 "vandc $vD, $vA, $vB", VecFP,
220 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
222 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
223 "vcfsx $vD, $vB, $UIMM", VecFP,
225 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
226 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
227 "vcfux $vD, $vB, $UIMM", VecFP,
229 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
230 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
231 "vctsxs $vD, $vB, $UIMM", VecFP,
233 (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>;
234 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
235 "vctuxs $vD, $vB, $UIMM", VecFP,
237 (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>;
238 def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
239 def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>;
241 def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>;
242 def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>;
243 def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>;
244 def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>;
245 def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>;
246 def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>;
248 def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>;
249 def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>;
250 def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>;
251 def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>;
252 def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>;
253 def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>;
254 def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>;
255 def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>;
256 def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>;
257 def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>;
258 def VMINSW : VX1_Int< 896, "vminsw", int_ppc_altivec_vminsw>;
259 def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>;
260 def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
261 def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
263 def VMRGHB : VX1_Int<12 , "vmrghb", int_ppc_altivec_vmrghb>;
264 def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>;
265 def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>;
266 def VMRGLB : VX1_Int<268, "vmrglb", int_ppc_altivec_vmrglb>;
267 def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>;
268 def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>;
270 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
271 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
272 def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
273 def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
274 def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
275 def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
277 def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
278 def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
279 def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
280 def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
281 def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
282 def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
283 def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
284 def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
286 def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
287 def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
288 def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
289 def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
290 def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
291 def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
293 def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
295 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
296 "vsubfp $vD, $vA, $vB", VecGeneral,
297 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
298 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
299 "vsububm $vD, $vA, $vB", VecGeneral,
300 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
301 def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
302 "vsubuhm $vD, $vA, $vB", VecGeneral,
303 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
304 def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
305 "vsubuwm $vD, $vA, $vB", VecGeneral,
306 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
308 def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
309 def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
310 def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
311 def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
312 def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
313 def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
314 def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
315 def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
316 def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
317 def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
318 def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
320 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
321 "vnor $vD, $vA, $vB", VecFP,
322 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
323 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
324 "vor $vD, $vA, $vB", VecFP,
325 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
326 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
327 "vxor $vD, $vA, $vB", VecFP,
328 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
330 def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
331 def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
332 def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
334 def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >;
335 def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
336 def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
337 def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
338 def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
340 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
341 "vspltb $vD, $vB, $UIMM", VecPerm,
342 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
343 VSPLTB_shuffle_mask:$UIMM))]>;
344 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
345 "vsplth $vD, $vB, $UIMM", VecPerm,
346 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
347 VSPLTH_shuffle_mask:$UIMM))]>;
348 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
349 "vspltw $vD, $vB, $UIMM", VecPerm,
350 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
351 VSPLTW_shuffle_mask:$UIMM))]>;
353 def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
354 def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
355 def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
356 def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
357 def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
358 def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
359 def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
360 def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
363 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
364 "vspltisb $vD, $SIMM", VecPerm,
365 [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
366 def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
367 "vspltish $vD, $SIMM", VecPerm,
368 [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
369 def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
370 "vspltisw $vD, $SIMM", VecPerm,
371 [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
374 def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
375 def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
376 def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
377 def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
378 def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
379 def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
380 "vpkuhum $vD, $vA, $vB", VecFP,
381 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
382 VRRC:$vB, VPKUHUM_shuffle_mask))]>;
383 def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
384 def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
385 "vpkuwum $vD, $vA, $vB", VecFP,
386 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
387 VRRC:$vB, VPKUWUM_shuffle_mask))]>;
388 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
391 def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
392 def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
393 def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
394 def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
395 def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
396 def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
399 // Altivec Comparisons.
401 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
402 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
403 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
404 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
405 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
406 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> {
411 // f32 element comparisons.0
412 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
413 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
414 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
415 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
416 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
417 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
418 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
419 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
421 // i8 element comparisons.
422 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
423 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
424 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
425 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
426 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
427 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
429 // i16 element comparisons.
430 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
431 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
432 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
433 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
434 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
435 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
437 // i32 element comparisons.
438 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
439 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
440 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
441 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
442 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
443 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
445 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
446 "vxor $vD, $vD, $vD", VecFP,
447 [(set VRRC:$vD, (v4f32 immAllZerosV))]>;
450 //===----------------------------------------------------------------------===//
451 // Additional Altivec Patterns
455 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
456 def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>;
457 def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
458 (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
459 def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
460 (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
461 def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
462 (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
463 def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
464 (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
467 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
468 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
469 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
470 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
471 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
472 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
475 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
476 def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
477 def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
478 def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
481 def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
482 (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
483 def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
484 (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
485 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
486 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
487 def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
488 (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
491 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
492 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
493 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
495 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
496 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
497 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
499 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
500 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
501 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
503 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
504 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
505 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
507 // Immediate vector formation with vsplti*.
508 def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
509 def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
510 def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
512 def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
513 def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
514 def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
516 def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
517 def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
518 def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
520 // Logical Operations
521 def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>;
522 def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>;
523 def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>;
525 def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
526 def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
527 def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
528 def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
529 def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
530 def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
531 def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
532 def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
533 def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
534 (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
535 def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
536 (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
538 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
539 (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
541 // Fused multiply add and multiply sub for packed float. These are represented
542 // separately from the real instructions above, for operations that must have
543 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
544 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
545 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
546 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
547 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
549 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
550 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
551 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
552 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
554 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
555 (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;