1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
19 def VSPLT_get_imm : SDNodeXForm<build_vector, [{
20 return getI32Imm(PPC::getVSPLTImmediate(N));
23 def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isSplatShuffleMask(N);
27 def vecimm0 : PatLeaf<(build_vector), [{
28 return PPC::isZeroVector(N);
32 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
33 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
35 PPC::isVecSplatImm(N, 1, &Val);
36 return getI32Imm(Val);
38 def vecspltisb : PatLeaf<(build_vector), [{
39 return PPC::isVecSplatImm(N, 1);
40 }], VSPLTISB_get_imm>;
42 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
43 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
45 PPC::isVecSplatImm(N, 2, &Val);
46 return getI32Imm(Val);
48 def vecspltish : PatLeaf<(build_vector), [{
49 return PPC::isVecSplatImm(N, 2);
50 }], VSPLTISH_get_imm>;
52 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
53 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
55 PPC::isVecSplatImm(N, 4, &Val);
56 return getI32Imm(Val);
58 def vecspltisw : PatLeaf<(build_vector), [{
59 return PPC::isVecSplatImm(N, 4);
60 }], VSPLTISW_get_imm>;
62 class isVDOT { // vector dot instruction.
63 list<Register> Defs = [CR6];
67 //===----------------------------------------------------------------------===//
68 // Instruction Definitions.
70 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
71 [(set VRRC:$rD, (v4f32 (undef)))]>;
73 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
74 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
75 "lvebx $vD, $src", LdStGeneral,
76 [(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
77 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
78 "lvehx $vD, $src", LdStGeneral,
79 [(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
80 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
81 "lvewx $vD, $src", LdStGeneral,
82 [(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
83 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
84 "lvx $vD, $src", LdStGeneral,
85 [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
88 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
89 "lvsl $vD, $base, $rA", LdStGeneral,
91 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
92 "lvsl $vD, $base, $rA", LdStGeneral,
95 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
96 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
97 "stvebx $rS, $rA, $rB", LdStGeneral,
99 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
100 "stvehx $rS, $rA, $rB", LdStGeneral,
102 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
103 "stvewx $rS, $rA, $rB", LdStGeneral,
105 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
106 "stvx $rS, $dst", LdStGeneral,
107 [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
110 let PPC970_Unit = 5 in { // VALU Operations.
111 // VA-Form instructions. 3-input AltiVec ops.
112 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
113 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
114 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
116 Requires<[FPContractions]>;
117 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
118 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
119 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
121 Requires<[FPContractions]>;
123 def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
124 "vperm $vD, $vA, $vB, $vC", VecPerm,
126 (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
127 def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
128 "vsldoi $vD, $vA, $vB, $SH", VecFP,
130 (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
133 // VX-Form instructions. AltiVec arithmetic ops.
134 def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
135 "vaddcuw $vD, $vA, $vB", VecFP,
137 (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>;
138 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
139 "vaddfp $vD, $vA, $vB", VecFP,
140 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
142 def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
143 "vaddubm $vD, $vA, $vB", VecGeneral,
144 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
145 def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
146 "vadduhm $vD, $vA, $vB", VecGeneral,
147 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
148 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
149 "vadduwm $vD, $vA, $vB", VecGeneral,
150 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
152 def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
153 "vaddsbs $vD, $vA, $vB", VecFP,
155 (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>;
156 def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
157 "vaddshs $vD, $vA, $vB", VecFP,
159 (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>;
160 def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
161 "vaddsws $vD, $vA, $vB", VecFP,
163 (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>;
165 def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
166 "vaddubs $vD, $vA, $vB", VecFP,
168 (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>;
169 def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
170 "vadduhs $vD, $vA, $vB", VecFP,
172 (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>;
173 def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
174 "vadduws $vD, $vA, $vB", VecFP,
176 (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>;
177 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
178 "vand $vD, $vA, $vB", VecFP,
179 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
180 def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
181 "vandc $vD, $vA, $vB", VecFP,
182 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
184 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
185 "vcfsx $vD, $vB, $UIMM", VecFP,
187 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
188 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
189 "vcfux $vD, $vB, $UIMM", VecFP,
191 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
192 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
193 "vctsxs $vD, $vB, $UIMM", VecFP,
195 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
196 "vctuxs $vD, $vB, $UIMM", VecFP,
198 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
199 "vexptefp $vD, $vB", VecFP,
201 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
202 "vlogefp $vD, $vB", VecFP,
204 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
205 "vmaxfp $vD, $vA, $vB", VecFP,
207 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
208 "vminfp $vD, $vA, $vB", VecFP,
210 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
211 "vrefp $vD, $vB", VecFP,
213 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
214 "vrfim $vD, $vB", VecFP,
216 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
217 "vrfin $vD, $vB", VecFP,
219 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
220 "vrfip $vD, $vB", VecFP,
222 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
223 "vrfiz $vD, $vB", VecFP,
225 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
226 "vrsqrtefp $vD, $vB", VecFP,
227 [(set VRRC:$vD,(int_ppc_altivec_vrsqrtefp VRRC:$vB))]>;
228 def VSUBCUW : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
229 "vsubcuw $vD, $vA, $vB", VecFP,
231 (int_ppc_altivec_vsubcuw VRRC:$vA, VRRC:$vB))]>;
232 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
233 "vsubfp $vD, $vA, $vB", VecFP,
234 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
236 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
237 "vsububm $vD, $vA, $vB", VecGeneral,
238 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
239 def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
240 "vsubuhm $vD, $vA, $vB", VecGeneral,
241 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
242 def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
243 "vsubuwm $vD, $vA, $vB", VecGeneral,
244 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
246 def VSUBSBS : VXForm_1<1792, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
247 "vsubsbs $vD, $vA, $vB", VecFP,
249 (int_ppc_altivec_vsubsbs VRRC:$vA, VRRC:$vB))]>;
250 def VSUBSHS : VXForm_1<1856, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
251 "vsubshs $vD, $vA, $vB", VecFP,
253 (int_ppc_altivec_vsubshs VRRC:$vA, VRRC:$vB))]>;
254 def VSUBSWS : VXForm_1<1920, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
255 "vsubsws $vD, $vA, $vB", VecFP,
257 (int_ppc_altivec_vsubsws VRRC:$vA, VRRC:$vB))]>;
259 def VSUBUBS : VXForm_1<1536, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
260 "vsububs $vD, $vA, $vB", VecFP,
262 (int_ppc_altivec_vsububs VRRC:$vA, VRRC:$vB))]>;
263 def VSUBUHS : VXForm_1<1600, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
264 "vsubuhs $vD, $vA, $vB", VecFP,
266 (int_ppc_altivec_vsubuhs VRRC:$vA, VRRC:$vB))]>;
267 def VSUBUWS : VXForm_1<1664, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
268 "vsubuws $vD, $vA, $vB", VecFP,
270 (int_ppc_altivec_vsubuws VRRC:$vA, VRRC:$vB))]>;
272 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
273 "vnor $vD, $vA, $vB", VecFP,
274 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
275 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
276 "vor $vD, $vA, $vB", VecFP,
277 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
278 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
279 "vxor $vD, $vA, $vB", VecFP,
280 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
282 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
283 "vspltb $vD, $vB, $UIMM", VecPerm,
285 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
286 "vsplth $vD, $vB, $UIMM", VecPerm,
288 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
289 "vspltw $vD, $vB, $UIMM", VecPerm,
290 [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
291 VSPLT_shuffle_mask:$UIMM))]>;
293 def VSPLTISB : VXForm_1<780, (ops VRRC:$vD, s5imm:$SIMM),
294 "vspltisb $vD, $SIMM", VecPerm,
295 [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
296 def VSPLTISH : VXForm_1<844, (ops VRRC:$vD, s5imm:$SIMM),
297 "vspltish $vD, $SIMM", VecPerm,
298 [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
299 def VSPLTISW : VXForm_1<908, (ops VRRC:$vD, s5imm:$SIMM),
300 "vspltisw $vD, $SIMM", VecPerm,
301 [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
304 // Altivec Comparisons.
306 // f32 element comparisons.
307 def VCMPBFP : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
308 "vcmpbfp $vD, $vA, $vB", VecFPCompare,
310 (int_ppc_altivec_vcmpbfp VRRC:$vA, VRRC:$vB))]>;
311 def VCMPBFPo : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
312 "vcmpbfp. $vD, $vA, $vB", VecFPCompare,
314 def VCMPEQFP : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
315 "vcmpeqfp $vD, $vA, $vB", VecFPCompare,
317 (int_ppc_altivec_vcmpeqfp VRRC:$vA, VRRC:$vB))]>;
318 def VCMPEQFPo : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
319 "vcmpeqfp. $vD, $vA, $vB", VecFPCompare,
321 def VCMPGEFP : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
322 "vcmpgefp $vD, $vA, $vB", VecFPCompare,
324 (int_ppc_altivec_vcmpgefp VRRC:$vA, VRRC:$vB))]>;
325 def VCMPGEFPo : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
326 "vcmpgefp. $vD, $vA, $vB", VecFPCompare,
328 def VCMPGTFP : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
329 "vcmpgtfp $vD, $vA, $vB", VecFPCompare,
331 (int_ppc_altivec_vcmpgtfp VRRC:$vA, VRRC:$vB))]>;
332 def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
333 "vcmpgtfp. $vD, $vA, $vB", VecFPCompare,
336 // i8 element comparisons.
337 def VCMPEQUB : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
338 "vcmpequb $vD, $vA, $vB", VecFPCompare,
340 (int_ppc_altivec_vcmpequb VRRC:$vA, VRRC:$vB))]>;
341 def VCMPEQUBo : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
342 "vcmpequb. $vD, $vA, $vB", VecFPCompare,
344 def VCMPGTSB : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
345 "vcmpgtsb $vD, $vA, $vB", VecFPCompare,
347 (int_ppc_altivec_vcmpgtsb VRRC:$vA, VRRC:$vB))]>;
348 def VCMPGTSBo : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
349 "vcmpgtsb. $vD, $vA, $vB", VecFPCompare,
351 def VCMPGTUB : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
352 "vcmpgtub $vD, $vA, $vB", VecFPCompare,
354 (int_ppc_altivec_vcmpgtub VRRC:$vA, VRRC:$vB))]>;
355 def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
356 "vcmpgtub. $vD, $vA, $vB", VecFPCompare,
359 // i16 element comparisons.
360 def VCMPEQUH : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
361 "vcmpequh $vD, $vA, $vB", VecFPCompare,
363 (int_ppc_altivec_vcmpequh VRRC:$vA, VRRC:$vB))]>;
364 def VCMPEQUHo : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
365 "vcmpequh. $vD, $vA, $vB", VecFPCompare,
367 def VCMPGTSH : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
368 "vcmpgtsh $vD, $vA, $vB", VecFPCompare,
370 (int_ppc_altivec_vcmpgtsh VRRC:$vA, VRRC:$vB))]>;
371 def VCMPGTSHo : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
372 "vcmpgtsh. $vD, $vA, $vB", VecFPCompare,
374 def VCMPGTUH : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
375 "vcmpgtuh $vD, $vA, $vB", VecFPCompare,
377 (int_ppc_altivec_vcmpgtuh VRRC:$vA, VRRC:$vB))]>;
378 def VCMPGTUHo : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
379 "vcmpgtuh. $vD, $vA, $vB", VecFPCompare,
382 // i32 element comparisons.
383 def VCMPEQUW : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
384 "vcmpequw $vD, $vA, $vB", VecFPCompare,
386 (int_ppc_altivec_vcmpequw VRRC:$vA, VRRC:$vB))]>;
387 def VCMPEQUWo : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
388 "vcmpequw. $vD, $vA, $vB", VecFPCompare,
390 def VCMPGTSW : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
391 "vcmpgtsw $vD, $vA, $vB", VecFPCompare,
393 (int_ppc_altivec_vcmpgtsw VRRC:$vA, VRRC:$vB))]>;
394 def VCMPGTSWo : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
395 "vcmpgtsw. $vD, $vA, $vB", VecFPCompare,
397 def VCMPGTUW : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
398 "vcmpgtuw $vD, $vA, $vB", VecFPCompare,
400 (int_ppc_altivec_vcmpgtuw VRRC:$vA, VRRC:$vB))]>;
401 def VCMPGTUWo : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
402 "vcmpgtuw. $vD, $vA, $vB", VecFPCompare,
405 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
406 "vxor $vD, $vD, $vD", VecFP,
407 [(set VRRC:$vD, (v4f32 vecimm0))]>;
410 //===----------------------------------------------------------------------===//
411 // Additional Altivec Patterns
415 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
416 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
417 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
418 def : Pat<(v16i8 vecimm0), (v16i8 (V_SET0))>;
419 def : Pat<(v8i16 vecimm0), (v8i16 (V_SET0))>;
420 def : Pat<(v4i32 vecimm0), (v4i32 (V_SET0))>;
423 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
424 def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
425 def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
428 def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
429 (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
430 def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
431 (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
432 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
433 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
436 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
437 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
438 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
440 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
441 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
442 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
444 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
445 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
446 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
448 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
449 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
450 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
452 // Immediate vector formation with vsplti*.
453 def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
454 def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
455 def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
457 def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
458 def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
459 def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
461 def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
462 def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
463 def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
465 // Logical Operations
466 def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
467 def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
468 def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
469 def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
470 def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
471 def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
472 def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
473 def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
474 def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
475 (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
476 def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
477 (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
479 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
480 (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
482 // Fused multiply add and multiply sub for packed float. These are represented
483 // separately from the real instructions above, for operations that must have
484 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
485 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
486 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
487 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
488 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
490 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
491 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
492 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
493 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
495 def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
496 (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
498 def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
499 (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
501 def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
502 (v4i32 (LVEWX xoaddr:$src))>;