1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 /// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
19 /// shuffle mask for the VPKUHUM or VPKUWUM instructions.
20 def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
21 return PPC::isVPKUHUMShuffleMask(N, false);
23 def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isVPKUWUMShuffleMask(N, false);
27 def VPKUHUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
28 return PPC::isVPKUHUMShuffleMask(N, true);
30 def VPKUWUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
31 return PPC::isVPKUWUMShuffleMask(N, true);
35 def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
36 return PPC::isVMRGLShuffleMask(N, 1, false);
38 def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
39 return PPC::isVMRGLShuffleMask(N, 2, false);
41 def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
42 return PPC::isVMRGLShuffleMask(N, 4, false);
44 def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
45 return PPC::isVMRGHShuffleMask(N, 1, false);
47 def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
48 return PPC::isVMRGHShuffleMask(N, 2, false);
50 def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
51 return PPC::isVMRGHShuffleMask(N, 4, false);
54 def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{
55 return PPC::isVMRGLShuffleMask(N, 1, true);
57 def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{
58 return PPC::isVMRGLShuffleMask(N, 2, true);
60 def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{
61 return PPC::isVMRGLShuffleMask(N, 4, true);
63 def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{
64 return PPC::isVMRGHShuffleMask(N, 1, true);
66 def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{
67 return PPC::isVMRGHShuffleMask(N, 2, true);
69 def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
70 return PPC::isVMRGHShuffleMask(N, 4, true);
73 def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
74 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
76 def VSLDOI_shuffle_mask : PatLeaf<(build_vector), [{
77 return PPC::isVSLDOIShuffleMask(N, false) != -1;
80 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
81 /// vector_shuffle(X,undef,mask) by the dag combiner.
82 def VSLDOI_unary_get_imm : SDNodeXForm<build_vector, [{
83 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
85 def VSLDOI_unary_shuffle_mask : PatLeaf<(build_vector), [{
86 return PPC::isVSLDOIShuffleMask(N, true) != -1;
87 }], VSLDOI_unary_get_imm>;
90 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
91 def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
92 return getI32Imm(PPC::getVSPLTImmediate(N, 1));
94 def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
95 return PPC::isSplatShuffleMask(N, 1);
97 def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
98 return getI32Imm(PPC::getVSPLTImmediate(N, 2));
100 def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
101 return PPC::isSplatShuffleMask(N, 2);
103 def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
104 return getI32Imm(PPC::getVSPLTImmediate(N, 4));
106 def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
107 return PPC::isSplatShuffleMask(N, 4);
111 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
112 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
113 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
115 def vecspltisb : PatLeaf<(build_vector), [{
116 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).Val != 0;
117 }], VSPLTISB_get_imm>;
119 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
120 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
121 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
123 def vecspltish : PatLeaf<(build_vector), [{
124 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).Val != 0;
125 }], VSPLTISH_get_imm>;
127 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
128 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
129 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
131 def vecspltisw : PatLeaf<(build_vector), [{
132 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
133 }], VSPLTISW_get_imm>;
135 def V_immneg0 : PatLeaf<(build_vector), [{
136 return PPC::isAllNegativeZeroVector(N);
139 //===----------------------------------------------------------------------===//
140 // Helpers for defining instructions that directly correspond to intrinsics.
142 // VA1a_Int - A VAForm_1a intrinsic definition.
143 class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
144 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
145 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
146 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
148 // VX1_Int - A VXForm_1 intrinsic definition.
149 class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
150 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
151 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
152 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
154 // VX2_Int - A VXForm_2 intrinsic definition.
155 class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
156 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB),
157 !strconcat(opc, " $vD, $vB"), VecFP,
158 [(set VRRC:$vD, (IntID VRRC:$vB))]>;
160 //===----------------------------------------------------------------------===//
161 // Instruction Definitions.
163 def IMPLICIT_DEF_VRRC : Pseudo<(outs VRRC:$rD), (ins),"; IMPLICIT_DEF_VRRC $rD",
164 [(set VRRC:$rD, (v4i32 (undef)))]>;
166 def DSS : DSS_Form<822, (outs), (ins u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
167 "dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
168 def DST : DSS_Form<342, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
169 "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
170 def DSTST : DSS_Form<374, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
171 "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
173 def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins),
174 "mfvscr $vD", LdStGeneral,
175 [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
176 def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB),
177 "mtvscr $vB", LdStGeneral,
178 [(int_ppc_altivec_mtvscr VRRC:$vB)]>;
180 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
181 def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src),
182 "lvebx $vD, $src", LdStGeneral,
183 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
184 def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src),
185 "lvehx $vD, $src", LdStGeneral,
186 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
187 def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src),
188 "lvewx $vD, $src", LdStGeneral,
189 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
190 def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src),
191 "lvx $vD, $src", LdStGeneral,
192 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
193 def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src),
194 "lvxl $vD, $src", LdStGeneral,
195 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
198 def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src),
199 "lvsl $vD, $src", LdStGeneral,
200 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
202 def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src),
203 "lvsr $vD, $src", LdStGeneral,
204 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
207 let isStore = 1, PPC970_Unit = 2 in { // Stores.
208 def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst),
209 "stvebx $rS, $dst", LdStGeneral,
210 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
211 def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst),
212 "stvehx $rS, $dst", LdStGeneral,
213 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
214 def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst),
215 "stvewx $rS, $dst", LdStGeneral,
216 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
217 def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst),
218 "stvx $rS, $dst", LdStGeneral,
219 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
220 def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst),
221 "stvxl $rS, $dst", LdStGeneral,
222 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
225 let PPC970_Unit = 5 in { // VALU Operations.
226 // VA-Form instructions. 3-input AltiVec ops.
227 def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
228 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
229 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
231 Requires<[FPContractions]>;
232 def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
233 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
234 [(set VRRC:$vD, (fsub V_immneg0,
235 (fsub (fmul VRRC:$vA, VRRC:$vC),
237 Requires<[FPContractions]>;
239 def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
240 def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
241 def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>;
242 def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
243 def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
246 def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH),
247 "vsldoi $vD, $vA, $vB, $SH", VecFP,
249 (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB,
250 VSLDOI_shuffle_mask:$SH))]>;
252 // VX-Form instructions. AltiVec arithmetic ops.
253 def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
254 "vaddfp $vD, $vA, $vB", VecFP,
255 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
257 def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
258 "vaddubm $vD, $vA, $vB", VecGeneral,
259 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
260 def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
261 "vadduhm $vD, $vA, $vB", VecGeneral,
262 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
263 def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
264 "vadduwm $vD, $vA, $vB", VecGeneral,
265 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
267 def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
268 def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
269 def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
270 def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
271 def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
272 def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
273 def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
276 def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
277 "vand $vD, $vA, $vB", VecFP,
278 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
279 def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
280 "vandc $vD, $vA, $vB", VecFP,
281 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
283 def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
284 "vcfsx $vD, $vB, $UIMM", VecFP,
286 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
287 def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
288 "vcfux $vD, $vB, $UIMM", VecFP,
290 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
291 def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
292 "vctsxs $vD, $vB, $UIMM", VecFP,
294 (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>;
295 def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
296 "vctuxs $vD, $vB, $UIMM", VecFP,
298 (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>;
299 def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
300 def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>;
302 def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>;
303 def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>;
304 def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>;
305 def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>;
306 def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>;
307 def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>;
309 def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>;
310 def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>;
311 def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>;
312 def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>;
313 def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>;
314 def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>;
315 def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>;
316 def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>;
317 def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>;
318 def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>;
319 def VMINSW : VX1_Int< 898, "vminsw", int_ppc_altivec_vminsw>;
320 def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>;
321 def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
322 def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
324 def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
325 "vmrghb $vD, $vA, $vB", VecFP,
326 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
327 VRRC:$vB, VMRGHB_shuffle_mask))]>;
328 def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
329 "vmrghh $vD, $vA, $vB", VecFP,
330 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
331 VRRC:$vB, VMRGHH_shuffle_mask))]>;
332 def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
333 "vmrghw $vD, $vA, $vB", VecFP,
334 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
335 VRRC:$vB, VMRGHW_shuffle_mask))]>;
336 def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
337 "vmrglb $vD, $vA, $vB", VecFP,
338 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
339 VRRC:$vB, VMRGLB_shuffle_mask))]>;
340 def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
341 "vmrglh $vD, $vA, $vB", VecFP,
342 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
343 VRRC:$vB, VMRGLH_shuffle_mask))]>;
344 def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
345 "vmrglw $vD, $vA, $vB", VecFP,
346 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
347 VRRC:$vB, VMRGLW_shuffle_mask))]>;
349 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
350 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
351 def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
352 def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
353 def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
354 def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
356 def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
357 def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
358 def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
359 def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
360 def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
361 def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
362 def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
363 def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
365 def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
366 def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
367 def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
368 def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
369 def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
370 def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
372 def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
374 def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
375 "vsubfp $vD, $vA, $vB", VecGeneral,
376 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
377 def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
378 "vsububm $vD, $vA, $vB", VecGeneral,
379 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
380 def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
381 "vsubuhm $vD, $vA, $vB", VecGeneral,
382 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
383 def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
384 "vsubuwm $vD, $vA, $vB", VecGeneral,
385 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
387 def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
388 def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
389 def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
390 def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
391 def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
392 def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
393 def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
394 def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
395 def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
396 def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
397 def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
399 def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
400 "vnor $vD, $vA, $vB", VecFP,
401 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
402 def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
403 "vor $vD, $vA, $vB", VecFP,
404 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
405 def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
406 "vxor $vD, $vA, $vB", VecFP,
407 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
409 def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
410 def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
411 def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
413 def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >;
414 def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
415 def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
416 def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
417 def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
419 def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
420 "vspltb $vD, $vB, $UIMM", VecPerm,
421 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
422 VSPLTB_shuffle_mask:$UIMM))]>;
423 def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
424 "vsplth $vD, $vB, $UIMM", VecPerm,
425 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
426 VSPLTH_shuffle_mask:$UIMM))]>;
427 def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
428 "vspltw $vD, $vB, $UIMM", VecPerm,
429 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
430 VSPLTW_shuffle_mask:$UIMM))]>;
432 def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
433 def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
434 def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
435 def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
436 def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
437 def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
438 def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
439 def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
442 def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM),
443 "vspltisb $vD, $SIMM", VecPerm,
444 [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>;
445 def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM),
446 "vspltish $vD, $SIMM", VecPerm,
447 [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>;
448 def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM),
449 "vspltisw $vD, $SIMM", VecPerm,
450 [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>;
453 def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
454 def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
455 def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
456 def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
457 def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
458 def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
459 "vpkuhum $vD, $vA, $vB", VecFP,
460 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
461 VRRC:$vB, VPKUHUM_shuffle_mask))]>;
462 def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
463 def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
464 "vpkuwum $vD, $vA, $vB", VecFP,
465 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
466 VRRC:$vB, VPKUWUM_shuffle_mask))]>;
467 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
470 def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
471 def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
472 def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
473 def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
474 def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
475 def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
478 // Altivec Comparisons.
480 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
481 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
482 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
483 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
484 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
485 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> {
490 // f32 element comparisons.0
491 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
492 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
493 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
494 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
495 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
496 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
497 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
498 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
500 // i8 element comparisons.
501 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
502 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
503 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
504 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
505 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
506 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
508 // i16 element comparisons.
509 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
510 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
511 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
512 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
513 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
514 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
516 // i32 element comparisons.
517 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
518 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
519 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
520 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
521 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
522 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
524 def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins),
525 "vxor $vD, $vD, $vD", VecFP,
526 [(set VRRC:$vD, (v4i32 immAllZerosV))]>;
529 //===----------------------------------------------------------------------===//
530 // Additional Altivec Patterns
534 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
535 def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>;
536 def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
537 (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
538 def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
539 (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
540 def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
541 (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
542 def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
543 (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
546 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VRRC)>;
547 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VRRC)>;
548 def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VRRC)>;
551 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
554 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
555 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
558 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
559 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
560 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
562 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
563 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
564 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
566 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
567 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
568 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
570 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
571 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
572 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
576 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
577 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VSLDOI_unary_shuffle_mask:$in),
578 (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_unary_shuffle_mask:$in)>;
579 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUWUM_unary_shuffle_mask:$in),
580 (VPKUWUM VRRC:$vA, VRRC:$vA)>;
581 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUHUM_unary_shuffle_mask:$in),
582 (VPKUHUM VRRC:$vA, VRRC:$vA)>;
585 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in),
586 (VMRGLB VRRC:$vA, VRRC:$vA)>;
587 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in),
588 (VMRGLH VRRC:$vA, VRRC:$vA)>;
589 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in),
590 (VMRGLW VRRC:$vA, VRRC:$vA)>;
591 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in),
592 (VMRGHB VRRC:$vA, VRRC:$vA)>;
593 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in),
594 (VMRGHH VRRC:$vA, VRRC:$vA)>;
595 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
596 (VMRGHW VRRC:$vA, VRRC:$vA)>;
598 // Logical Operations
599 def : Pat<(v4i32 (vnot VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
600 def : Pat<(v4i32 (vnot_conv VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
602 def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))),
603 (VNOR VRRC:$A, VRRC:$B)>;
604 def : Pat<(v4i32 (and VRRC:$A, (vnot_conv VRRC:$B))),
605 (VANDC VRRC:$A, VRRC:$B)>;
607 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
608 (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>;
610 // Fused multiply add and multiply sub for packed float. These are represented
611 // separately from the real instructions above, for operations that must have
612 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
613 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
614 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
615 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
616 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
618 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
619 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
620 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
621 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
623 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
624 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>;