1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
19 def VSPLT_get_imm : SDNodeXForm<build_vector, [{
20 return getI32Imm(PPC::getVSPLTImmediate(N));
23 def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isSplatShuffleMask(N);
27 def vecimm0 : PatLeaf<(build_vector), [{
28 return PPC::isZeroVector(N);
32 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
33 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
35 PPC::isVecSplatImm(N, 1, &Val);
36 return getI32Imm(Val);
38 def vecspltisb : PatLeaf<(build_vector), [{
39 return PPC::isVecSplatImm(N, 1);
40 }], VSPLTISB_get_imm>;
42 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
43 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
45 PPC::isVecSplatImm(N, 2, &Val);
46 return getI32Imm(Val);
48 def vecspltish : PatLeaf<(build_vector), [{
49 return PPC::isVecSplatImm(N, 2);
50 }], VSPLTISH_get_imm>;
52 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
53 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
55 PPC::isVecSplatImm(N, 4, &Val);
56 return getI32Imm(Val);
58 def vecspltisw : PatLeaf<(build_vector), [{
59 return PPC::isVecSplatImm(N, 4);
60 }], VSPLTISW_get_imm>;
64 //===----------------------------------------------------------------------===//
65 // Instruction Definitions.
67 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
68 [(set VRRC:$rD, (v4f32 (undef)))]>;
70 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
71 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
72 "lvebx $vD, $src", LdStGeneral,
73 [(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
74 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
75 "lvehx $vD, $src", LdStGeneral,
76 [(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
77 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
78 "lvewx $vD, $src", LdStGeneral,
79 [(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
80 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
81 "lvx $vD, $src", LdStGeneral,
82 [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
85 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
86 "lvsl $vD, $base, $rA", LdStGeneral,
88 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
89 "lvsl $vD, $base, $rA", LdStGeneral,
92 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
93 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
94 "stvebx $rS, $rA, $rB", LdStGeneral,
96 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
97 "stvehx $rS, $rA, $rB", LdStGeneral,
99 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
100 "stvewx $rS, $rA, $rB", LdStGeneral,
102 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
103 "stvx $rS, $dst", LdStGeneral,
104 [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
107 let PPC970_Unit = 5 in { // VALU Operations.
108 // VA-Form instructions. 3-input AltiVec ops.
109 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
110 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
111 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
113 Requires<[FPContractions]>;
114 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
115 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
116 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
118 Requires<[FPContractions]>;
120 def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
121 "vperm $vD, $vA, $vB, $vC", VecPerm,
123 (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
124 def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
125 "vsldoi $vD, $vA, $vB, $SH", VecFP,
127 (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
130 // VX-Form instructions. AltiVec arithmetic ops.
131 def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
132 "vaddcuw $vD, $vA, $vB", VecFP,
134 (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>;
135 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
136 "vaddfp $vD, $vA, $vB", VecFP,
137 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
139 def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
140 "vaddubm $vD, $vA, $vB", VecGeneral,
141 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
142 def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
143 "vadduhm $vD, $vA, $vB", VecGeneral,
144 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
145 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
146 "vadduwm $vD, $vA, $vB", VecGeneral,
147 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
149 def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
150 "vaddsbs $vD, $vA, $vB", VecFP,
152 (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>;
153 def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
154 "vaddshs $vD, $vA, $vB", VecFP,
156 (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>;
157 def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
158 "vaddsws $vD, $vA, $vB", VecFP,
160 (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>;
162 def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
163 "vaddubs $vD, $vA, $vB", VecFP,
165 (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>;
166 def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
167 "vadduhs $vD, $vA, $vB", VecFP,
169 (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>;
170 def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
171 "vadduws $vD, $vA, $vB", VecFP,
173 (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>;
174 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
175 "vand $vD, $vA, $vB", VecFP,
176 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
177 def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
178 "vandc $vD, $vA, $vB", VecFP,
179 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
181 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
182 "vcfsx $vD, $vB, $UIMM", VecFP,
184 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
185 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
186 "vcfux $vD, $vB, $UIMM", VecFP,
188 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
189 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
190 "vctsxs $vD, $vB, $UIMM", VecFP,
192 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
193 "vctuxs $vD, $vB, $UIMM", VecFP,
195 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
196 "vexptefp $vD, $vB", VecFP,
198 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
199 "vlogefp $vD, $vB", VecFP,
201 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
202 "vmaxfp $vD, $vA, $vB", VecFP,
204 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
205 "vminfp $vD, $vA, $vB", VecFP,
207 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
208 "vrefp $vD, $vB", VecFP,
210 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
211 "vrfim $vD, $vB", VecFP,
213 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
214 "vrfin $vD, $vB", VecFP,
216 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
217 "vrfip $vD, $vB", VecFP,
219 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
220 "vrfiz $vD, $vB", VecFP,
222 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
223 "vrsqrtefp $vD, $vB", VecFP,
224 [(set VRRC:$vD,(int_ppc_altivec_vrsqrtefp VRRC:$vB))]>;
225 def VSUBCUW : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
226 "vsubcuw $vD, $vA, $vB", VecFP,
228 (int_ppc_altivec_vsubcuw VRRC:$vA, VRRC:$vB))]>;
229 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
230 "vsubfp $vD, $vA, $vB", VecFP,
231 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
233 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
234 "vsububm $vD, $vA, $vB", VecGeneral,
235 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
236 def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
237 "vsubuhm $vD, $vA, $vB", VecGeneral,
238 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
239 def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
240 "vsubuwm $vD, $vA, $vB", VecGeneral,
241 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
243 def VSUBSBS : VXForm_1<1792, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
244 "vsubsbs $vD, $vA, $vB", VecFP,
246 (int_ppc_altivec_vsubsbs VRRC:$vA, VRRC:$vB))]>;
247 def VSUBSHS : VXForm_1<1856, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
248 "vsubshs $vD, $vA, $vB", VecFP,
250 (int_ppc_altivec_vsubshs VRRC:$vA, VRRC:$vB))]>;
251 def VSUBSWS : VXForm_1<1920, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
252 "vsubsws $vD, $vA, $vB", VecFP,
254 (int_ppc_altivec_vsubsws VRRC:$vA, VRRC:$vB))]>;
256 def VSUBUBS : VXForm_1<1536, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
257 "vsububs $vD, $vA, $vB", VecFP,
259 (int_ppc_altivec_vsububs VRRC:$vA, VRRC:$vB))]>;
260 def VSUBUHS : VXForm_1<1600, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
261 "vsubuhs $vD, $vA, $vB", VecFP,
263 (int_ppc_altivec_vsubuhs VRRC:$vA, VRRC:$vB))]>;
264 def VSUBUWS : VXForm_1<1664, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
265 "vsubuws $vD, $vA, $vB", VecFP,
267 (int_ppc_altivec_vsubuws VRRC:$vA, VRRC:$vB))]>;
269 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
270 "vnor $vD, $vA, $vB", VecFP,
271 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
272 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
273 "vor $vD, $vA, $vB", VecFP,
274 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
275 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
276 "vxor $vD, $vA, $vB", VecFP,
277 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
279 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
280 "vspltb $vD, $vB, $UIMM", VecPerm,
282 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
283 "vsplth $vD, $vB, $UIMM", VecPerm,
285 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
286 "vspltw $vD, $vB, $UIMM", VecPerm,
287 [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
288 VSPLT_shuffle_mask:$UIMM))]>;
290 def VSPLTISB : VXForm_1<780, (ops VRRC:$vD, s5imm:$SIMM),
291 "vspltisb $vD, $SIMM", VecPerm,
292 [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
293 def VSPLTISH : VXForm_1<844, (ops VRRC:$vD, s5imm:$SIMM),
294 "vspltish $vD, $SIMM", VecPerm,
295 [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
296 def VSPLTISW : VXForm_1<908, (ops VRRC:$vD, s5imm:$SIMM),
297 "vspltisw $vD, $SIMM", VecPerm,
298 [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
301 // VX-Form Pseudo Instructions
303 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
304 "vxor $vD, $vD, $vD", VecFP,
305 [(set VRRC:$vD, (v4f32 vecimm0))]>;
308 //===----------------------------------------------------------------------===//
309 // Additional Altivec Patterns
313 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
314 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
315 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
316 def : Pat<(v16i8 vecimm0), (v16i8 (V_SET0))>;
317 def : Pat<(v8i16 vecimm0), (v8i16 (V_SET0))>;
318 def : Pat<(v4i32 vecimm0), (v4i32 (V_SET0))>;
321 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
322 def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
323 def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
326 def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
327 (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
328 def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
329 (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
330 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
331 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
334 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
335 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
336 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
338 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
339 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
340 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
342 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
343 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
344 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
346 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
347 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
348 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
350 // Immediate vector formation with vsplti*.
351 def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
352 def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
353 def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
355 def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
356 def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
357 def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
359 def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
360 def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
361 def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
363 // Logical Operations
364 def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
365 def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
366 def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
367 def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
368 def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
369 def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
370 def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
371 def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
372 def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
373 (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
374 def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
375 (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
377 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
378 (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
380 // Fused multiply add and multiply sub for packed float. These are represented
381 // separately from the real instructions above, for operations that must have
382 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
383 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
384 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
385 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
386 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
388 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
389 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
390 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
391 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
393 def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
394 (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
396 def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
397 (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
399 def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
400 (v4i32 (LVEWX xoaddr:$src))>;