1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
20 def vnot_ppc : PatFrag<(ops node:$in),
21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
23 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
24 (vector_shuffle node:$lhs, node:$rhs), [{
25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
27 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
28 (vector_shuffle node:$lhs, node:$rhs), [{
29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
31 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
32 (vector_shuffle node:$lhs, node:$rhs), [{
33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
35 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
36 (vector_shuffle node:$lhs, node:$rhs), [{
37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
41 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
43 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
45 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
49 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
53 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
55 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
57 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
61 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
67 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
69 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
71 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
72 (vector_shuffle node:$lhs, node:$rhs), [{
73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
75 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
76 (vector_shuffle node:$lhs, node:$rhs), [{
77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
79 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
80 (vector_shuffle node:$lhs, node:$rhs), [{
81 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
83 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
84 (vector_shuffle node:$lhs, node:$rhs), [{
85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
87 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
88 (vector_shuffle node:$lhs, node:$rhs), [{
89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
93 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
94 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
96 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
97 (vector_shuffle node:$lhs, node:$rhs), [{
98 return PPC::isVSLDOIShuffleMask(N, false) != -1;
102 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
103 /// vector_shuffle(X,undef,mask) by the dag combiner.
104 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
105 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
107 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
108 (vector_shuffle node:$lhs, node:$rhs), [{
109 return PPC::isVSLDOIShuffleMask(N, true) != -1;
110 }], VSLDOI_unary_get_imm>;
113 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
114 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
115 return getI32Imm(PPC::getVSPLTImmediate(N, 1));
117 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
118 (vector_shuffle node:$lhs, node:$rhs), [{
119 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
121 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
122 return getI32Imm(PPC::getVSPLTImmediate(N, 2));
124 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
125 (vector_shuffle node:$lhs, node:$rhs), [{
126 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
128 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
129 return getI32Imm(PPC::getVSPLTImmediate(N, 4));
131 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
132 (vector_shuffle node:$lhs, node:$rhs), [{
133 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
137 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
138 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
139 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
141 def vecspltisb : PatLeaf<(build_vector), [{
142 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
143 }], VSPLTISB_get_imm>;
145 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
146 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
147 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
149 def vecspltish : PatLeaf<(build_vector), [{
150 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
151 }], VSPLTISH_get_imm>;
153 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
154 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
155 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
157 def vecspltisw : PatLeaf<(build_vector), [{
158 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
159 }], VSPLTISW_get_imm>;
161 //===----------------------------------------------------------------------===//
162 // Helpers for defining instructions that directly correspond to intrinsics.
164 // VA1a_Int - A VAForm_1a intrinsic definition of generic type.
165 class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
166 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
167 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
168 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
170 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
171 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
172 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
173 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
174 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
176 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
177 // inputs doesn't match the type of the output.
178 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
180 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
181 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
182 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
184 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
185 // input types and an output type.
186 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
187 ValueType In1Ty, ValueType In2Ty>
188 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
189 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
191 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
193 // VX1_Int - A VXForm_1 intrinsic definition of generic type.
194 class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
195 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
196 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
197 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
199 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
200 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
201 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
202 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
203 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
205 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
206 // inputs doesn't match the type of the output.
207 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
209 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
210 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
211 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
213 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
214 // input types and an output type.
215 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
216 ValueType In1Ty, ValueType In2Ty>
217 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
218 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
219 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
221 // VX2_Int - A VXForm_1 intrinsic definition of generic type.
222 class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
223 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB),
224 !strconcat(opc, " $vD, $vB"), VecFP,
225 [(set VRRC:$vD, (IntID VRRC:$vB))]>;
227 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
228 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
229 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB),
230 !strconcat(opc, " $vD, $vB"), VecFP,
231 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
233 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
234 // inputs doesn't match the type of the output.
235 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
237 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB),
238 !strconcat(opc, " $vD, $vB"), VecFP,
239 [(set OutTy:$vD, (IntID InTy:$vB))]>;
241 //===----------------------------------------------------------------------===//
242 // Instruction Definitions.
244 def HasAltivec : Predicate<"PPCSubTarget.hasAltivec()">;
245 let Predicates = [HasAltivec] in {
247 let isCodeGenOnly = 1 in {
248 def DSS : DSS_Form<822, (outs),
249 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
250 "dss $STRM", LdStLoad /*FIXME*/, []>;
251 def DSSALL : DSS_Form<822, (outs),
252 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2),
253 "dssall", LdStLoad /*FIXME*/, []>;
254 def DST : DSS_Form<342, (outs),
255 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
256 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
257 def DSTT : DSS_Form<342, (outs),
258 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
259 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
260 def DSTST : DSS_Form<374, (outs),
261 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
262 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
263 def DSTSTT : DSS_Form<374, (outs),
264 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
265 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
267 def DST64 : DSS_Form<342, (outs),
268 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
269 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
270 def DSTT64 : DSS_Form<342, (outs),
271 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
272 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
273 def DSTST64 : DSS_Form<374, (outs),
274 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
275 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
276 def DSTSTT64 : DSS_Form<374, (outs),
277 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
278 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
281 def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins),
282 "mfvscr $vD", LdStStore,
283 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
284 def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB),
285 "mtvscr $vB", LdStLoad,
286 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
288 let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads.
289 def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src),
290 "lvebx $vD, $src", LdStLoad,
291 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
292 def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src),
293 "lvehx $vD, $src", LdStLoad,
294 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
295 def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src),
296 "lvewx $vD, $src", LdStLoad,
297 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
298 def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src),
299 "lvx $vD, $src", LdStLoad,
300 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
301 def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src),
302 "lvxl $vD, $src", LdStLoad,
303 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
306 def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src),
307 "lvsl $vD, $src", LdStLoad,
308 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
310 def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src),
311 "lvsr $vD, $src", LdStLoad,
312 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
315 let PPC970_Unit = 2 in { // Stores.
316 def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst),
317 "stvebx $rS, $dst", LdStStore,
318 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
319 def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst),
320 "stvehx $rS, $dst", LdStStore,
321 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
322 def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst),
323 "stvewx $rS, $dst", LdStStore,
324 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
325 def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst),
326 "stvx $rS, $dst", LdStStore,
327 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
328 def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst),
329 "stvxl $rS, $dst", LdStStore,
330 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
333 let PPC970_Unit = 5 in { // VALU Operations.
334 // VA-Form instructions. 3-input AltiVec ops.
335 def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
336 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
338 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
339 def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
340 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
341 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
342 (fneg v4f32:$vB))))]>;
344 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
345 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
347 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
349 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
350 v4i32, v4i32, v16i8>;
351 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
354 def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH),
355 "vsldoi $vD, $vA, $vB, $SH", VecFP,
357 (vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>;
359 // VX-Form instructions. AltiVec arithmetic ops.
360 def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
361 "vaddfp $vD, $vA, $vB", VecFP,
362 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
364 def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
365 "vaddubm $vD, $vA, $vB", VecGeneral,
366 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
367 def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
368 "vadduhm $vD, $vA, $vB", VecGeneral,
369 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
370 def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
371 "vadduwm $vD, $vA, $vB", VecGeneral,
372 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
374 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
375 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
376 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
377 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
378 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
379 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
380 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
383 def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
384 "vand $vD, $vA, $vB", VecFP,
385 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
386 def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
387 "vandc $vD, $vA, $vB", VecFP,
388 [(set VRRC:$vD, (and (v4i32 VRRC:$vA),
389 (vnot_ppc VRRC:$vB)))]>;
391 def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
392 "vcfsx $vD, $vB, $UIMM", VecFP,
394 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
395 def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
396 "vcfux $vD, $vB, $UIMM", VecFP,
398 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
399 def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
400 "vctsxs $vD, $vB, $UIMM", VecFP,
402 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
403 def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
404 "vctuxs $vD, $vB, $UIMM", VecFP,
406 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
408 // Defines with the UIM field set to 0 for floating-point
409 // to integer (fp_to_sint/fp_to_uint) conversions and integer
410 // to floating-point (sint_to_fp/uint_to_fp) conversions.
412 def VCFSX_0 : VXForm_1<842, (outs VRRC:$vD), (ins VRRC:$vB),
413 "vcfsx $vD, $vB, 0", VecFP,
415 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
416 def VCTUXS_0 : VXForm_1<906, (outs VRRC:$vD), (ins VRRC:$vB),
417 "vctuxs $vD, $vB, 0", VecFP,
419 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
420 def VCFUX_0 : VXForm_1<778, (outs VRRC:$vD), (ins VRRC:$vB),
421 "vcfux $vD, $vB, 0", VecFP,
423 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
424 def VCTSXS_0 : VXForm_1<970, (outs VRRC:$vD), (ins VRRC:$vB),
425 "vctsxs $vD, $vB, 0", VecFP,
427 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
429 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
430 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;
432 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
433 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
434 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
435 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
436 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
437 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
439 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
440 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
441 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
442 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
443 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
444 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
445 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
446 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
447 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
448 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
449 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
450 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
451 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
452 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
454 def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
455 "vmrghb $vD, $vA, $vB", VecFP,
456 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
457 def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
458 "vmrghh $vD, $vA, $vB", VecFP,
459 [(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>;
460 def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
461 "vmrghw $vD, $vA, $vB", VecFP,
462 [(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>;
463 def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
464 "vmrglb $vD, $vA, $vB", VecFP,
465 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
466 def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
467 "vmrglh $vD, $vA, $vB", VecFP,
468 [(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>;
469 def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
470 "vmrglw $vD, $vA, $vB", VecFP,
471 [(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>;
473 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
474 v4i32, v16i8, v4i32>;
475 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
476 v4i32, v8i16, v4i32>;
477 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
478 v4i32, v8i16, v4i32>;
479 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
480 v4i32, v16i8, v4i32>;
481 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
482 v4i32, v8i16, v4i32>;
483 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
484 v4i32, v8i16, v4i32>;
486 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
488 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
490 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
492 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
494 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
496 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
498 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub,
500 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
503 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>;
504 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;
505 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;
506 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;
507 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;
508 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
510 def VSUBCUW : VX1_Int_Ty<74, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
512 def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
513 "vsubfp $vD, $vA, $vB", VecGeneral,
514 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
515 def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
516 "vsububm $vD, $vA, $vB", VecGeneral,
517 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
518 def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
519 "vsubuhm $vD, $vA, $vB", VecGeneral,
520 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
521 def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
522 "vsubuwm $vD, $vA, $vB", VecGeneral,
523 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
525 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
526 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
527 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
528 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
529 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
530 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
532 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
533 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
535 def VSUM4SBS: VX1_Int_Ty3<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs,
536 v4i32, v16i8, v4i32>;
537 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
538 v4i32, v8i16, v4i32>;
539 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
540 v4i32, v16i8, v4i32>;
542 def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
543 "vnor $vD, $vA, $vB", VecFP,
544 [(set VRRC:$vD, (vnot_ppc (or (v4i32 VRRC:$vA),
546 def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
547 "vor $vD, $vA, $vB", VecFP,
548 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
549 def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
550 "vxor $vD, $vA, $vB", VecFP,
551 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
553 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
554 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
555 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
557 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;
558 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
560 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
561 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
562 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
564 def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
565 "vspltb $vD, $vB, $UIMM", VecPerm,
567 (vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
568 def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
569 "vsplth $vD, $vB, $UIMM", VecPerm,
571 (vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
572 def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
573 "vspltw $vD, $vB, $UIMM", VecPerm,
575 (vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
577 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
578 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
580 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
581 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
582 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
583 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
584 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
585 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
588 def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM),
589 "vspltisb $vD, $SIMM", VecPerm,
590 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
591 def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM),
592 "vspltish $vD, $SIMM", VecPerm,
593 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
594 def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM),
595 "vspltisw $vD, $SIMM", VecPerm,
596 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
599 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
601 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
603 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
605 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
607 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
609 def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
610 "vpkuhum $vD, $vA, $vB", VecFP,
612 (vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
613 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
615 def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
616 "vpkuwum $vD, $vA, $vB", VecFP,
618 (vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
619 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
623 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
625 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
627 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
629 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
631 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
633 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
637 // Altivec Comparisons.
639 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
640 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
641 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
642 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
643 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
644 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
649 // f32 element comparisons.0
650 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
651 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
652 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
653 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
654 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
655 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
656 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
657 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
659 // i8 element comparisons.
660 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
661 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
662 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
663 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
664 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
665 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
667 // i16 element comparisons.
668 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
669 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
670 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
671 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
672 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
673 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
675 // i32 element comparisons.
676 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
677 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
678 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
679 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
680 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
681 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
683 let isCodeGenOnly = 1 in
684 def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins),
685 "vxor $vD, $vD, $vD", VecFP,
686 [(set VRRC:$vD, (v4i32 immAllZerosV))]>;
688 def V_SETALLONES : VXForm_3<908, (outs VRRC:$vD), (ins),
689 "vspltisw $vD, -1", VecFP,
690 [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
692 } // VALU Operations.
694 //===----------------------------------------------------------------------===//
695 // Additional Altivec Patterns
699 def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>;
700 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
703 def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM),
704 (DST 0, imm:$STRM, $rA, $rB)>;
705 def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM),
706 (DSTT 1, imm:$STRM, $rA, $rB)>;
707 def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM),
708 (DSTST 0, imm:$STRM, $rA, $rB)>;
709 def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM),
710 (DSTSTT 1, imm:$STRM, $rA, $rB)>;
713 def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM),
714 (DST64 0, imm:$STRM, $rA, $rB)>;
715 def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM),
716 (DSTT64 1, imm:$STRM, $rA, $rB)>;
717 def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM),
718 (DSTST64 0, imm:$STRM, $rA, $rB)>;
719 def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM),
720 (DSTSTT64 1, imm:$STRM, $rA, $rB)>;
723 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
726 def : Pat<(store v4i32:$rS, xoaddr:$dst),
727 (STVX $rS, xoaddr:$dst)>;
730 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
731 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
732 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
734 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
735 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
736 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
738 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
739 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
740 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
742 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
743 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
744 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
748 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
749 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
750 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm VRRC:$in))>;
751 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
753 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
757 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
759 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
761 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
763 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
765 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
767 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
770 // Logical Operations
771 def : Pat<(v4i32 (vnot_ppc VRRC:$vA)), (VNOR $vA, $vA)>;
773 def : Pat<(v4i32 (vnot_ppc (or VRRC:$A, VRRC:$B))),
775 def : Pat<(v4i32 (and VRRC:$A, (vnot_ppc VRRC:$B))),
778 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
780 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>;
782 // Fused multiply add and multiply sub for packed float. These are represented
783 // separately from the real instructions above, for operations that must have
784 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
785 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
786 (VMADDFP $A, $B, $C)>;
787 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
788 (VNMSUBFP $A, $B, $C)>;
790 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
791 (VMADDFP $A, $B, $C)>;
792 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
793 (VNMSUBFP $A, $B, $C)>;
795 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
796 (VPERM $vA, $vB, $vC)>;
799 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
800 (v16i8 (VSLB $vA, $vB))>;
801 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
802 (v8i16 (VSLH $vA, $vB))>;
803 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
804 (v4i32 (VSLW $vA, $vB))>;
806 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
807 (v16i8 (VSRB $vA, $vB))>;
808 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
809 (v8i16 (VSRH $vA, $vB))>;
810 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
811 (v4i32 (VSRW $vA, $vB))>;
813 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
814 (v16i8 (VSRAB $vA, $vB))>;
815 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
816 (v8i16 (VSRAH $vA, $vB))>;
817 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
818 (v4i32 (VSRAW $vA, $vB))>;
820 // Float to integer and integer to float conversions
821 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
823 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
825 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
827 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
830 // Floating-point rounding
831 def : Pat<(v4f32 (ffloor v4f32:$vA)),
833 def : Pat<(v4f32 (fceil v4f32:$vA)),
835 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
837 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),