1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
20 def vnot_ppc : PatFrag<(ops node:$in),
21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
23 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
24 (vector_shuffle node:$lhs, node:$rhs), [{
25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false,
28 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
29 (vector_shuffle node:$lhs, node:$rhs), [{
30 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false,
33 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
34 (vector_shuffle node:$lhs, node:$rhs), [{
35 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true,
38 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
39 (vector_shuffle node:$lhs, node:$rhs), [{
40 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true,
45 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
49 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
53 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
55 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
57 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
61 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
65 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
66 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
67 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
71 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
72 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
75 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
76 (vector_shuffle node:$lhs, node:$rhs), [{
77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
79 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
80 (vector_shuffle node:$lhs, node:$rhs), [{
81 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
83 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
84 (vector_shuffle node:$lhs, node:$rhs), [{
85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
87 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
88 (vector_shuffle node:$lhs, node:$rhs), [{
89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
91 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
92 (vector_shuffle node:$lhs, node:$rhs), [{
93 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
97 // These fragments are provided for little-endian, where the inputs must be
98 // swapped for correct semantics.
99 def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
100 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
101 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
103 def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
104 (vector_shuffle node:$lhs, node:$rhs), [{
105 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
107 def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
108 (vector_shuffle node:$lhs, node:$rhs), [{
109 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
111 def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
112 (vector_shuffle node:$lhs, node:$rhs), [{
113 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
115 def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
116 (vector_shuffle node:$lhs, node:$rhs), [{
117 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
119 def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
120 (vector_shuffle node:$lhs, node:$rhs), [{
121 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
125 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
126 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false, *CurDAG));
128 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
129 (vector_shuffle node:$lhs, node:$rhs), [{
130 return PPC::isVSLDOIShuffleMask(N, false, *CurDAG) != -1;
134 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
135 /// vector_shuffle(X,undef,mask) by the dag combiner.
136 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
137 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true, *CurDAG));
139 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
140 (vector_shuffle node:$lhs, node:$rhs), [{
141 return PPC::isVSLDOIShuffleMask(N, true, *CurDAG) != -1;
142 }], VSLDOI_unary_get_imm>;
145 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
146 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
147 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG));
149 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
150 (vector_shuffle node:$lhs, node:$rhs), [{
151 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
153 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
154 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG));
156 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
157 (vector_shuffle node:$lhs, node:$rhs), [{
158 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
160 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
161 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG));
163 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
164 (vector_shuffle node:$lhs, node:$rhs), [{
165 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
169 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
170 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
171 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
173 def vecspltisb : PatLeaf<(build_vector), [{
174 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
175 }], VSPLTISB_get_imm>;
177 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
178 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
179 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
181 def vecspltish : PatLeaf<(build_vector), [{
182 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
183 }], VSPLTISH_get_imm>;
185 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
186 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
187 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
189 def vecspltisw : PatLeaf<(build_vector), [{
190 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
191 }], VSPLTISW_get_imm>;
193 //===----------------------------------------------------------------------===//
194 // Helpers for defining instructions that directly correspond to intrinsics.
196 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
197 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
198 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
199 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
200 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
202 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
203 // inputs doesn't match the type of the output.
204 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
206 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
207 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
208 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
210 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
211 // input types and an output type.
212 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
213 ValueType In1Ty, ValueType In2Ty>
214 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
215 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
217 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
219 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
220 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
221 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
222 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
223 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
225 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
226 // inputs doesn't match the type of the output.
227 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
229 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
230 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
231 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
233 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
234 // input types and an output type.
235 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
236 ValueType In1Ty, ValueType In2Ty>
237 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
238 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
239 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
241 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
242 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
243 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
244 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
245 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
247 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
248 // inputs doesn't match the type of the output.
249 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
251 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
252 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
253 [(set OutTy:$vD, (IntID InTy:$vB))]>;
255 //===----------------------------------------------------------------------===//
256 // Instruction Definitions.
258 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
259 let Predicates = [HasAltivec] in {
261 def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
262 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
263 Deprecated<DeprecatedDST> {
268 def DSSALL : DSS_Form<1, 822, (outs), (ins),
269 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
270 Deprecated<DeprecatedDST> {
276 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
277 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
278 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
279 Deprecated<DeprecatedDST>;
281 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
282 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
283 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
284 Deprecated<DeprecatedDST>;
286 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
287 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
288 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
289 Deprecated<DeprecatedDST>;
291 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
292 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
293 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
294 Deprecated<DeprecatedDST>;
296 let isCodeGenOnly = 1 in {
297 // The very same instructions as above, but formally matching 64bit registers.
298 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
299 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
300 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
301 Deprecated<DeprecatedDST>;
303 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
304 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
305 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
306 Deprecated<DeprecatedDST>;
308 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
309 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
310 [(int_ppc_altivec_dstst i64:$rA, i32:$rB,
312 Deprecated<DeprecatedDST>;
314 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
315 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
316 [(int_ppc_altivec_dststt i64:$rA, i32:$rB,
318 Deprecated<DeprecatedDST>;
321 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
322 "mfvscr $vD", IIC_LdStStore,
323 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
324 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
325 "mtvscr $vB", IIC_LdStLoad,
326 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
328 let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads.
329 def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
330 "lvebx $vD, $src", IIC_LdStLoad,
331 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
332 def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src),
333 "lvehx $vD, $src", IIC_LdStLoad,
334 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
335 def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src),
336 "lvewx $vD, $src", IIC_LdStLoad,
337 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
338 def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
339 "lvx $vD, $src", IIC_LdStLoad,
340 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
341 def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
342 "lvxl $vD, $src", IIC_LdStLoad,
343 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
346 def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src),
347 "lvsl $vD, $src", IIC_LdStLoad,
348 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
350 def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
351 "lvsr $vD, $src", IIC_LdStLoad,
352 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
355 let PPC970_Unit = 2 in { // Stores.
356 def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
357 "stvebx $rS, $dst", IIC_LdStStore,
358 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
359 def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
360 "stvehx $rS, $dst", IIC_LdStStore,
361 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
362 def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
363 "stvewx $rS, $dst", IIC_LdStStore,
364 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
365 def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
366 "stvx $rS, $dst", IIC_LdStStore,
367 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
368 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
369 "stvxl $rS, $dst", IIC_LdStStore,
370 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
373 let PPC970_Unit = 5 in { // VALU Operations.
374 // VA-Form instructions. 3-input AltiVec ops.
375 let isCommutable = 1 in {
376 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
377 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
379 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
381 // FIXME: The fma+fneg pattern won't match because fneg is not legal.
382 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
383 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
384 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
385 (fneg v4f32:$vB))))]>;
387 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
388 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
390 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
393 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
394 v4i32, v4i32, v16i8>;
395 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
398 def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
399 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
401 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
403 // VX-Form instructions. AltiVec arithmetic ops.
404 let isCommutable = 1 in {
405 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
406 "vaddfp $vD, $vA, $vB", IIC_VecFP,
407 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
409 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
410 "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
411 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
412 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
413 "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
414 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
415 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
416 "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
417 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
419 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
420 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
421 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
422 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
423 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
424 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
425 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
428 let isCommutable = 1 in
429 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
430 "vand $vD, $vA, $vB", IIC_VecFP,
431 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
432 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
433 "vandc $vD, $vA, $vB", IIC_VecFP,
434 [(set v4i32:$vD, (and v4i32:$vA,
435 (vnot_ppc v4i32:$vB)))]>;
437 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
438 "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
440 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
441 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
442 "vcfux $vD, $vB, $UIMM", IIC_VecFP,
444 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
445 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
446 "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
448 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
449 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
450 "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
452 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
454 // Defines with the UIM field set to 0 for floating-point
455 // to integer (fp_to_sint/fp_to_uint) conversions and integer
456 // to floating-point (sint_to_fp/uint_to_fp) conversions.
457 let isCodeGenOnly = 1, VA = 0 in {
458 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
459 "vcfsx $vD, $vB, 0", IIC_VecFP,
461 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
462 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
463 "vctuxs $vD, $vB, 0", IIC_VecFP,
465 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
466 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
467 "vcfux $vD, $vB, 0", IIC_VecFP,
469 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
470 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
471 "vctsxs $vD, $vB, 0", IIC_VecFP,
473 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
475 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
476 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;
478 let isCommutable = 1 in {
479 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
480 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
481 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
482 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
483 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
484 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
486 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
487 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
488 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
489 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
490 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
491 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
492 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
493 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
494 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
495 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
496 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
497 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
498 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
499 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
502 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
503 "vmrghb $vD, $vA, $vB", IIC_VecFP,
504 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
505 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
506 "vmrghh $vD, $vA, $vB", IIC_VecFP,
507 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
508 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
509 "vmrghw $vD, $vA, $vB", IIC_VecFP,
510 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
511 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
512 "vmrglb $vD, $vA, $vB", IIC_VecFP,
513 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
514 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
515 "vmrglh $vD, $vA, $vB", IIC_VecFP,
516 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
517 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
518 "vmrglw $vD, $vA, $vB", IIC_VecFP,
519 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
521 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
522 v4i32, v16i8, v4i32>;
523 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
524 v4i32, v8i16, v4i32>;
525 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
526 v4i32, v8i16, v4i32>;
527 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
528 v4i32, v16i8, v4i32>;
529 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
530 v4i32, v8i16, v4i32>;
531 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
532 v4i32, v8i16, v4i32>;
534 let isCommutable = 1 in {
535 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
537 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
539 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
541 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
543 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
545 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
547 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub,
549 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
553 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>;
554 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;
555 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;
556 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;
557 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;
558 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
560 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
562 def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
563 "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
564 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
565 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
566 "vsububm $vD, $vA, $vB", IIC_VecGeneral,
567 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
568 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
569 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
570 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
571 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
572 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
573 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
575 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
576 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
577 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
578 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
579 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
580 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
582 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
583 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
585 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
586 v4i32, v16i8, v4i32>;
587 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
588 v4i32, v8i16, v4i32>;
589 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
590 v4i32, v16i8, v4i32>;
592 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
593 "vnor $vD, $vA, $vB", IIC_VecFP,
594 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
596 let isCommutable = 1 in {
597 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
598 "vor $vD, $vA, $vB", IIC_VecFP,
599 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
600 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
601 "vxor $vD, $vA, $vB", IIC_VecFP,
602 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
605 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
606 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
607 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
609 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;
610 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
612 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
613 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
614 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
616 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
617 "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
619 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
620 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
621 "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
623 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
624 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
625 "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
627 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
629 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
630 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
632 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
633 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
634 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
635 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
636 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
637 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
640 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
641 "vspltisb $vD, $SIMM", IIC_VecPerm,
642 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
643 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
644 "vspltish $vD, $SIMM", IIC_VecPerm,
645 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
646 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
647 "vspltisw $vD, $SIMM", IIC_VecPerm,
648 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
651 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
653 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
655 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
657 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
659 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
661 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
662 "vpkuhum $vD, $vA, $vB", IIC_VecFP,
664 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
665 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
667 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
668 "vpkuwum $vD, $vA, $vB", IIC_VecFP,
670 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
671 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
675 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
677 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
679 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
681 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
683 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
685 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
689 // Altivec Comparisons.
691 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
692 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
694 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
695 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
696 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
698 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
703 // f32 element comparisons.0
704 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
705 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
706 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
707 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
708 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
709 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
710 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
711 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
713 // i8 element comparisons.
714 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
715 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
716 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
717 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
718 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
719 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
721 // i16 element comparisons.
722 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
723 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
724 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
725 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
726 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
727 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
729 // i32 element comparisons.
730 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
731 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
732 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
733 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
734 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
735 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
737 let isCodeGenOnly = 1 in {
738 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
739 "vxor $vD, $vD, $vD", IIC_VecFP,
740 [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
741 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
742 "vxor $vD, $vD, $vD", IIC_VecFP,
743 [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
744 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
745 "vxor $vD, $vD, $vD", IIC_VecFP,
746 [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
749 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
750 "vspltisw $vD, -1", IIC_VecFP,
751 [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
752 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
753 "vspltisw $vD, -1", IIC_VecFP,
754 [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
755 def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
756 "vspltisw $vD, -1", IIC_VecFP,
757 [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
760 } // VALU Operations.
762 //===----------------------------------------------------------------------===//
763 // Additional Altivec Patterns
767 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
770 def : Pat<(store v4i32:$rS, xoaddr:$dst),
771 (STVX $rS, xoaddr:$dst)>;
774 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
775 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
776 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
778 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
779 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
780 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
782 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
783 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
784 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
786 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
787 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
788 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
792 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
793 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
794 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;
795 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
797 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
801 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
803 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
805 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
807 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
809 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
811 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
814 // Match vmrg*(y,x), i.e., swapped operands. These fragments
815 // are matched for little-endian, where the inputs must be
816 // swapped for correct semantics.
817 def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
819 def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
821 def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
823 def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
825 def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
827 def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
830 // Logical Operations
831 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
833 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
835 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
838 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
840 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>;
842 // Fused multiply add and multiply sub for packed float. These are represented
843 // separately from the real instructions above, for operations that must have
844 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
845 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
846 (VMADDFP $A, $B, $C)>;
847 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
848 (VNMSUBFP $A, $B, $C)>;
850 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
851 (VMADDFP $A, $B, $C)>;
852 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
853 (VNMSUBFP $A, $B, $C)>;
855 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
856 (VPERM $vA, $vB, $vC)>;
858 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
859 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
862 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
863 (v16i8 (VSLB $vA, $vB))>;
864 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
865 (v8i16 (VSLH $vA, $vB))>;
866 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
867 (v4i32 (VSLW $vA, $vB))>;
869 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
870 (v16i8 (VSRB $vA, $vB))>;
871 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
872 (v8i16 (VSRH $vA, $vB))>;
873 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
874 (v4i32 (VSRW $vA, $vB))>;
876 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
877 (v16i8 (VSRAB $vA, $vB))>;
878 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
879 (v8i16 (VSRAH $vA, $vB))>;
880 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
881 (v4i32 (VSRAW $vA, $vB))>;
883 // Float to integer and integer to float conversions
884 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
886 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
888 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
890 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
893 // Floating-point rounding
894 def : Pat<(v4f32 (ffloor v4f32:$vA)),
896 def : Pat<(v4f32 (fceil v4f32:$vA)),
898 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
900 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),