1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
19 def VSPLT_get_imm : SDNodeXForm<build_vector, [{
20 return getI32Imm(PPC::getVSPLTImmediate(N));
23 def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isSplatShuffleMask(N);
28 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
29 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
31 PPC::isVecSplatImm(N, 1, &Val);
32 return getI32Imm(Val);
34 def vecspltisb : PatLeaf<(build_vector), [{
35 return PPC::isVecSplatImm(N, 1);
36 }], VSPLTISB_get_imm>;
38 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
39 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
41 PPC::isVecSplatImm(N, 2, &Val);
42 return getI32Imm(Val);
44 def vecspltish : PatLeaf<(build_vector), [{
45 return PPC::isVecSplatImm(N, 2);
46 }], VSPLTISH_get_imm>;
48 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
49 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
51 PPC::isVecSplatImm(N, 4, &Val);
52 return getI32Imm(Val);
54 def vecspltisw : PatLeaf<(build_vector), [{
55 return PPC::isVecSplatImm(N, 4);
56 }], VSPLTISW_get_imm>;
58 class isVDOT { // vector dot instruction.
59 list<Register> Defs = [CR6];
63 //===----------------------------------------------------------------------===//
64 // Helpers for defining instructions that directly correspond to intrinsics.
66 // VA1a_Int - A VAForm_1a intrinsic definition.
67 class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
68 : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
69 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
70 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
72 // VX1_Int - A VXForm_1 intrinsic definition.
73 class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
74 : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
75 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
76 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
78 // VX2_Int - A VXForm_2 intrinsic definition.
79 class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
80 : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
81 !strconcat(opc, " $vD, $vB"), VecFP,
82 [(set VRRC:$vD, (IntID VRRC:$vB))]>;
84 //===----------------------------------------------------------------------===//
85 // Instruction Definitions.
87 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
88 [(set VRRC:$rD, (v4f32 (undef)))]>;
90 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
91 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
92 "lvebx $vD, $src", LdStGeneral,
93 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
94 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
95 "lvehx $vD, $src", LdStGeneral,
96 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
97 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
98 "lvewx $vD, $src", LdStGeneral,
99 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
100 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
101 "lvx $vD, $src", LdStGeneral,
102 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
103 def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
104 "lvxl $vD, $src", LdStGeneral,
105 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
108 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src),
109 "lvsl $vD, $src", LdStGeneral,
110 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
112 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src),
113 "lvsl $vD, $src", LdStGeneral,
114 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
117 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
118 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
119 "stvebx $rS, $dst", LdStGeneral,
120 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
121 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
122 "stvehx $rS, $dst", LdStGeneral,
123 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
124 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
125 "stvewx $rS, $dst", LdStGeneral,
126 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
127 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
128 "stvx $rS, $dst", LdStGeneral,
129 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
130 def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
131 "stvxl $rS, $dst", LdStGeneral,
132 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
135 let PPC970_Unit = 5 in { // VALU Operations.
136 // VA-Form instructions. 3-input AltiVec ops.
137 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
138 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
139 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
141 Requires<[FPContractions]>;
142 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
143 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
144 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
146 Requires<[FPContractions]>;
147 def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
148 def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
149 def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
150 def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
152 def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
153 "vsldoi $vD, $vA, $vB, $SH", VecFP,
155 (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
158 // VX-Form instructions. AltiVec arithmetic ops.
159 def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
160 "vaddcuw $vD, $vA, $vB", VecFP,
162 (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>;
163 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
164 "vaddfp $vD, $vA, $vB", VecFP,
165 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
167 def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
168 "vaddubm $vD, $vA, $vB", VecGeneral,
169 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
170 def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
171 "vadduhm $vD, $vA, $vB", VecGeneral,
172 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
173 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
174 "vadduwm $vD, $vA, $vB", VecGeneral,
175 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
177 def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
178 "vaddsbs $vD, $vA, $vB", VecFP,
180 (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>;
181 def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
182 "vaddshs $vD, $vA, $vB", VecFP,
184 (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>;
185 def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
186 "vaddsws $vD, $vA, $vB", VecFP,
188 (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>;
190 def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
191 "vaddubs $vD, $vA, $vB", VecFP,
193 (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>;
194 def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
195 "vadduhs $vD, $vA, $vB", VecFP,
197 (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>;
198 def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
199 "vadduws $vD, $vA, $vB", VecFP,
201 (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>;
202 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
203 "vand $vD, $vA, $vB", VecFP,
204 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
205 def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
206 "vandc $vD, $vA, $vB", VecFP,
207 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
209 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
210 "vcfsx $vD, $vB, $UIMM", VecFP,
212 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
213 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
214 "vcfux $vD, $vB, $UIMM", VecFP,
216 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
217 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
218 "vctsxs $vD, $vB, $UIMM", VecFP,
220 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
221 "vctuxs $vD, $vB, $UIMM", VecFP,
223 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
224 "vexptefp $vD, $vB", VecFP,
225 [(set VRRC:$vD, (int_ppc_altivec_vexptefp VRRC:$vB))]>;
226 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
227 "vlogefp $vD, $vB", VecFP,
228 [(set VRRC:$vD, (int_ppc_altivec_vlogefp VRRC:$vB))]>;
229 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
230 "vmaxfp $vD, $vA, $vB", VecFP,
232 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
233 "vminfp $vD, $vA, $vB", VecFP,
236 def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>;
237 def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>;
238 def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>;
239 def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>;
241 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
242 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
243 def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
244 def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
245 def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
246 def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
248 def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
249 def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
250 def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
251 def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
252 def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
253 def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
254 def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
255 def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
257 def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
258 def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
259 def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
260 def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
261 def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
262 def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
264 def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
266 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
267 "vsubfp $vD, $vA, $vB", VecGeneral,
268 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
269 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
270 "vsububm $vD, $vA, $vB", VecGeneral,
271 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
272 def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
273 "vsubuhm $vD, $vA, $vB", VecGeneral,
274 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
275 def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
276 "vsubuwm $vD, $vA, $vB", VecGeneral,
277 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
279 def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
280 def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
281 def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
282 def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
283 def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
284 def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
285 def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
286 def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
287 def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
288 def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
289 def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
291 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
292 "vnor $vD, $vA, $vB", VecFP,
293 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
294 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
295 "vor $vD, $vA, $vB", VecFP,
296 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
297 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
298 "vxor $vD, $vA, $vB", VecFP,
299 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
301 def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
302 def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
303 def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
304 def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
305 def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
306 def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
307 def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
309 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
310 "vspltb $vD, $vB, $UIMM", VecPerm,
312 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
313 "vsplth $vD, $vB, $UIMM", VecPerm,
315 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
316 "vspltw $vD, $vB, $UIMM", VecPerm,
317 [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
318 VSPLT_shuffle_mask:$UIMM))]>;
320 def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
321 def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
322 def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
323 def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
324 def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
325 def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
326 def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
327 def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
330 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
331 "vspltisb $vD, $SIMM", VecPerm,
332 [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
333 def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
334 "vspltish $vD, $SIMM", VecPerm,
335 [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
336 def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
337 "vspltisw $vD, $SIMM", VecPerm,
338 [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
341 def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
342 def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
343 def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
344 def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
345 def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
346 def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
347 "vpkuhum $vD, $vA, $vB", VecFP,
349 def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
350 def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
351 "vpkuwum $vD, $vA, $vB", VecFP,
353 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
356 def VUPKHPX : VXForm_2<846, (ops VRRC:$vD, VRRC:$vB),
357 "vupkhpx $vD, $vB", VecFP,
358 [(set VRRC:$vD, (int_ppc_altivec_vupkhpx VRRC:$vB))]>;
359 def VUPKHSB : VXForm_2<526, (ops VRRC:$vD, VRRC:$vB),
360 "vupkhsb $vD, $vB", VecFP,
361 [(set VRRC:$vD, (int_ppc_altivec_vupkhsb VRRC:$vB))]>;
362 def VUPKHSH : VXForm_2<590, (ops VRRC:$vD, VRRC:$vB),
363 "vupkhsh $vD, $vB", VecFP,
364 [(set VRRC:$vD, (int_ppc_altivec_vupkhsh VRRC:$vB))]>;
365 def VUPKLPX : VXForm_2<974, (ops VRRC:$vD, VRRC:$vB),
366 "vupklpx $vD, $vB", VecFP,
367 [(set VRRC:$vD, (int_ppc_altivec_vupklpx VRRC:$vB))]>;
368 def VUPKLSB : VXForm_2<654, (ops VRRC:$vD, VRRC:$vB),
369 "vupklsb $vD, $vB", VecFP,
370 [(set VRRC:$vD, (int_ppc_altivec_vupklsb VRRC:$vB))]>;
371 def VUPKLSH : VXForm_2<718, (ops VRRC:$vD, VRRC:$vB),
372 "vupklsh $vD, $vB", VecFP,
373 [(set VRRC:$vD, (int_ppc_altivec_vupklsh VRRC:$vB))]>;
376 // Altivec Comparisons.
378 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
379 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
380 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
381 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
382 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
383 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]>,isVDOT;
385 // f32 element comparisons.0
386 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
387 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
388 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
389 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
390 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
391 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
392 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
393 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
395 // i8 element comparisons.
396 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
397 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
398 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
399 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
400 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
401 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
403 // i16 element comparisons.
404 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
405 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
406 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
407 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
408 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
409 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
411 // i32 element comparisons.
412 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
413 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
414 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
415 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
416 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
417 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
419 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
420 "vxor $vD, $vD, $vD", VecFP,
421 [(set VRRC:$vD, (v4f32 immAllZerosV))]>;
424 //===----------------------------------------------------------------------===//
425 // Additional Altivec Patterns
429 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
430 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
431 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
432 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
433 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
434 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
437 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
438 def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
439 def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
440 def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
443 def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
444 (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
445 def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
446 (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
447 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
448 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
449 def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
450 (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
453 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
454 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
455 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
457 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
458 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
459 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
461 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
462 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
463 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
465 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
466 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
467 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
469 // Immediate vector formation with vsplti*.
470 def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
471 def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
472 def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
474 def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
475 def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
476 def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
478 def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
479 def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
480 def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
482 // Logical Operations
483 def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
484 def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
485 def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
486 def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
487 def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
488 def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
489 def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
490 def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
491 def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
492 (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
493 def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
494 (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
496 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
497 (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
499 // Fused multiply add and multiply sub for packed float. These are represented
500 // separately from the real instructions above, for operations that must have
501 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
502 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
503 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
504 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
505 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
507 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
508 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
509 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
510 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
511 def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
512 (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
514 def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
515 (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
516 def : Pat<(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
517 (v4f32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
518 def : Pat<(PPCvperm (v8i16 VRRC:$vA), VRRC:$vB, VRRC:$vC),
519 (v8i16 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
520 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
521 (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;