1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
19 def VSPLT_get_imm : SDNodeXForm<build_vector, [{
20 return getI32Imm(PPC::getVSPLTImmediate(N));
23 def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isSplatShuffleMask(N);
28 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
29 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
31 PPC::isVecSplatImm(N, 1, &Val);
32 return getI32Imm(Val);
34 def vecspltisb : PatLeaf<(build_vector), [{
35 return PPC::isVecSplatImm(N, 1);
36 }], VSPLTISB_get_imm>;
38 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
39 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
41 PPC::isVecSplatImm(N, 2, &Val);
42 return getI32Imm(Val);
44 def vecspltish : PatLeaf<(build_vector), [{
45 return PPC::isVecSplatImm(N, 2);
46 }], VSPLTISH_get_imm>;
48 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
49 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
51 PPC::isVecSplatImm(N, 4, &Val);
52 return getI32Imm(Val);
54 def vecspltisw : PatLeaf<(build_vector), [{
55 return PPC::isVecSplatImm(N, 4);
56 }], VSPLTISW_get_imm>;
58 class isVDOT { // vector dot instruction.
59 list<Register> Defs = [CR6];
63 //===----------------------------------------------------------------------===//
64 // Helpers for defining instructions that directly correspond to intrinsics.
66 // VA1a_Int - A VAForm_1a intrinsic definition.
67 class VA1a_Int<bits<6> xo, string asmstr, Intrinsic IntID>
68 : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), asmstr, VecFP,
69 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
71 // VX1_Int - A VXForm_1 intrinsic definition.
72 class VX1_Int<bits<11> xo, string asmstr, Intrinsic IntID>
73 : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFP,
74 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
76 // VX2_Int - A VXForm_2 intrinsic definition.
77 class VX2_Int<bits<11> xo, string asmstr, Intrinsic IntID>
78 : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB), asmstr, VecFP,
79 [(set VRRC:$vD, (IntID VRRC:$vB))]>;
81 //===----------------------------------------------------------------------===//
82 // Instruction Definitions.
84 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
85 [(set VRRC:$rD, (v4f32 (undef)))]>;
87 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
88 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
89 "lvebx $vD, $src", LdStGeneral,
90 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
91 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
92 "lvehx $vD, $src", LdStGeneral,
93 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
94 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
95 "lvewx $vD, $src", LdStGeneral,
96 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
97 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
98 "lvx $vD, $src", LdStGeneral,
99 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
100 def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
101 "lvxl $vD, $src", LdStGeneral,
102 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
105 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src),
106 "lvsl $vD, $src", LdStGeneral,
107 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
109 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src),
110 "lvsl $vD, $src", LdStGeneral,
111 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
114 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
115 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
116 "stvebx $rS, $dst", LdStGeneral,
117 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
118 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
119 "stvehx $rS, $dst", LdStGeneral,
120 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
121 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
122 "stvewx $rS, $dst", LdStGeneral,
123 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
124 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
125 "stvx $rS, $dst", LdStGeneral,
126 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
127 def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
128 "stvxl $rS, $dst", LdStGeneral,
129 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
132 let PPC970_Unit = 5 in { // VALU Operations.
133 // VA-Form instructions. 3-input AltiVec ops.
134 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
135 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
136 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
138 Requires<[FPContractions]>;
139 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
140 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
141 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
143 Requires<[FPContractions]>;
144 def VMHADDSHS : VAForm_1a<32, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
145 "vmhaddshs $vD, $vA, $vB, $vC", VecFP,
147 (int_ppc_altivec_vmhaddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
148 def VMHRADDSHS : VAForm_1a<33, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
149 "vmhraddshs $vD, $vA, $vB, $vC", VecFP,
151 (int_ppc_altivec_vmhraddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
152 def VPERM : VAForm_1a<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
153 "vperm $vD, $vA, $vB, $vC", VecPerm,
155 (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
156 def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
157 "vsldoi $vD, $vA, $vB, $SH", VecFP,
159 (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
161 def VSEL : VAForm_1a<42, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
162 "vsel $vD, $vA, $vB, $vC", VecFP,
164 (int_ppc_altivec_vsel VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
166 // VX-Form instructions. AltiVec arithmetic ops.
167 def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
168 "vaddcuw $vD, $vA, $vB", VecFP,
170 (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>;
171 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
172 "vaddfp $vD, $vA, $vB", VecFP,
173 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
175 def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
176 "vaddubm $vD, $vA, $vB", VecGeneral,
177 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
178 def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
179 "vadduhm $vD, $vA, $vB", VecGeneral,
180 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
181 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
182 "vadduwm $vD, $vA, $vB", VecGeneral,
183 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
185 def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
186 "vaddsbs $vD, $vA, $vB", VecFP,
188 (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>;
189 def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
190 "vaddshs $vD, $vA, $vB", VecFP,
192 (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>;
193 def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
194 "vaddsws $vD, $vA, $vB", VecFP,
196 (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>;
198 def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
199 "vaddubs $vD, $vA, $vB", VecFP,
201 (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>;
202 def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
203 "vadduhs $vD, $vA, $vB", VecFP,
205 (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>;
206 def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
207 "vadduws $vD, $vA, $vB", VecFP,
209 (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>;
210 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
211 "vand $vD, $vA, $vB", VecFP,
212 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
213 def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
214 "vandc $vD, $vA, $vB", VecFP,
215 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
217 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
218 "vcfsx $vD, $vB, $UIMM", VecFP,
220 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
221 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
222 "vcfux $vD, $vB, $UIMM", VecFP,
224 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
225 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
226 "vctsxs $vD, $vB, $UIMM", VecFP,
228 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
229 "vctuxs $vD, $vB, $UIMM", VecFP,
231 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
232 "vexptefp $vD, $vB", VecFP,
233 [(set VRRC:$vD, (int_ppc_altivec_vexptefp VRRC:$vB))]>;
234 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
235 "vlogefp $vD, $vB", VecFP,
236 [(set VRRC:$vD, (int_ppc_altivec_vlogefp VRRC:$vB))]>;
237 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
238 "vmaxfp $vD, $vA, $vB", VecFP,
240 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
241 "vminfp $vD, $vA, $vB", VecFP,
244 def VMRGHH : VX1_Int<76 , "vmrghh $vD, $vA, $vB", int_ppc_altivec_vmrghh>;
245 def VMRGHW : VX1_Int<140, "vmrghw $vD, $vA, $vB", int_ppc_altivec_vmrghw>;
246 def VMRGLH : VX1_Int<332, "vmrglh $vD, $vA, $vB", int_ppc_altivec_vmrglh>;
247 def VMRGLW : VX1_Int<396, "vmrglw $vD, $vA, $vB", int_ppc_altivec_vmrglw>;
249 def VMSUMMBM : VA1a_Int<37, "vmsummbm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsummbm>;
250 def VMSUMSHM : VA1a_Int<40, "vmsumshm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumshm>;
251 def VMSUMSHS : VA1a_Int<41, "vmsumshs $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumshs>;
252 def VMSUMUBM : VA1a_Int<36, "vmsumubm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumubm>;
253 def VMSUMUHM : VA1a_Int<38, "vmsumuhm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumuhm>;
254 def VMSUMUHS : VA1a_Int<39, "vmsumuhs $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumuhs>;
256 def VMULESB : VX1_Int<776, "vmulesb $vD, $vA, $vB", int_ppc_altivec_vmulesb>;
257 def VMULESH : VX1_Int<840, "vmulesh $vD, $vA, $vB", int_ppc_altivec_vmulesh>;
258 def VMULEUB : VX1_Int<520, "vmuleub $vD, $vA, $vB", int_ppc_altivec_vmuleub>;
259 def VMULEUH : VX1_Int<584, "vmuleuh $vD, $vA, $vB", int_ppc_altivec_vmuleuh>;
260 def VMULOSB : VX1_Int<264, "vmulosb $vD, $vA, $vB", int_ppc_altivec_vmulosb>;
261 def VMULOSH : VX1_Int<328, "vmulosh $vD, $vA, $vB", int_ppc_altivec_vmulosh>;
262 def VMULOUB : VX1_Int< 8, "vmuloub $vD, $vA, $vB", int_ppc_altivec_vmuloub>;
263 def VMULOUH : VX1_Int< 72, "vmulouh $vD, $vA, $vB", int_ppc_altivec_vmulouh>;
265 def VREFP : VX2_Int<266, "vrefp $vD, $vB", int_ppc_altivec_vrefp>;
266 def VRFIM : VX2_Int<714, "vrfim $vD, $vB", int_ppc_altivec_vrfim>;
267 def VRFIN : VX2_Int<522, "vrfin $vD, $vB", int_ppc_altivec_vrfin>;
268 def VRFIP : VX2_Int<650, "vrfip $vD, $vB", int_ppc_altivec_vrfip>;
269 def VRFIZ : VX2_Int<586, "vrfiz $vD, $vB", int_ppc_altivec_vrfiz>;
270 def VRSQRTEFP : VX2_Int<330, "vrsqrtefp $vD, $vB", int_ppc_altivec_vrsqrtefp>;
272 def VSUBCUW : VX1_Int<74, "vsubcuw $vD, $vA, $vB", int_ppc_altivec_vsubcuw>;
274 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
275 "vsubfp $vD, $vA, $vB", VecGeneral,
276 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
277 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
278 "vsububm $vD, $vA, $vB", VecGeneral,
279 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
280 def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
281 "vsubuhm $vD, $vA, $vB", VecGeneral,
282 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
283 def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
284 "vsubuwm $vD, $vA, $vB", VecGeneral,
285 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
287 def VSUBSBS : VX1_Int<1792, "vsubsbs $vD, $vA, $vB", int_ppc_altivec_vsubsbs>;
288 def VSUBSHS : VX1_Int<1856, "vsubshs $vD, $vA, $vB", int_ppc_altivec_vsubshs>;
289 def VSUBSWS : VX1_Int<1920, "vsubsws $vD, $vA, $vB", int_ppc_altivec_vsubsws>;
290 def VSUBUBS : VX1_Int<1536, "vsububs $vD, $vA, $vB", int_ppc_altivec_vsububs>;
291 def VSUBUHS : VX1_Int<1600, "vsubuhs $vD, $vA, $vB", int_ppc_altivec_vsubuhs>;
292 def VSUBUWS : VX1_Int<1664, "vsubuws $vD, $vA, $vB", int_ppc_altivec_vsubuws>;
293 def VSUMSWS : VX1_Int<1928, "vsumsws $vD, $vA, $vB", int_ppc_altivec_vsumsws>;
294 def VSUM2SWS: VX1_Int<1672, "vsum2sws $vD, $vA, $vB", int_ppc_altivec_vsum2sws>;
295 def VSUM4SBS: VX1_Int<1672, "vsum4sbs $vD, $vA, $vB", int_ppc_altivec_vsum4sbs>;
296 def VSUM4SHS: VX1_Int<1608, "vsum4shs $vD, $vA, $vB", int_ppc_altivec_vsum4shs>;
297 def VSUM4UBS: VX1_Int<1544, "vsum4ubs $vD, $vA, $vB", int_ppc_altivec_vsum4ubs>;
299 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
300 "vnor $vD, $vA, $vB", VecFP,
301 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
302 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
303 "vor $vD, $vA, $vB", VecFP,
304 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
305 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
306 "vxor $vD, $vA, $vB", VecFP,
307 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
309 def VRLB : VX1_Int< 4, "vrlb $vD, $vA, $vB", int_ppc_altivec_vrlb>;
310 def VRLH : VX1_Int< 68, "vrlh $vD, $vA, $vB", int_ppc_altivec_vrlh>;
311 def VRLW : VX1_Int< 132, "vrlw $vD, $vA, $vB", int_ppc_altivec_vrlw>;
312 def VSLO : VX1_Int<1036, "vslo $vD, $vA, $vB", int_ppc_altivec_vslo>;
313 def VSLB : VX1_Int< 260, "vslb $vD, $vA, $vB", int_ppc_altivec_vslb>;
314 def VSLH : VX1_Int< 324, "vslh $vD, $vA, $vB", int_ppc_altivec_vslh>;
315 def VSLW : VX1_Int< 388, "vslw $vD, $vA, $vB", int_ppc_altivec_vslw>;
317 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
318 "vspltb $vD, $vB, $UIMM", VecPerm,
320 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
321 "vsplth $vD, $vB, $UIMM", VecPerm,
323 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
324 "vspltw $vD, $vB, $UIMM", VecPerm,
325 [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
326 VSPLT_shuffle_mask:$UIMM))]>;
328 def VSR : VX1_Int< 708, "vsr $vD, $vA, $vB" , int_ppc_altivec_vsr>;
329 def VSRO : VX1_Int<1100, "vsro $vD, $vA, $vB" , int_ppc_altivec_vsro>;
330 def VSRAB : VX1_Int< 772, "vsrab $vD, $vA, $vB", int_ppc_altivec_vsrab>;
331 def VSRAH : VX1_Int< 836, "vsrah $vD, $vA, $vB", int_ppc_altivec_vsrah>;
332 def VSRAW : VX1_Int< 900, "vsraw $vD, $vA, $vB", int_ppc_altivec_vsraw>;
333 def VSRB : VX1_Int< 516, "vsrb $vD, $vA, $vB" , int_ppc_altivec_vsrb>;
334 def VSRH : VX1_Int< 580, "vsrh $vD, $vA, $vB" , int_ppc_altivec_vsrh>;
335 def VSRW : VX1_Int< 644, "vsrw $vD, $vA, $vB" , int_ppc_altivec_vsrw>;
338 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
339 "vspltisb $vD, $SIMM", VecPerm,
340 [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
341 def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
342 "vspltish $vD, $SIMM", VecPerm,
343 [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
344 def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
345 "vspltisw $vD, $SIMM", VecPerm,
346 [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
349 def VPKPX : VXForm_1<782, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
350 "vpkpx $vD, $vA, $vB", VecFP,
352 (int_ppc_altivec_vpkpx VRRC:$vA, VRRC:$vB))]>;
353 def VPKSHSS : VXForm_1<398, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
354 "vpkshss $vD, $vA, $vB", VecFP,
356 (int_ppc_altivec_vpkshss VRRC:$vA, VRRC:$vB))]>;
357 def VPKSHUS : VXForm_1<270, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
358 "vpkshus $vD, $vA, $vB", VecFP,
360 (int_ppc_altivec_vpkshus VRRC:$vA, VRRC:$vB))]>;
361 def VPKSWSS : VXForm_1<462, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
362 "vpkswss $vD, $vA, $vB", VecFP,
364 (int_ppc_altivec_vpkswss VRRC:$vA, VRRC:$vB))]>;
365 def VPKSWUS : VXForm_1<334, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
366 "vpkswus $vD, $vA, $vB", VecFP,
368 (int_ppc_altivec_vpkswus VRRC:$vA, VRRC:$vB))]>;
369 def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
370 "vpkuhum $vD, $vA, $vB", VecFP,
372 def VPKUHUS : VXForm_1<142, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
373 "vpkuhus $vD, $vA, $vB", VecFP,
375 (int_ppc_altivec_vpkuhus VRRC:$vA, VRRC:$vB))]>;
376 def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
377 "vpkuwum $vD, $vA, $vB", VecFP,
379 def VPKUWUS : VXForm_1<206, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
380 "vpkuwus $vD, $vA, $vB", VecFP,
382 (int_ppc_altivec_vpkuwus VRRC:$vA, VRRC:$vB))]>;
385 def VUPKHPX : VXForm_2<846, (ops VRRC:$vD, VRRC:$vB),
386 "vupkhpx $vD, $vB", VecFP,
387 [(set VRRC:$vD, (int_ppc_altivec_vupkhpx VRRC:$vB))]>;
388 def VUPKHSB : VXForm_2<526, (ops VRRC:$vD, VRRC:$vB),
389 "vupkhsb $vD, $vB", VecFP,
390 [(set VRRC:$vD, (int_ppc_altivec_vupkhsb VRRC:$vB))]>;
391 def VUPKHSH : VXForm_2<590, (ops VRRC:$vD, VRRC:$vB),
392 "vupkhsh $vD, $vB", VecFP,
393 [(set VRRC:$vD, (int_ppc_altivec_vupkhsh VRRC:$vB))]>;
394 def VUPKLPX : VXForm_2<974, (ops VRRC:$vD, VRRC:$vB),
395 "vupklpx $vD, $vB", VecFP,
396 [(set VRRC:$vD, (int_ppc_altivec_vupklpx VRRC:$vB))]>;
397 def VUPKLSB : VXForm_2<654, (ops VRRC:$vD, VRRC:$vB),
398 "vupklsb $vD, $vB", VecFP,
399 [(set VRRC:$vD, (int_ppc_altivec_vupklsb VRRC:$vB))]>;
400 def VUPKLSH : VXForm_2<718, (ops VRRC:$vD, VRRC:$vB),
401 "vupklsh $vD, $vB", VecFP,
402 [(set VRRC:$vD, (int_ppc_altivec_vupklsh VRRC:$vB))]>;
405 // Altivec Comparisons.
407 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
408 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
409 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
410 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
411 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
412 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]>,isVDOT;
414 // f32 element comparisons.0
415 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
416 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
417 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
418 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
419 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
420 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
421 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
422 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
424 // i8 element comparisons.
425 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
426 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
427 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
428 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
429 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
430 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
432 // i16 element comparisons.
433 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
434 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
435 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
436 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
437 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
438 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
440 // i32 element comparisons.
441 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
442 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
443 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
444 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
445 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
446 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
448 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
449 "vxor $vD, $vD, $vD", VecFP,
450 [(set VRRC:$vD, (v4f32 immAllZerosV))]>;
453 //===----------------------------------------------------------------------===//
454 // Additional Altivec Patterns
458 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
459 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
460 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
461 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
462 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
463 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
466 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
467 def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
468 def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
469 def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
472 def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
473 (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
474 def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
475 (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
476 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
477 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
478 def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
479 (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
482 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
483 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
484 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
486 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
487 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
488 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
490 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
491 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
492 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
494 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
495 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
496 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
498 // Immediate vector formation with vsplti*.
499 def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
500 def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
501 def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
503 def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
504 def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
505 def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
507 def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
508 def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
509 def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
511 // Logical Operations
512 def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
513 def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
514 def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
515 def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
516 def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
517 def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
518 def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
519 def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
520 def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
521 (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
522 def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
523 (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
525 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
526 (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
528 // Fused multiply add and multiply sub for packed float. These are represented
529 // separately from the real instructions above, for operations that must have
530 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
531 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
532 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
533 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
534 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
536 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
537 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
538 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
539 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
540 def : Pat<(int_ppc_altivec_vperm VRRC:$A, VRRC:$B, VRRC:$C),
541 (VPERM VRRC:$A, VRRC:$B, VRRC:$C)>;
542 def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
543 (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
545 def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
546 (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;