1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
388 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
390 : I<opcode, OOL, IOL, asmstr, itin> {
391 let Inst{21-30} = xo;
394 // This is the same as XForm_base_r3xo, but the first two operands are swapped
395 // when code is emitted.
396 class XForm_base_r3xo_swapped
397 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
399 : I<opcode, OOL, IOL, asmstr, itin> {
404 bit RC = 0; // set by isDOT
406 let Inst{6-10} = RST;
409 let Inst{21-30} = xo;
414 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
415 InstrItinClass itin, list<dag> pattern>
416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
418 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
419 InstrItinClass itin, list<dag> pattern>
420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
424 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
425 InstrItinClass itin, list<dag> pattern>
426 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
431 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
432 InstrItinClass itin, list<dag> pattern>
433 : I<opcode, OOL, IOL, asmstr, itin> {
438 let Pattern = pattern;
440 let Inst{6-10} = RST;
443 let Inst{21-30} = xo;
447 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
448 InstrItinClass itin, list<dag> pattern>
449 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
450 let Pattern = pattern;
453 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
454 InstrItinClass itin, list<dag> pattern>
455 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
457 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
458 InstrItinClass itin, list<dag> pattern>
459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
460 let Pattern = pattern;
463 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
464 InstrItinClass itin, list<dag> pattern>
465 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
467 let Pattern = pattern;
470 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
472 : I<opcode, OOL, IOL, asmstr, itin> {
481 let Inst{11-15} = RA;
482 let Inst{16-20} = RB;
483 let Inst{21-30} = xo;
487 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
489 : I<opcode, OOL, IOL, asmstr, itin> {
496 let Inst{11-15} = RA;
497 let Inst{16-20} = RB;
498 let Inst{21-30} = xo;
502 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
504 : I<opcode, OOL, IOL, asmstr, itin> {
509 let Inst{12-15} = SR;
510 let Inst{21-30} = xo;
513 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
515 : I<opcode, OOL, IOL, asmstr, itin> {
519 let Inst{21-30} = xo;
522 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
524 : I<opcode, OOL, IOL, asmstr, itin> {
529 let Inst{16-20} = RB;
530 let Inst{21-30} = xo;
533 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
535 : I<opcode, OOL, IOL, asmstr, itin> {
541 let Inst{21-30} = xo;
544 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
546 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
550 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
552 : I<opcode, OOL, IOL, asmstr, itin> {
559 let Inst{11-15} = FRA;
560 let Inst{16-20} = FRB;
561 let Inst{21-30} = xo;
565 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
566 InstrItinClass itin, list<dag> pattern>
567 : I<opcode, OOL, IOL, asmstr, itin> {
568 let Pattern = pattern;
572 let Inst{21-30} = xo;
576 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
577 string asmstr, InstrItinClass itin, list<dag> pattern>
578 : I<opcode, OOL, IOL, asmstr, itin> {
581 let Pattern = pattern;
586 let Inst{21-30} = xo;
590 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
591 string asmstr, InstrItinClass itin, list<dag> pattern>
592 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
596 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
597 InstrItinClass itin, list<dag> pattern>
598 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
601 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
602 InstrItinClass itin, list<dag> pattern>
603 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
607 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
608 InstrItinClass itin, list<dag> pattern>
609 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
612 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
613 // numbers presumably relates to some document, but I haven't found it.
614 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
615 InstrItinClass itin, list<dag> pattern>
616 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
617 let Pattern = pattern;
619 bit RC = 0; // set by isDOT
621 let Inst{6-10} = RST;
623 let Inst{21-30} = xo;
626 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
627 InstrItinClass itin, list<dag> pattern>
628 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
629 let Pattern = pattern;
632 bit RC = 0; // set by isDOT
636 let Inst{21-30} = xo;
640 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
641 InstrItinClass itin, list<dag> pattern>
642 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
648 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
649 InstrItinClass itin, list<dag> pattern>
650 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
656 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
657 InstrItinClass itin, list<dag> pattern>
658 : I<opcode, OOL, IOL, asmstr, itin> {
663 let Pattern = pattern;
665 let Inst{6-10} = XT{4-0};
668 let Inst{21-30} = xo;
669 let Inst{31} = XT{5};
672 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
673 InstrItinClass itin, list<dag> pattern>
674 : I<opcode, OOL, IOL, asmstr, itin> {
678 let Pattern = pattern;
680 let Inst{6-10} = XT{4-0};
682 let Inst{16-20} = XB{4-0};
683 let Inst{21-29} = xo;
684 let Inst{30} = XB{5};
685 let Inst{31} = XT{5};
688 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
689 InstrItinClass itin, list<dag> pattern>
690 : I<opcode, OOL, IOL, asmstr, itin> {
694 let Pattern = pattern;
698 let Inst{16-20} = XB{4-0};
699 let Inst{21-29} = xo;
700 let Inst{30} = XB{5};
704 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
705 InstrItinClass itin, list<dag> pattern>
706 : I<opcode, OOL, IOL, asmstr, itin> {
711 let Pattern = pattern;
713 let Inst{6-10} = XT{4-0};
716 let Inst{16-20} = XB{4-0};
717 let Inst{21-29} = xo;
718 let Inst{30} = XB{5};
719 let Inst{31} = XT{5};
722 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
723 InstrItinClass itin, list<dag> pattern>
724 : I<opcode, OOL, IOL, asmstr, itin> {
729 let Pattern = pattern;
731 let Inst{6-10} = XT{4-0};
732 let Inst{11-15} = XA{4-0};
733 let Inst{16-20} = XB{4-0};
734 let Inst{21-28} = xo;
735 let Inst{29} = XA{5};
736 let Inst{30} = XB{5};
737 let Inst{31} = XT{5};
740 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
741 InstrItinClass itin, list<dag> pattern>
742 : I<opcode, OOL, IOL, asmstr, itin> {
747 let Pattern = pattern;
751 let Inst{11-15} = XA{4-0};
752 let Inst{16-20} = XB{4-0};
753 let Inst{21-28} = xo;
754 let Inst{29} = XA{5};
755 let Inst{30} = XB{5};
759 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
760 InstrItinClass itin, list<dag> pattern>
761 : I<opcode, OOL, IOL, asmstr, itin> {
767 let Pattern = pattern;
769 let Inst{6-10} = XT{4-0};
770 let Inst{11-15} = XA{4-0};
771 let Inst{16-20} = XB{4-0};
774 let Inst{24-28} = xo;
775 let Inst{29} = XA{5};
776 let Inst{30} = XB{5};
777 let Inst{31} = XT{5};
780 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
781 InstrItinClass itin, list<dag> pattern>
782 : I<opcode, OOL, IOL, asmstr, itin> {
787 let Pattern = pattern;
789 bit RC = 0; // set by isDOT
791 let Inst{6-10} = XT{4-0};
792 let Inst{11-15} = XA{4-0};
793 let Inst{16-20} = XB{4-0};
795 let Inst{22-28} = xo;
796 let Inst{29} = XA{5};
797 let Inst{30} = XB{5};
798 let Inst{31} = XT{5};
801 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
802 InstrItinClass itin, list<dag> pattern>
803 : I<opcode, OOL, IOL, asmstr, itin> {
809 let Pattern = pattern;
811 let Inst{6-10} = XT{4-0};
812 let Inst{11-15} = XA{4-0};
813 let Inst{16-20} = XB{4-0};
814 let Inst{21-25} = XC{4-0};
815 let Inst{26-27} = xo;
816 let Inst{28} = XC{5};
817 let Inst{29} = XA{5};
818 let Inst{30} = XB{5};
819 let Inst{31} = XT{5};
822 // DCB_Form - Form X instruction, used for dcb* instructions.
823 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
824 InstrItinClass itin, list<dag> pattern>
825 : I<31, OOL, IOL, asmstr, itin> {
829 let Pattern = pattern;
831 let Inst{6-10} = immfield;
834 let Inst{21-30} = xo;
839 // DSS_Form - Form X instruction, used for altivec dss* instructions.
840 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
841 InstrItinClass itin, list<dag> pattern>
842 : I<31, OOL, IOL, asmstr, itin> {
847 let Pattern = pattern;
851 let Inst{9-10} = STRM;
854 let Inst{21-30} = xo;
859 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
860 InstrItinClass itin, list<dag> pattern>
861 : I<opcode, OOL, IOL, asmstr, itin> {
866 let Pattern = pattern;
868 let Inst{6-10} = CRD;
869 let Inst{11-15} = CRA;
870 let Inst{16-20} = CRB;
871 let Inst{21-30} = xo;
875 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
876 InstrItinClass itin, list<dag> pattern>
877 : I<opcode, OOL, IOL, asmstr, itin> {
880 let Pattern = pattern;
882 let Inst{6-10} = CRD;
883 let Inst{11-15} = CRD;
884 let Inst{16-20} = CRD;
885 let Inst{21-30} = xo;
889 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
890 InstrItinClass itin, list<dag> pattern>
891 : I<opcode, OOL, IOL, asmstr, itin> {
896 let Pattern = pattern;
899 let Inst{11-15} = BI;
901 let Inst{19-20} = BH;
902 let Inst{21-30} = xo;
906 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
907 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
908 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
909 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
913 let BI{0-1} = BIBO{5-6};
914 let BI{2-4} = CR{0-2};
918 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
919 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
920 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
925 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
926 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
927 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
933 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
935 : I<opcode, OOL, IOL, asmstr, itin> {
941 let Inst{11-13} = BFA;
944 let Inst{21-30} = xo;
948 class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
950 : I<opcode, OOL, IOL, asmstr, itin> {
963 let Inst{21-30} = xo;
967 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
968 bits<6> opcode2, bits<2> xo2,
969 dag OOL, dag IOL, string asmstr,
970 InstrItinClass itin, list<dag> pattern>
971 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
979 let Pattern = pattern;
982 let Inst{11-15} = BI;
984 let Inst{19-20} = BH;
985 let Inst{21-30} = xo1;
988 let Inst{38-42} = RST;
989 let Inst{43-47} = DS_RA{18-14}; // Register #
990 let Inst{48-61} = DS_RA{13-0}; // Displacement.
991 let Inst{62-63} = xo2;
994 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
995 bits<5> bo, bits<5> bi, bit lk,
996 bits<6> opcode2, bits<2> xo2,
997 dag OOL, dag IOL, string asmstr,
998 InstrItinClass itin, list<dag> pattern>
999 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1000 OOL, IOL, asmstr, itin, pattern> {
1007 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1008 InstrItinClass itin>
1009 : I<opcode, OOL, IOL, asmstr, itin> {
1013 let Inst{6-10} = RT;
1014 let Inst{11} = SPR{4};
1015 let Inst{12} = SPR{3};
1016 let Inst{13} = SPR{2};
1017 let Inst{14} = SPR{1};
1018 let Inst{15} = SPR{0};
1019 let Inst{16} = SPR{9};
1020 let Inst{17} = SPR{8};
1021 let Inst{18} = SPR{7};
1022 let Inst{19} = SPR{6};
1023 let Inst{20} = SPR{5};
1024 let Inst{21-30} = xo;
1028 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1029 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1030 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
1034 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1035 InstrItinClass itin>
1036 : I<opcode, OOL, IOL, asmstr, itin> {
1039 let Inst{6-10} = RT;
1040 let Inst{11-20} = 0;
1041 let Inst{21-30} = xo;
1045 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1046 InstrItinClass itin>
1047 : I<opcode, OOL, IOL, asmstr, itin> {
1051 let Inst{6-10} = rS;
1053 let Inst{12-19} = FXM;
1055 let Inst{21-30} = xo;
1059 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1060 InstrItinClass itin>
1061 : I<opcode, OOL, IOL, asmstr, itin> {
1065 let Inst{6-10} = ST;
1067 let Inst{12-19} = FXM;
1069 let Inst{21-30} = xo;
1073 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1074 InstrItinClass itin>
1075 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1077 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1078 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1079 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1084 // This is probably 1.7.9, but I don't have the reference that uses this
1085 // numbering scheme...
1086 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1087 InstrItinClass itin, list<dag>pattern>
1088 : I<opcode, OOL, IOL, asmstr, itin> {
1092 bit RC = 0; // set by isDOT
1093 let Pattern = pattern;
1096 let Inst{7-14} = FM;
1098 let Inst{16-20} = rT;
1099 let Inst{21-30} = xo;
1103 class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1104 InstrItinClass itin, list<dag>pattern>
1105 : I<opcode, OOL, IOL, asmstr, itin> {
1111 bit RC = 0; // set by isDOT
1112 let Pattern = pattern;
1115 let Inst{7-14} = FLM;
1117 let Inst{16-20} = FRB;
1118 let Inst{21-30} = xo;
1122 // 1.7.10 XS-Form - SRADI.
1123 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1124 InstrItinClass itin, list<dag> pattern>
1125 : I<opcode, OOL, IOL, asmstr, itin> {
1130 bit RC = 0; // set by isDOT
1131 let Pattern = pattern;
1133 let Inst{6-10} = RS;
1134 let Inst{11-15} = A;
1135 let Inst{16-20} = SH{4,3,2,1,0};
1136 let Inst{21-29} = xo;
1137 let Inst{30} = SH{5};
1142 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1143 InstrItinClass itin, list<dag> pattern>
1144 : I<opcode, OOL, IOL, asmstr, itin> {
1149 let Pattern = pattern;
1151 bit RC = 0; // set by isDOT
1153 let Inst{6-10} = RT;
1154 let Inst{11-15} = RA;
1155 let Inst{16-20} = RB;
1157 let Inst{22-30} = xo;
1161 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1162 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1163 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1168 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1169 InstrItinClass itin, list<dag> pattern>
1170 : I<opcode, OOL, IOL, asmstr, itin> {
1176 let Pattern = pattern;
1178 bit RC = 0; // set by isDOT
1180 let Inst{6-10} = FRT;
1181 let Inst{11-15} = FRA;
1182 let Inst{16-20} = FRB;
1183 let Inst{21-25} = FRC;
1184 let Inst{26-30} = xo;
1188 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1189 InstrItinClass itin, list<dag> pattern>
1190 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1194 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1195 InstrItinClass itin, list<dag> pattern>
1196 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1200 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1201 InstrItinClass itin, list<dag> pattern>
1202 : I<opcode, OOL, IOL, asmstr, itin> {
1208 let Pattern = pattern;
1210 let Inst{6-10} = RT;
1211 let Inst{11-15} = RA;
1212 let Inst{16-20} = RB;
1213 let Inst{21-25} = COND;
1214 let Inst{26-30} = xo;
1219 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1220 InstrItinClass itin, list<dag> pattern>
1221 : I<opcode, OOL, IOL, asmstr, itin> {
1228 let Pattern = pattern;
1230 bit RC = 0; // set by isDOT
1232 let Inst{6-10} = RS;
1233 let Inst{11-15} = RA;
1234 let Inst{16-20} = RB;
1235 let Inst{21-25} = MB;
1236 let Inst{26-30} = ME;
1240 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1241 InstrItinClass itin, list<dag> pattern>
1242 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1246 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1247 InstrItinClass itin, list<dag> pattern>
1248 : I<opcode, OOL, IOL, asmstr, itin> {
1254 let Pattern = pattern;
1256 bit RC = 0; // set by isDOT
1258 let Inst{6-10} = RS;
1259 let Inst{11-15} = RA;
1260 let Inst{16-20} = SH{4,3,2,1,0};
1261 let Inst{21-26} = MBE{4,3,2,1,0,5};
1262 let Inst{27-29} = xo;
1263 let Inst{30} = SH{5};
1267 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1268 InstrItinClass itin, list<dag> pattern>
1269 : I<opcode, OOL, IOL, asmstr, itin> {
1275 let Pattern = pattern;
1277 bit RC = 0; // set by isDOT
1279 let Inst{6-10} = RS;
1280 let Inst{11-15} = RA;
1281 let Inst{16-20} = RB;
1282 let Inst{21-26} = MBE{4,3,2,1,0,5};
1283 let Inst{27-30} = xo;
1290 // VAForm_1 - DACB ordering.
1291 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1292 InstrItinClass itin, list<dag> pattern>
1293 : I<4, OOL, IOL, asmstr, itin> {
1299 let Pattern = pattern;
1301 let Inst{6-10} = VD;
1302 let Inst{11-15} = VA;
1303 let Inst{16-20} = VB;
1304 let Inst{21-25} = VC;
1305 let Inst{26-31} = xo;
1308 // VAForm_1a - DABC ordering.
1309 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1310 InstrItinClass itin, list<dag> pattern>
1311 : I<4, OOL, IOL, asmstr, itin> {
1317 let Pattern = pattern;
1319 let Inst{6-10} = VD;
1320 let Inst{11-15} = VA;
1321 let Inst{16-20} = VB;
1322 let Inst{21-25} = VC;
1323 let Inst{26-31} = xo;
1326 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1327 InstrItinClass itin, list<dag> pattern>
1328 : I<4, OOL, IOL, asmstr, itin> {
1334 let Pattern = pattern;
1336 let Inst{6-10} = VD;
1337 let Inst{11-15} = VA;
1338 let Inst{16-20} = VB;
1340 let Inst{22-25} = SH;
1341 let Inst{26-31} = xo;
1345 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1346 InstrItinClass itin, list<dag> pattern>
1347 : I<4, OOL, IOL, asmstr, itin> {
1352 let Pattern = pattern;
1354 let Inst{6-10} = VD;
1355 let Inst{11-15} = VA;
1356 let Inst{16-20} = VB;
1357 let Inst{21-31} = xo;
1360 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1361 InstrItinClass itin, list<dag> pattern>
1362 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1368 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1369 InstrItinClass itin, list<dag> pattern>
1370 : I<4, OOL, IOL, asmstr, itin> {
1374 let Pattern = pattern;
1376 let Inst{6-10} = VD;
1377 let Inst{11-15} = 0;
1378 let Inst{16-20} = VB;
1379 let Inst{21-31} = xo;
1382 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1383 InstrItinClass itin, list<dag> pattern>
1384 : I<4, OOL, IOL, asmstr, itin> {
1388 let Pattern = pattern;
1390 let Inst{6-10} = VD;
1391 let Inst{11-15} = IMM;
1392 let Inst{16-20} = 0;
1393 let Inst{21-31} = xo;
1396 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1397 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1398 InstrItinClass itin, list<dag> pattern>
1399 : I<4, OOL, IOL, asmstr, itin> {
1402 let Pattern = pattern;
1404 let Inst{6-10} = VD;
1405 let Inst{11-15} = 0;
1406 let Inst{16-20} = 0;
1407 let Inst{21-31} = xo;
1410 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1411 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1412 InstrItinClass itin, list<dag> pattern>
1413 : I<4, OOL, IOL, asmstr, itin> {
1416 let Pattern = pattern;
1419 let Inst{11-15} = 0;
1420 let Inst{16-20} = VB;
1421 let Inst{21-31} = xo;
1425 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1426 InstrItinClass itin, list<dag> pattern>
1427 : I<4, OOL, IOL, asmstr, itin> {
1433 let Pattern = pattern;
1435 let Inst{6-10} = VD;
1436 let Inst{11-15} = VA;
1437 let Inst{16-20} = VB;
1439 let Inst{22-31} = xo;
1442 //===----------------------------------------------------------------------===//
1443 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1444 : I<0, OOL, IOL, asmstr, NoItinerary> {
1445 let isCodeGenOnly = 1;
1447 let Pattern = pattern;