1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class Format<bits<5> val> {
17 def Pseudo: Format<0>;
20 def Simm16 : Format<3>;
21 def PCRelimm24 : Format<5>;
22 def Imm24 : Format<6>;
24 def PCRelimm14 : Format<8>;
25 def Imm14 : Format<9>;
26 def Imm2 : Format<10>;
28 def Imm3 : Format<12>;
29 def Imm1 : Format<13>;
31 def Imm4 : Format<15>;
32 def Imm8 : Format<16>;
33 def Disimm16 : Format<17>;
34 def Disimm14 : Format<18>;
37 def Imm15 : Format<21>;
39 def Imm6 : Format<23>;
41 //===----------------------------------------------------------------------===//
43 // PowerPC instruction formats
45 class I<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
53 let Namespace = "PPC";
54 let Inst{0-5} = opcode;
56 let AsmString = asmstr;
60 class IForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
61 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
70 class BForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
71 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
78 let Inst{11-13} = CRNum;
79 let Inst{14-15} = BICode;
85 class BForm_ext<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode,
86 bit ppc64, bit vmx, dag OL, string asmstr>
87 : BForm<opcode, aa, lk, ppc64, vmx, OL, asmstr> {
93 class DForm_base<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
94 : I<opcode, ppc64, vmx, OL, asmstr> {
104 class DForm_1<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
105 : I<opcode, ppc64, vmx, OL, asmstr> {
115 class DForm_2<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
116 : DForm_base<opcode, ppc64, vmx, OL, asmstr>;
118 class DForm_2_r0<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
119 : I<opcode, ppc64, vmx, OL, asmstr> {
128 // Currently we make the use/def reg distinction in ISel, not tablegen
129 class DForm_3<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
130 : DForm_1<opcode, ppc64, vmx, OL, asmstr>;
132 class DForm_4<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
133 : I<opcode, ppc64, vmx, OL, asmstr> {
143 class DForm_4_zero<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
144 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
150 class DForm_5<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
151 : I<opcode, ppc64, vmx, OL, asmstr> {
160 let Inst{11-15} = RA;
164 class DForm_5_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
165 : DForm_5<opcode, ppc64, vmx, OL, asmstr> {
169 class DForm_6<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
170 : DForm_5<opcode, ppc64, vmx, OL, asmstr>;
172 class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
173 : DForm_6<opcode, ppc64, vmx, OL, asmstr> {
177 class DForm_8<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
178 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
181 class DForm_9<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
182 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
186 class DSForm_1<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
187 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
192 let Inst{6-10} = RST;
193 let Inst{11-15} = RA;
194 let Inst{16-29} = DS;
195 let Inst{30-31} = xo;
198 class DSForm_2<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
199 dag OL, string asmstr>
200 : DSForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
203 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
204 dag OL, string asmstr>
205 : I<opcode, ppc64, vmx, OL, asmstr> {
210 let Inst{6-10} = RST;
213 let Inst{21-30} = xo;
217 // This is the same as XForm_base_r3xo, but the first two operands are swapped
218 // when code is emitted.
219 class XForm_base_r3xo_swapped
220 <bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
221 dag OL, string asmstr>
222 : I<opcode, ppc64, vmx, OL, asmstr> {
227 let Inst{6-10} = RST;
230 let Inst{21-30} = xo;
235 class XForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
236 dag OL, string asmstr>
237 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
239 class XForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
240 dag OL, string asmstr>
241 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
246 class XForm_6<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
247 dag OL, string asmstr>
248 : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr>;
250 class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
251 dag OL, string asmstr>
252 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
254 class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
255 dag OL, string asmstr>
256 : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
259 class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
260 dag OL, string asmstr>
261 : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
265 class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
266 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
275 let Inst{11-15} = RA;
276 let Inst{16-20} = RB;
277 let Inst{21-30} = xo;
281 class XForm_16_ext<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
282 dag OL, string asmstr>
283 : XForm_16<opcode, xo, ppc64, vmx, OL, asmstr> {
287 class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
288 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
295 let Inst{11-15} = FRA;
296 let Inst{16-20} = FRB;
297 let Inst{21-30} = xo;
301 class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
302 dag OL, string asmstr>
303 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
306 class XForm_26<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
307 dag OL, string asmstr>
308 : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
312 class XForm_28<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
313 dag OL, string asmstr>
314 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
318 class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
319 dag OL, string asmstr>
320 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
323 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
324 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
330 let Inst{11-15} = BI;
332 let Inst{19-20} = BH;
333 let Inst{21-30} = xo;
337 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
338 bits<5> bi, bit lk, bit ppc64, bit vmx,
339 dag OL, string asmstr>
340 : XLForm_2<opcode, xo, lk, ppc64, vmx, OL, asmstr> {
347 class XFXForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
348 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
353 let Inst{11-20} = SPR;
354 let Inst{21-30} = xo;
358 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, bit ppc64,
359 bit vmx, dag OL, string asmstr>
360 : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr> {
364 class XFXForm_7<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
365 dag OL, string asmstr>
366 : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
368 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
369 bit ppc64, bit vmx, dag OL, string asmstr>
370 : XFXForm_7<opcode, xo, ppc64, vmx, OL, asmstr> {
375 class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, bit ppc64, bit vmx,
376 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
383 let Inst{16-20} = SH{1-5};
384 let Inst{21-29} = xo;
385 let Inst{30} = SH{0};
390 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
391 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
397 let Inst{11-15} = RA;
398 let Inst{16-20} = RB;
400 let Inst{22-30} = xo;
404 class XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
405 dag OL, string asmstr>
406 : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
407 let Inst{11-15} = RB;
408 let Inst{16-20} = RA;
411 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
412 dag OL, string asmstr>
413 : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
418 class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx,
419 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
425 let Inst{6-10} = FRT;
426 let Inst{11-15} = FRA;
427 let Inst{16-20} = FRB;
428 let Inst{21-25} = FRC;
429 let Inst{26-30} = xo;
433 class AForm_2<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
435 : AForm_1<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
439 class AForm_3<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
441 : AForm_1<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
446 class MForm_1<bits<6> opcode, bit rc, bit ppc64, bit vmx,
447 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
455 let Inst{11-15} = RA;
456 let Inst{16-20} = RB;
457 let Inst{21-25} = MB;
458 let Inst{26-30} = ME;
462 class MForm_2<bits<6> opcode, bit rc, bit ppc64, bit vmx,
463 dag OL, string asmstr>
464 : MForm_1<opcode, rc, ppc64, vmx, OL, asmstr> {
468 class MDForm_1<bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx,
469 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
476 let Inst{11-15} = RA;
477 let Inst{16-20} = SH{1-5};
478 let Inst{21-26} = MBE;
479 let Inst{27-29} = xo;
480 let Inst{30} = SH{0};
484 //===----------------------------------------------------------------------===//
486 class Pseudo<dag OL, string asmstr> : I<0, 0, 0, OL, asmstr> {