1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
388 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
390 : I<opcode, OOL, IOL, asmstr, itin> {
391 let Inst{21-30} = xo;
394 // This is the same as XForm_base_r3xo, but the first two operands are swapped
395 // when code is emitted.
396 class XForm_base_r3xo_swapped
397 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
399 : I<opcode, OOL, IOL, asmstr, itin> {
404 bit RC = 0; // set by isDOT
406 let Inst{6-10} = RST;
409 let Inst{21-30} = xo;
414 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
415 InstrItinClass itin, list<dag> pattern>
416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
418 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
419 InstrItinClass itin, list<dag> pattern>
420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
424 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
425 InstrItinClass itin, list<dag> pattern>
426 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
431 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
432 InstrItinClass itin, list<dag> pattern>
433 : I<opcode, OOL, IOL, asmstr, itin> {
438 let Pattern = pattern;
440 let Inst{6-10} = RST;
443 let Inst{21-30} = xo;
447 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
448 InstrItinClass itin, list<dag> pattern>
449 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
450 let Pattern = pattern;
453 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
454 InstrItinClass itin, list<dag> pattern>
455 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
457 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
458 InstrItinClass itin, list<dag> pattern>
459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
460 let Pattern = pattern;
463 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
464 InstrItinClass itin, list<dag> pattern>
465 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
467 let Pattern = pattern;
470 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
472 : I<opcode, OOL, IOL, asmstr, itin> {
481 let Inst{11-15} = RA;
482 let Inst{16-20} = RB;
483 let Inst{21-30} = xo;
487 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
489 : I<opcode, OOL, IOL, asmstr, itin> {
496 let Inst{11-15} = RA;
497 let Inst{16-20} = RB;
498 let Inst{21-30} = xo;
502 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
504 : I<opcode, OOL, IOL, asmstr, itin> {
509 let Inst{12-15} = SR;
510 let Inst{21-30} = xo;
513 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
515 : I<opcode, OOL, IOL, asmstr, itin> {
519 let Inst{21-30} = xo;
522 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
524 : I<opcode, OOL, IOL, asmstr, itin> {
529 let Inst{16-20} = RB;
530 let Inst{21-30} = xo;
533 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
535 : I<opcode, OOL, IOL, asmstr, itin> {
541 let Inst{21-30} = xo;
544 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
546 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
550 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
552 : I<opcode, OOL, IOL, asmstr, itin> {
559 let Inst{11-15} = FRA;
560 let Inst{16-20} = FRB;
561 let Inst{21-30} = xo;
565 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
566 InstrItinClass itin, list<dag> pattern>
567 : I<opcode, OOL, IOL, asmstr, itin> {
568 let Pattern = pattern;
572 let Inst{21-30} = xo;
576 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
577 string asmstr, InstrItinClass itin, list<dag> pattern>
578 : I<opcode, OOL, IOL, asmstr, itin> {
581 let Pattern = pattern;
586 let Inst{21-30} = xo;
590 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
591 string asmstr, InstrItinClass itin, list<dag> pattern>
592 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
596 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
597 InstrItinClass itin, list<dag> pattern>
598 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
601 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
602 InstrItinClass itin, list<dag> pattern>
603 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
607 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
608 InstrItinClass itin, list<dag> pattern>
609 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
612 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
613 // numbers presumably relates to some document, but I haven't found it.
614 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
615 InstrItinClass itin, list<dag> pattern>
616 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
617 let Pattern = pattern;
619 bit RC = 0; // set by isDOT
621 let Inst{6-10} = RST;
623 let Inst{21-30} = xo;
626 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
627 InstrItinClass itin, list<dag> pattern>
628 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
629 let Pattern = pattern;
632 bit RC = 0; // set by isDOT
636 let Inst{21-30} = xo;
640 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
641 InstrItinClass itin, list<dag> pattern>
642 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
648 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
649 InstrItinClass itin, list<dag> pattern>
650 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
656 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
657 InstrItinClass itin, list<dag> pattern>
658 : I<opcode, OOL, IOL, asmstr, itin> {
663 let Pattern = pattern;
665 let Inst{6-10} = XT{4-0};
668 let Inst{21-30} = xo;
669 let Inst{31} = XT{5};
672 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
673 InstrItinClass itin, list<dag> pattern>
674 : I<opcode, OOL, IOL, asmstr, itin> {
678 let Pattern = pattern;
680 let Inst{6-10} = XT{4-0};
682 let Inst{16-20} = XB{4-0};
683 let Inst{21-29} = xo;
684 let Inst{30} = XB{5};
685 let Inst{31} = XT{5};
688 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
689 InstrItinClass itin, list<dag> pattern>
690 : I<opcode, OOL, IOL, asmstr, itin> {
694 let Pattern = pattern;
698 let Inst{16-20} = XB{4-0};
699 let Inst{21-29} = xo;
700 let Inst{30} = XB{5};
704 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
705 InstrItinClass itin, list<dag> pattern>
706 : I<opcode, OOL, IOL, asmstr, itin> {
711 let Pattern = pattern;
713 let Inst{6-10} = XT{4-0};
716 let Inst{16-20} = XB{4-0};
717 let Inst{21-29} = xo;
718 let Inst{30} = XB{5};
719 let Inst{31} = XT{5};
722 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
723 InstrItinClass itin, list<dag> pattern>
724 : I<opcode, OOL, IOL, asmstr, itin> {
729 let Pattern = pattern;
731 let Inst{6-10} = XT{4-0};
732 let Inst{11-15} = XA{4-0};
733 let Inst{16-20} = XB{4-0};
734 let Inst{21-28} = xo;
735 let Inst{29} = XA{5};
736 let Inst{30} = XB{5};
737 let Inst{31} = XT{5};
740 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
741 InstrItinClass itin, list<dag> pattern>
742 : I<opcode, OOL, IOL, asmstr, itin> {
747 let Pattern = pattern;
751 let Inst{11-15} = XA{4-0};
752 let Inst{16-20} = XB{4-0};
753 let Inst{21-28} = xo;
754 let Inst{29} = XA{5};
755 let Inst{30} = XB{5};
759 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
760 InstrItinClass itin, list<dag> pattern>
761 : I<opcode, OOL, IOL, asmstr, itin> {
767 let Pattern = pattern;
769 let Inst{6-10} = XT{4-0};
770 let Inst{11-15} = XA{4-0};
771 let Inst{16-20} = XB{4-0};
774 let Inst{24-28} = xo;
775 let Inst{29} = XA{5};
776 let Inst{30} = XB{5};
777 let Inst{31} = XT{5};
780 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
781 InstrItinClass itin, list<dag> pattern>
782 : I<opcode, OOL, IOL, asmstr, itin> {
787 let Pattern = pattern;
789 bit RC = 0; // set by isDOT
791 let Inst{6-10} = XT{4-0};
792 let Inst{11-15} = XA{4-0};
793 let Inst{16-20} = XB{4-0};
795 let Inst{22-28} = xo;
796 let Inst{29} = XA{5};
797 let Inst{30} = XB{5};
798 let Inst{31} = XT{5};
801 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
802 InstrItinClass itin, list<dag> pattern>
803 : I<opcode, OOL, IOL, asmstr, itin> {
809 let Pattern = pattern;
811 let Inst{6-10} = XT{4-0};
812 let Inst{11-15} = XA{4-0};
813 let Inst{16-20} = XB{4-0};
814 let Inst{21-25} = XC{4-0};
815 let Inst{26-27} = xo;
816 let Inst{28} = XC{5};
817 let Inst{29} = XA{5};
818 let Inst{30} = XB{5};
819 let Inst{31} = XT{5};
822 // DCB_Form - Form X instruction, used for dcb* instructions.
823 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
824 InstrItinClass itin, list<dag> pattern>
825 : I<31, OOL, IOL, asmstr, itin> {
829 let Pattern = pattern;
831 let Inst{6-10} = immfield;
834 let Inst{21-30} = xo;
839 // DSS_Form - Form X instruction, used for altivec dss* instructions.
840 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
841 InstrItinClass itin, list<dag> pattern>
842 : I<31, OOL, IOL, asmstr, itin> {
847 let Pattern = pattern;
851 let Inst{9-10} = STRM;
854 let Inst{21-30} = xo;
859 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
860 InstrItinClass itin, list<dag> pattern>
861 : I<opcode, OOL, IOL, asmstr, itin> {
866 let Pattern = pattern;
868 let Inst{6-10} = CRD;
869 let Inst{11-15} = CRA;
870 let Inst{16-20} = CRB;
871 let Inst{21-30} = xo;
875 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
876 InstrItinClass itin, list<dag> pattern>
877 : I<opcode, OOL, IOL, asmstr, itin> {
880 let Pattern = pattern;
882 let Inst{6-10} = CRD;
883 let Inst{11-15} = CRD;
884 let Inst{16-20} = CRD;
885 let Inst{21-30} = xo;
889 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
890 InstrItinClass itin, list<dag> pattern>
891 : I<opcode, OOL, IOL, asmstr, itin> {
896 let Pattern = pattern;
899 let Inst{11-15} = BI;
901 let Inst{19-20} = BH;
902 let Inst{21-30} = xo;
906 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
907 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
908 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
909 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
913 let BI{0-1} = BIBO{5-6};
914 let BI{2-4} = CR{0-2};
918 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
919 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
920 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
925 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
926 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
927 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
933 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
935 : I<opcode, OOL, IOL, asmstr, itin> {
941 let Inst{11-13} = BFA;
944 let Inst{21-30} = xo;
948 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
949 bits<6> opcode2, bits<2> xo2,
950 dag OOL, dag IOL, string asmstr,
951 InstrItinClass itin, list<dag> pattern>
952 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
960 let Pattern = pattern;
963 let Inst{11-15} = BI;
965 let Inst{19-20} = BH;
966 let Inst{21-30} = xo1;
969 let Inst{38-42} = RST;
970 let Inst{43-47} = DS_RA{18-14}; // Register #
971 let Inst{48-61} = DS_RA{13-0}; // Displacement.
972 let Inst{62-63} = xo2;
975 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
976 bits<5> bo, bits<5> bi, bit lk,
977 bits<6> opcode2, bits<2> xo2,
978 dag OOL, dag IOL, string asmstr,
979 InstrItinClass itin, list<dag> pattern>
980 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
981 OOL, IOL, asmstr, itin, pattern> {
988 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
990 : I<opcode, OOL, IOL, asmstr, itin> {
995 let Inst{11} = SPR{4};
996 let Inst{12} = SPR{3};
997 let Inst{13} = SPR{2};
998 let Inst{14} = SPR{1};
999 let Inst{15} = SPR{0};
1000 let Inst{16} = SPR{9};
1001 let Inst{17} = SPR{8};
1002 let Inst{18} = SPR{7};
1003 let Inst{19} = SPR{6};
1004 let Inst{20} = SPR{5};
1005 let Inst{21-30} = xo;
1009 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1010 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1011 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
1015 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1016 InstrItinClass itin>
1017 : I<opcode, OOL, IOL, asmstr, itin> {
1020 let Inst{6-10} = RT;
1021 let Inst{11-20} = 0;
1022 let Inst{21-30} = xo;
1026 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1027 InstrItinClass itin>
1028 : I<opcode, OOL, IOL, asmstr, itin> {
1032 let Inst{6-10} = rS;
1034 let Inst{12-19} = FXM;
1036 let Inst{21-30} = xo;
1040 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1041 InstrItinClass itin>
1042 : I<opcode, OOL, IOL, asmstr, itin> {
1046 let Inst{6-10} = ST;
1048 let Inst{12-19} = FXM;
1050 let Inst{21-30} = xo;
1054 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1055 InstrItinClass itin>
1056 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1058 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1059 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1060 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1065 // This is probably 1.7.9, but I don't have the reference that uses this
1066 // numbering scheme...
1067 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1068 InstrItinClass itin, list<dag>pattern>
1069 : I<opcode, OOL, IOL, asmstr, itin> {
1073 bit RC = 0; // set by isDOT
1074 let Pattern = pattern;
1077 let Inst{7-14} = FM;
1079 let Inst{16-20} = rT;
1080 let Inst{21-30} = xo;
1084 // 1.7.10 XS-Form - SRADI.
1085 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1086 InstrItinClass itin, list<dag> pattern>
1087 : I<opcode, OOL, IOL, asmstr, itin> {
1092 bit RC = 0; // set by isDOT
1093 let Pattern = pattern;
1095 let Inst{6-10} = RS;
1096 let Inst{11-15} = A;
1097 let Inst{16-20} = SH{4,3,2,1,0};
1098 let Inst{21-29} = xo;
1099 let Inst{30} = SH{5};
1104 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1105 InstrItinClass itin, list<dag> pattern>
1106 : I<opcode, OOL, IOL, asmstr, itin> {
1111 let Pattern = pattern;
1113 bit RC = 0; // set by isDOT
1115 let Inst{6-10} = RT;
1116 let Inst{11-15} = RA;
1117 let Inst{16-20} = RB;
1119 let Inst{22-30} = xo;
1123 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1124 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1125 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1130 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1131 InstrItinClass itin, list<dag> pattern>
1132 : I<opcode, OOL, IOL, asmstr, itin> {
1138 let Pattern = pattern;
1140 bit RC = 0; // set by isDOT
1142 let Inst{6-10} = FRT;
1143 let Inst{11-15} = FRA;
1144 let Inst{16-20} = FRB;
1145 let Inst{21-25} = FRC;
1146 let Inst{26-30} = xo;
1150 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1151 InstrItinClass itin, list<dag> pattern>
1152 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1156 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1157 InstrItinClass itin, list<dag> pattern>
1158 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1162 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1163 InstrItinClass itin, list<dag> pattern>
1164 : I<opcode, OOL, IOL, asmstr, itin> {
1170 let Pattern = pattern;
1172 let Inst{6-10} = RT;
1173 let Inst{11-15} = RA;
1174 let Inst{16-20} = RB;
1175 let Inst{21-25} = COND;
1176 let Inst{26-30} = xo;
1181 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1182 InstrItinClass itin, list<dag> pattern>
1183 : I<opcode, OOL, IOL, asmstr, itin> {
1190 let Pattern = pattern;
1192 bit RC = 0; // set by isDOT
1194 let Inst{6-10} = RS;
1195 let Inst{11-15} = RA;
1196 let Inst{16-20} = RB;
1197 let Inst{21-25} = MB;
1198 let Inst{26-30} = ME;
1202 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1203 InstrItinClass itin, list<dag> pattern>
1204 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1208 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1209 InstrItinClass itin, list<dag> pattern>
1210 : I<opcode, OOL, IOL, asmstr, itin> {
1216 let Pattern = pattern;
1218 bit RC = 0; // set by isDOT
1220 let Inst{6-10} = RS;
1221 let Inst{11-15} = RA;
1222 let Inst{16-20} = SH{4,3,2,1,0};
1223 let Inst{21-26} = MBE{4,3,2,1,0,5};
1224 let Inst{27-29} = xo;
1225 let Inst{30} = SH{5};
1229 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1230 InstrItinClass itin, list<dag> pattern>
1231 : I<opcode, OOL, IOL, asmstr, itin> {
1237 let Pattern = pattern;
1239 bit RC = 0; // set by isDOT
1241 let Inst{6-10} = RS;
1242 let Inst{11-15} = RA;
1243 let Inst{16-20} = RB;
1244 let Inst{21-26} = MBE{4,3,2,1,0,5};
1245 let Inst{27-30} = xo;
1252 // VAForm_1 - DACB ordering.
1253 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1254 InstrItinClass itin, list<dag> pattern>
1255 : I<4, OOL, IOL, asmstr, itin> {
1261 let Pattern = pattern;
1263 let Inst{6-10} = VD;
1264 let Inst{11-15} = VA;
1265 let Inst{16-20} = VB;
1266 let Inst{21-25} = VC;
1267 let Inst{26-31} = xo;
1270 // VAForm_1a - DABC ordering.
1271 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1272 InstrItinClass itin, list<dag> pattern>
1273 : I<4, OOL, IOL, asmstr, itin> {
1279 let Pattern = pattern;
1281 let Inst{6-10} = VD;
1282 let Inst{11-15} = VA;
1283 let Inst{16-20} = VB;
1284 let Inst{21-25} = VC;
1285 let Inst{26-31} = xo;
1288 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1289 InstrItinClass itin, list<dag> pattern>
1290 : I<4, OOL, IOL, asmstr, itin> {
1296 let Pattern = pattern;
1298 let Inst{6-10} = VD;
1299 let Inst{11-15} = VA;
1300 let Inst{16-20} = VB;
1302 let Inst{22-25} = SH;
1303 let Inst{26-31} = xo;
1307 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1308 InstrItinClass itin, list<dag> pattern>
1309 : I<4, OOL, IOL, asmstr, itin> {
1314 let Pattern = pattern;
1316 let Inst{6-10} = VD;
1317 let Inst{11-15} = VA;
1318 let Inst{16-20} = VB;
1319 let Inst{21-31} = xo;
1322 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1323 InstrItinClass itin, list<dag> pattern>
1324 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1330 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1331 InstrItinClass itin, list<dag> pattern>
1332 : I<4, OOL, IOL, asmstr, itin> {
1336 let Pattern = pattern;
1338 let Inst{6-10} = VD;
1339 let Inst{11-15} = 0;
1340 let Inst{16-20} = VB;
1341 let Inst{21-31} = xo;
1344 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1345 InstrItinClass itin, list<dag> pattern>
1346 : I<4, OOL, IOL, asmstr, itin> {
1350 let Pattern = pattern;
1352 let Inst{6-10} = VD;
1353 let Inst{11-15} = IMM;
1354 let Inst{16-20} = 0;
1355 let Inst{21-31} = xo;
1358 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1359 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1360 InstrItinClass itin, list<dag> pattern>
1361 : I<4, OOL, IOL, asmstr, itin> {
1364 let Pattern = pattern;
1366 let Inst{6-10} = VD;
1367 let Inst{11-15} = 0;
1368 let Inst{16-20} = 0;
1369 let Inst{21-31} = xo;
1372 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1373 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1374 InstrItinClass itin, list<dag> pattern>
1375 : I<4, OOL, IOL, asmstr, itin> {
1378 let Pattern = pattern;
1381 let Inst{11-15} = 0;
1382 let Inst{16-20} = VB;
1383 let Inst{21-31} = xo;
1387 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1388 InstrItinClass itin, list<dag> pattern>
1389 : I<4, OOL, IOL, asmstr, itin> {
1395 let Pattern = pattern;
1397 let Inst{6-10} = VD;
1398 let Inst{11-15} = VA;
1399 let Inst{16-20} = VB;
1401 let Inst{22-31} = xo;
1404 //===----------------------------------------------------------------------===//
1405 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1406 : I<0, OOL, IOL, asmstr, NoItinerary> {
1407 let isCodeGenOnly = 1;
1409 let Pattern = pattern;