1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 // This is the same as XForm_base_r3xo, but the first two operands are swapped
384 // when code is emitted.
385 class XForm_base_r3xo_swapped
386 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
388 : I<opcode, OOL, IOL, asmstr, itin> {
393 bit RC = 0; // set by isDOT
395 let Inst{6-10} = RST;
398 let Inst{21-30} = xo;
403 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
404 InstrItinClass itin, list<dag> pattern>
405 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
407 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
408 InstrItinClass itin, list<dag> pattern>
409 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
413 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
414 InstrItinClass itin, list<dag> pattern>
415 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
420 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
421 InstrItinClass itin, list<dag> pattern>
422 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
423 let Pattern = pattern;
426 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
427 InstrItinClass itin, list<dag> pattern>
428 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
430 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
431 InstrItinClass itin, list<dag> pattern>
432 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
433 let Pattern = pattern;
436 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
437 InstrItinClass itin, list<dag> pattern>
438 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
440 let Pattern = pattern;
443 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
445 : I<opcode, OOL, IOL, asmstr, itin> {
454 let Inst{11-15} = RA;
455 let Inst{16-20} = RB;
456 let Inst{21-30} = xo;
460 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
462 : I<opcode, OOL, IOL, asmstr, itin> {
468 let Inst{21-30} = xo;
471 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
473 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
477 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
479 : I<opcode, OOL, IOL, asmstr, itin> {
486 let Inst{11-15} = FRA;
487 let Inst{16-20} = FRB;
488 let Inst{21-30} = xo;
492 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
493 InstrItinClass itin, list<dag> pattern>
494 : I<opcode, OOL, IOL, asmstr, itin> {
495 let Pattern = pattern;
499 let Inst{21-30} = xo;
503 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
504 string asmstr, InstrItinClass itin, list<dag> pattern>
505 : I<opcode, OOL, IOL, asmstr, itin> {
508 let Pattern = pattern;
513 let Inst{21-30} = xo;
517 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
518 string asmstr, InstrItinClass itin, list<dag> pattern>
519 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
523 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
524 InstrItinClass itin, list<dag> pattern>
525 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
528 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
529 InstrItinClass itin, list<dag> pattern>
530 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
534 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
535 InstrItinClass itin, list<dag> pattern>
536 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
539 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
540 // numbers presumably relates to some document, but I haven't found it.
541 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
542 InstrItinClass itin, list<dag> pattern>
543 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
544 let Pattern = pattern;
546 bit RC = 0; // set by isDOT
548 let Inst{6-10} = RST;
550 let Inst{21-30} = xo;
553 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
554 InstrItinClass itin, list<dag> pattern>
555 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
556 let Pattern = pattern;
559 bit RC = 0; // set by isDOT
563 let Inst{21-30} = xo;
567 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
568 InstrItinClass itin, list<dag> pattern>
569 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
575 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
576 InstrItinClass itin, list<dag> pattern>
577 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
583 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
584 InstrItinClass itin, list<dag> pattern>
585 : I<opcode, OOL, IOL, asmstr, itin> {
590 let Pattern = pattern;
592 let Inst{6-10} = XT{4-0};
595 let Inst{21-30} = xo;
596 let Inst{31} = XT{5};
599 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
600 InstrItinClass itin, list<dag> pattern>
601 : I<opcode, OOL, IOL, asmstr, itin> {
605 let Pattern = pattern;
607 let Inst{6-10} = XT{4-0};
609 let Inst{16-20} = XB{4-0};
610 let Inst{21-29} = xo;
611 let Inst{30} = XB{5};
612 let Inst{31} = XT{5};
615 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
616 InstrItinClass itin, list<dag> pattern>
617 : I<opcode, OOL, IOL, asmstr, itin> {
621 let Pattern = pattern;
625 let Inst{16-20} = XB{4-0};
626 let Inst{21-29} = xo;
627 let Inst{30} = XB{5};
631 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
632 InstrItinClass itin, list<dag> pattern>
633 : I<opcode, OOL, IOL, asmstr, itin> {
638 let Pattern = pattern;
640 let Inst{6-10} = XT{4-0};
643 let Inst{16-20} = XB{4-0};
644 let Inst{21-29} = xo;
645 let Inst{30} = XB{5};
646 let Inst{31} = XT{5};
649 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
650 InstrItinClass itin, list<dag> pattern>
651 : I<opcode, OOL, IOL, asmstr, itin> {
656 let Pattern = pattern;
658 let Inst{6-10} = XT{4-0};
659 let Inst{11-15} = XA{4-0};
660 let Inst{16-20} = XB{4-0};
661 let Inst{21-28} = xo;
662 let Inst{29} = XA{5};
663 let Inst{30} = XB{5};
664 let Inst{31} = XT{5};
667 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
668 InstrItinClass itin, list<dag> pattern>
669 : I<opcode, OOL, IOL, asmstr, itin> {
674 let Pattern = pattern;
678 let Inst{11-15} = XA{4-0};
679 let Inst{16-20} = XB{4-0};
680 let Inst{21-28} = xo;
681 let Inst{29} = XA{5};
682 let Inst{30} = XB{5};
686 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
687 InstrItinClass itin, list<dag> pattern>
688 : I<opcode, OOL, IOL, asmstr, itin> {
694 let Pattern = pattern;
696 let Inst{6-10} = XT{4-0};
697 let Inst{11-15} = XA{4-0};
698 let Inst{16-20} = XB{4-0};
701 let Inst{24-28} = xo;
702 let Inst{29} = XA{5};
703 let Inst{30} = XB{5};
704 let Inst{31} = XT{5};
707 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
708 InstrItinClass itin, list<dag> pattern>
709 : I<opcode, OOL, IOL, asmstr, itin> {
714 let Pattern = pattern;
716 bit RC = 0; // set by isDOT
718 let Inst{6-10} = XT{4-0};
719 let Inst{11-15} = XA{4-0};
720 let Inst{16-20} = XB{4-0};
722 let Inst{22-28} = xo;
723 let Inst{29} = XA{5};
724 let Inst{30} = XB{5};
725 let Inst{31} = XT{5};
728 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
729 InstrItinClass itin, list<dag> pattern>
730 : I<opcode, OOL, IOL, asmstr, itin> {
736 let Pattern = pattern;
738 let Inst{6-10} = XT{4-0};
739 let Inst{11-15} = XA{4-0};
740 let Inst{16-20} = XB{4-0};
741 let Inst{21-25} = XC{4-0};
742 let Inst{26-27} = xo;
743 let Inst{28} = XC{5};
744 let Inst{29} = XA{5};
745 let Inst{30} = XB{5};
746 let Inst{31} = XT{5};
749 // DCB_Form - Form X instruction, used for dcb* instructions.
750 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
751 InstrItinClass itin, list<dag> pattern>
752 : I<31, OOL, IOL, asmstr, itin> {
756 let Pattern = pattern;
758 let Inst{6-10} = immfield;
761 let Inst{21-30} = xo;
766 // DSS_Form - Form X instruction, used for altivec dss* instructions.
767 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
768 InstrItinClass itin, list<dag> pattern>
769 : I<31, OOL, IOL, asmstr, itin> {
775 let Pattern = pattern;
779 let Inst{9-10} = STRM;
782 let Inst{21-30} = xo;
787 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
788 InstrItinClass itin, list<dag> pattern>
789 : I<opcode, OOL, IOL, asmstr, itin> {
794 let Pattern = pattern;
796 let Inst{6-10} = CRD;
797 let Inst{11-15} = CRA;
798 let Inst{16-20} = CRB;
799 let Inst{21-30} = xo;
803 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
804 InstrItinClass itin, list<dag> pattern>
805 : I<opcode, OOL, IOL, asmstr, itin> {
808 let Pattern = pattern;
810 let Inst{6-10} = CRD;
811 let Inst{11-15} = CRD;
812 let Inst{16-20} = CRD;
813 let Inst{21-30} = xo;
817 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
818 InstrItinClass itin, list<dag> pattern>
819 : I<opcode, OOL, IOL, asmstr, itin> {
824 let Pattern = pattern;
827 let Inst{11-15} = BI;
829 let Inst{19-20} = BH;
830 let Inst{21-30} = xo;
834 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
835 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
836 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
837 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
841 let BI{0-1} = BIBO{5-6};
842 let BI{2-4} = CR{0-2};
846 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
847 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
848 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
853 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
854 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
855 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
861 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
863 : I<opcode, OOL, IOL, asmstr, itin> {
869 let Inst{11-13} = BFA;
872 let Inst{21-30} = xo;
877 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
879 : I<opcode, OOL, IOL, asmstr, itin> {
884 let Inst{11} = SPR{4};
885 let Inst{12} = SPR{3};
886 let Inst{13} = SPR{2};
887 let Inst{14} = SPR{1};
888 let Inst{15} = SPR{0};
889 let Inst{16} = SPR{9};
890 let Inst{17} = SPR{8};
891 let Inst{18} = SPR{7};
892 let Inst{19} = SPR{6};
893 let Inst{20} = SPR{5};
894 let Inst{21-30} = xo;
898 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
899 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
900 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
904 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
906 : I<opcode, OOL, IOL, asmstr, itin> {
911 let Inst{21-30} = xo;
915 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
917 : I<opcode, OOL, IOL, asmstr, itin> {
923 let Inst{12-19} = FXM;
925 let Inst{21-30} = xo;
929 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
931 : I<opcode, OOL, IOL, asmstr, itin> {
937 let Inst{12-19} = FXM;
939 let Inst{21-30} = xo;
943 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
945 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
947 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
948 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
949 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
954 // This is probably 1.7.9, but I don't have the reference that uses this
955 // numbering scheme...
956 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
957 InstrItinClass itin, list<dag>pattern>
958 : I<opcode, OOL, IOL, asmstr, itin> {
962 bit RC = 0; // set by isDOT
963 let Pattern = pattern;
968 let Inst{16-20} = rT;
969 let Inst{21-30} = xo;
973 // 1.7.10 XS-Form - SRADI.
974 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
975 InstrItinClass itin, list<dag> pattern>
976 : I<opcode, OOL, IOL, asmstr, itin> {
981 bit RC = 0; // set by isDOT
982 let Pattern = pattern;
986 let Inst{16-20} = SH{4,3,2,1,0};
987 let Inst{21-29} = xo;
988 let Inst{30} = SH{5};
993 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
994 InstrItinClass itin, list<dag> pattern>
995 : I<opcode, OOL, IOL, asmstr, itin> {
1000 let Pattern = pattern;
1002 bit RC = 0; // set by isDOT
1004 let Inst{6-10} = RT;
1005 let Inst{11-15} = RA;
1006 let Inst{16-20} = RB;
1008 let Inst{22-30} = xo;
1012 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1013 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1014 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1019 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1020 InstrItinClass itin, list<dag> pattern>
1021 : I<opcode, OOL, IOL, asmstr, itin> {
1027 let Pattern = pattern;
1029 bit RC = 0; // set by isDOT
1031 let Inst{6-10} = FRT;
1032 let Inst{11-15} = FRA;
1033 let Inst{16-20} = FRB;
1034 let Inst{21-25} = FRC;
1035 let Inst{26-30} = xo;
1039 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1040 InstrItinClass itin, list<dag> pattern>
1041 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1045 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1046 InstrItinClass itin, list<dag> pattern>
1047 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1051 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1052 InstrItinClass itin, list<dag> pattern>
1053 : I<opcode, OOL, IOL, asmstr, itin> {
1059 let Pattern = pattern;
1061 let Inst{6-10} = RT;
1062 let Inst{11-15} = RA;
1063 let Inst{16-20} = RB;
1064 let Inst{21-25} = COND;
1065 let Inst{26-30} = xo;
1070 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1071 InstrItinClass itin, list<dag> pattern>
1072 : I<opcode, OOL, IOL, asmstr, itin> {
1079 let Pattern = pattern;
1081 bit RC = 0; // set by isDOT
1083 let Inst{6-10} = RS;
1084 let Inst{11-15} = RA;
1085 let Inst{16-20} = RB;
1086 let Inst{21-25} = MB;
1087 let Inst{26-30} = ME;
1091 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1092 InstrItinClass itin, list<dag> pattern>
1093 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1097 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1098 InstrItinClass itin, list<dag> pattern>
1099 : I<opcode, OOL, IOL, asmstr, itin> {
1105 let Pattern = pattern;
1107 bit RC = 0; // set by isDOT
1109 let Inst{6-10} = RS;
1110 let Inst{11-15} = RA;
1111 let Inst{16-20} = SH{4,3,2,1,0};
1112 let Inst{21-26} = MBE{4,3,2,1,0,5};
1113 let Inst{27-29} = xo;
1114 let Inst{30} = SH{5};
1118 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1119 InstrItinClass itin, list<dag> pattern>
1120 : I<opcode, OOL, IOL, asmstr, itin> {
1126 let Pattern = pattern;
1128 bit RC = 0; // set by isDOT
1130 let Inst{6-10} = RS;
1131 let Inst{11-15} = RA;
1132 let Inst{16-20} = RB;
1133 let Inst{21-26} = MBE{4,3,2,1,0,5};
1134 let Inst{27-30} = xo;
1141 // VAForm_1 - DACB ordering.
1142 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1143 InstrItinClass itin, list<dag> pattern>
1144 : I<4, OOL, IOL, asmstr, itin> {
1150 let Pattern = pattern;
1152 let Inst{6-10} = VD;
1153 let Inst{11-15} = VA;
1154 let Inst{16-20} = VB;
1155 let Inst{21-25} = VC;
1156 let Inst{26-31} = xo;
1159 // VAForm_1a - DABC ordering.
1160 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1161 InstrItinClass itin, list<dag> pattern>
1162 : I<4, OOL, IOL, asmstr, itin> {
1168 let Pattern = pattern;
1170 let Inst{6-10} = VD;
1171 let Inst{11-15} = VA;
1172 let Inst{16-20} = VB;
1173 let Inst{21-25} = VC;
1174 let Inst{26-31} = xo;
1177 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1178 InstrItinClass itin, list<dag> pattern>
1179 : I<4, OOL, IOL, asmstr, itin> {
1185 let Pattern = pattern;
1187 let Inst{6-10} = VD;
1188 let Inst{11-15} = VA;
1189 let Inst{16-20} = VB;
1191 let Inst{22-25} = SH;
1192 let Inst{26-31} = xo;
1196 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1197 InstrItinClass itin, list<dag> pattern>
1198 : I<4, OOL, IOL, asmstr, itin> {
1203 let Pattern = pattern;
1205 let Inst{6-10} = VD;
1206 let Inst{11-15} = VA;
1207 let Inst{16-20} = VB;
1208 let Inst{21-31} = xo;
1211 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1212 InstrItinClass itin, list<dag> pattern>
1213 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1219 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1220 InstrItinClass itin, list<dag> pattern>
1221 : I<4, OOL, IOL, asmstr, itin> {
1225 let Pattern = pattern;
1227 let Inst{6-10} = VD;
1228 let Inst{11-15} = 0;
1229 let Inst{16-20} = VB;
1230 let Inst{21-31} = xo;
1233 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1234 InstrItinClass itin, list<dag> pattern>
1235 : I<4, OOL, IOL, asmstr, itin> {
1239 let Pattern = pattern;
1241 let Inst{6-10} = VD;
1242 let Inst{11-15} = IMM;
1243 let Inst{16-20} = 0;
1244 let Inst{21-31} = xo;
1247 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1248 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1249 InstrItinClass itin, list<dag> pattern>
1250 : I<4, OOL, IOL, asmstr, itin> {
1253 let Pattern = pattern;
1255 let Inst{6-10} = VD;
1256 let Inst{11-15} = 0;
1257 let Inst{16-20} = 0;
1258 let Inst{21-31} = xo;
1261 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1262 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1263 InstrItinClass itin, list<dag> pattern>
1264 : I<4, OOL, IOL, asmstr, itin> {
1267 let Pattern = pattern;
1270 let Inst{11-15} = 0;
1271 let Inst{16-20} = VB;
1272 let Inst{21-31} = xo;
1276 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1277 InstrItinClass itin, list<dag> pattern>
1278 : I<4, OOL, IOL, asmstr, itin> {
1284 let Pattern = pattern;
1286 let Inst{6-10} = VD;
1287 let Inst{11-15} = VA;
1288 let Inst{16-20} = VB;
1290 let Inst{22-31} = xo;
1293 //===----------------------------------------------------------------------===//
1294 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1295 : I<0, OOL, IOL, asmstr, NoItinerary> {
1296 let isCodeGenOnly = 1;
1298 let Pattern = pattern;