1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
388 // This is the same as XForm_base_r3xo, but the first two operands are swapped
389 // when code is emitted.
390 class XForm_base_r3xo_swapped
391 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
393 : I<opcode, OOL, IOL, asmstr, itin> {
398 bit RC = 0; // set by isDOT
400 let Inst{6-10} = RST;
403 let Inst{21-30} = xo;
408 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
409 InstrItinClass itin, list<dag> pattern>
410 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
412 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
413 InstrItinClass itin, list<dag> pattern>
414 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
418 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
419 InstrItinClass itin, list<dag> pattern>
420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
425 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
426 InstrItinClass itin, list<dag> pattern>
427 : I<opcode, OOL, IOL, asmstr, itin> {
432 let Pattern = pattern;
434 let Inst{6-10} = RST;
437 let Inst{21-30} = xo;
441 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
442 InstrItinClass itin, list<dag> pattern>
443 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
444 let Pattern = pattern;
447 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
448 InstrItinClass itin, list<dag> pattern>
449 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
451 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
452 InstrItinClass itin, list<dag> pattern>
453 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
454 let Pattern = pattern;
457 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
458 InstrItinClass itin, list<dag> pattern>
459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
461 let Pattern = pattern;
464 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
466 : I<opcode, OOL, IOL, asmstr, itin> {
475 let Inst{11-15} = RA;
476 let Inst{16-20} = RB;
477 let Inst{21-30} = xo;
481 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
483 : I<opcode, OOL, IOL, asmstr, itin> {
488 let Inst{12-15} = SR;
489 let Inst{21-30} = xo;
492 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
494 : I<opcode, OOL, IOL, asmstr, itin> {
498 let Inst{21-30} = xo;
501 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
503 : I<opcode, OOL, IOL, asmstr, itin> {
508 let Inst{16-20} = RB;
509 let Inst{21-30} = xo;
512 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
514 : I<opcode, OOL, IOL, asmstr, itin> {
520 let Inst{21-30} = xo;
523 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
525 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
529 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
531 : I<opcode, OOL, IOL, asmstr, itin> {
538 let Inst{11-15} = FRA;
539 let Inst{16-20} = FRB;
540 let Inst{21-30} = xo;
544 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
545 InstrItinClass itin, list<dag> pattern>
546 : I<opcode, OOL, IOL, asmstr, itin> {
547 let Pattern = pattern;
551 let Inst{21-30} = xo;
555 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
556 string asmstr, InstrItinClass itin, list<dag> pattern>
557 : I<opcode, OOL, IOL, asmstr, itin> {
560 let Pattern = pattern;
565 let Inst{21-30} = xo;
569 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
570 string asmstr, InstrItinClass itin, list<dag> pattern>
571 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
575 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
576 InstrItinClass itin, list<dag> pattern>
577 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
580 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
581 InstrItinClass itin, list<dag> pattern>
582 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
586 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
587 InstrItinClass itin, list<dag> pattern>
588 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
591 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
592 // numbers presumably relates to some document, but I haven't found it.
593 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
594 InstrItinClass itin, list<dag> pattern>
595 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
596 let Pattern = pattern;
598 bit RC = 0; // set by isDOT
600 let Inst{6-10} = RST;
602 let Inst{21-30} = xo;
605 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
606 InstrItinClass itin, list<dag> pattern>
607 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
608 let Pattern = pattern;
611 bit RC = 0; // set by isDOT
615 let Inst{21-30} = xo;
619 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
620 InstrItinClass itin, list<dag> pattern>
621 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
627 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
628 InstrItinClass itin, list<dag> pattern>
629 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
635 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
636 InstrItinClass itin, list<dag> pattern>
637 : I<opcode, OOL, IOL, asmstr, itin> {
642 let Pattern = pattern;
644 let Inst{6-10} = XT{4-0};
647 let Inst{21-30} = xo;
648 let Inst{31} = XT{5};
651 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
652 InstrItinClass itin, list<dag> pattern>
653 : I<opcode, OOL, IOL, asmstr, itin> {
657 let Pattern = pattern;
659 let Inst{6-10} = XT{4-0};
661 let Inst{16-20} = XB{4-0};
662 let Inst{21-29} = xo;
663 let Inst{30} = XB{5};
664 let Inst{31} = XT{5};
667 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
668 InstrItinClass itin, list<dag> pattern>
669 : I<opcode, OOL, IOL, asmstr, itin> {
673 let Pattern = pattern;
677 let Inst{16-20} = XB{4-0};
678 let Inst{21-29} = xo;
679 let Inst{30} = XB{5};
683 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
684 InstrItinClass itin, list<dag> pattern>
685 : I<opcode, OOL, IOL, asmstr, itin> {
690 let Pattern = pattern;
692 let Inst{6-10} = XT{4-0};
695 let Inst{16-20} = XB{4-0};
696 let Inst{21-29} = xo;
697 let Inst{30} = XB{5};
698 let Inst{31} = XT{5};
701 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
702 InstrItinClass itin, list<dag> pattern>
703 : I<opcode, OOL, IOL, asmstr, itin> {
708 let Pattern = pattern;
710 let Inst{6-10} = XT{4-0};
711 let Inst{11-15} = XA{4-0};
712 let Inst{16-20} = XB{4-0};
713 let Inst{21-28} = xo;
714 let Inst{29} = XA{5};
715 let Inst{30} = XB{5};
716 let Inst{31} = XT{5};
719 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
720 InstrItinClass itin, list<dag> pattern>
721 : I<opcode, OOL, IOL, asmstr, itin> {
726 let Pattern = pattern;
730 let Inst{11-15} = XA{4-0};
731 let Inst{16-20} = XB{4-0};
732 let Inst{21-28} = xo;
733 let Inst{29} = XA{5};
734 let Inst{30} = XB{5};
738 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
739 InstrItinClass itin, list<dag> pattern>
740 : I<opcode, OOL, IOL, asmstr, itin> {
746 let Pattern = pattern;
748 let Inst{6-10} = XT{4-0};
749 let Inst{11-15} = XA{4-0};
750 let Inst{16-20} = XB{4-0};
753 let Inst{24-28} = xo;
754 let Inst{29} = XA{5};
755 let Inst{30} = XB{5};
756 let Inst{31} = XT{5};
759 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
760 InstrItinClass itin, list<dag> pattern>
761 : I<opcode, OOL, IOL, asmstr, itin> {
766 let Pattern = pattern;
768 bit RC = 0; // set by isDOT
770 let Inst{6-10} = XT{4-0};
771 let Inst{11-15} = XA{4-0};
772 let Inst{16-20} = XB{4-0};
774 let Inst{22-28} = xo;
775 let Inst{29} = XA{5};
776 let Inst{30} = XB{5};
777 let Inst{31} = XT{5};
780 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
781 InstrItinClass itin, list<dag> pattern>
782 : I<opcode, OOL, IOL, asmstr, itin> {
788 let Pattern = pattern;
790 let Inst{6-10} = XT{4-0};
791 let Inst{11-15} = XA{4-0};
792 let Inst{16-20} = XB{4-0};
793 let Inst{21-25} = XC{4-0};
794 let Inst{26-27} = xo;
795 let Inst{28} = XC{5};
796 let Inst{29} = XA{5};
797 let Inst{30} = XB{5};
798 let Inst{31} = XT{5};
801 // DCB_Form - Form X instruction, used for dcb* instructions.
802 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
803 InstrItinClass itin, list<dag> pattern>
804 : I<31, OOL, IOL, asmstr, itin> {
808 let Pattern = pattern;
810 let Inst{6-10} = immfield;
813 let Inst{21-30} = xo;
818 // DSS_Form - Form X instruction, used for altivec dss* instructions.
819 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
820 InstrItinClass itin, list<dag> pattern>
821 : I<31, OOL, IOL, asmstr, itin> {
826 let Pattern = pattern;
830 let Inst{9-10} = STRM;
833 let Inst{21-30} = xo;
838 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
839 InstrItinClass itin, list<dag> pattern>
840 : I<opcode, OOL, IOL, asmstr, itin> {
845 let Pattern = pattern;
847 let Inst{6-10} = CRD;
848 let Inst{11-15} = CRA;
849 let Inst{16-20} = CRB;
850 let Inst{21-30} = xo;
854 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
855 InstrItinClass itin, list<dag> pattern>
856 : I<opcode, OOL, IOL, asmstr, itin> {
859 let Pattern = pattern;
861 let Inst{6-10} = CRD;
862 let Inst{11-15} = CRD;
863 let Inst{16-20} = CRD;
864 let Inst{21-30} = xo;
868 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
869 InstrItinClass itin, list<dag> pattern>
870 : I<opcode, OOL, IOL, asmstr, itin> {
875 let Pattern = pattern;
878 let Inst{11-15} = BI;
880 let Inst{19-20} = BH;
881 let Inst{21-30} = xo;
885 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
886 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
887 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
888 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
892 let BI{0-1} = BIBO{5-6};
893 let BI{2-4} = CR{0-2};
897 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
898 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
899 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
904 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
905 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
906 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
912 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
914 : I<opcode, OOL, IOL, asmstr, itin> {
920 let Inst{11-13} = BFA;
923 let Inst{21-30} = xo;
928 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
930 : I<opcode, OOL, IOL, asmstr, itin> {
935 let Inst{11} = SPR{4};
936 let Inst{12} = SPR{3};
937 let Inst{13} = SPR{2};
938 let Inst{14} = SPR{1};
939 let Inst{15} = SPR{0};
940 let Inst{16} = SPR{9};
941 let Inst{17} = SPR{8};
942 let Inst{18} = SPR{7};
943 let Inst{19} = SPR{6};
944 let Inst{20} = SPR{5};
945 let Inst{21-30} = xo;
949 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
950 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
951 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
955 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
957 : I<opcode, OOL, IOL, asmstr, itin> {
962 let Inst{21-30} = xo;
966 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
968 : I<opcode, OOL, IOL, asmstr, itin> {
974 let Inst{12-19} = FXM;
976 let Inst{21-30} = xo;
980 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
982 : I<opcode, OOL, IOL, asmstr, itin> {
988 let Inst{12-19} = FXM;
990 let Inst{21-30} = xo;
994 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
996 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
998 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
999 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1000 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1005 // This is probably 1.7.9, but I don't have the reference that uses this
1006 // numbering scheme...
1007 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1008 InstrItinClass itin, list<dag>pattern>
1009 : I<opcode, OOL, IOL, asmstr, itin> {
1013 bit RC = 0; // set by isDOT
1014 let Pattern = pattern;
1017 let Inst{7-14} = FM;
1019 let Inst{16-20} = rT;
1020 let Inst{21-30} = xo;
1024 // 1.7.10 XS-Form - SRADI.
1025 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1026 InstrItinClass itin, list<dag> pattern>
1027 : I<opcode, OOL, IOL, asmstr, itin> {
1032 bit RC = 0; // set by isDOT
1033 let Pattern = pattern;
1035 let Inst{6-10} = RS;
1036 let Inst{11-15} = A;
1037 let Inst{16-20} = SH{4,3,2,1,0};
1038 let Inst{21-29} = xo;
1039 let Inst{30} = SH{5};
1044 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1045 InstrItinClass itin, list<dag> pattern>
1046 : I<opcode, OOL, IOL, asmstr, itin> {
1051 let Pattern = pattern;
1053 bit RC = 0; // set by isDOT
1055 let Inst{6-10} = RT;
1056 let Inst{11-15} = RA;
1057 let Inst{16-20} = RB;
1059 let Inst{22-30} = xo;
1063 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1064 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1065 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1070 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1071 InstrItinClass itin, list<dag> pattern>
1072 : I<opcode, OOL, IOL, asmstr, itin> {
1078 let Pattern = pattern;
1080 bit RC = 0; // set by isDOT
1082 let Inst{6-10} = FRT;
1083 let Inst{11-15} = FRA;
1084 let Inst{16-20} = FRB;
1085 let Inst{21-25} = FRC;
1086 let Inst{26-30} = xo;
1090 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1091 InstrItinClass itin, list<dag> pattern>
1092 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1096 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1097 InstrItinClass itin, list<dag> pattern>
1098 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1102 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1103 InstrItinClass itin, list<dag> pattern>
1104 : I<opcode, OOL, IOL, asmstr, itin> {
1110 let Pattern = pattern;
1112 let Inst{6-10} = RT;
1113 let Inst{11-15} = RA;
1114 let Inst{16-20} = RB;
1115 let Inst{21-25} = COND;
1116 let Inst{26-30} = xo;
1121 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1122 InstrItinClass itin, list<dag> pattern>
1123 : I<opcode, OOL, IOL, asmstr, itin> {
1130 let Pattern = pattern;
1132 bit RC = 0; // set by isDOT
1134 let Inst{6-10} = RS;
1135 let Inst{11-15} = RA;
1136 let Inst{16-20} = RB;
1137 let Inst{21-25} = MB;
1138 let Inst{26-30} = ME;
1142 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1143 InstrItinClass itin, list<dag> pattern>
1144 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1148 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1149 InstrItinClass itin, list<dag> pattern>
1150 : I<opcode, OOL, IOL, asmstr, itin> {
1156 let Pattern = pattern;
1158 bit RC = 0; // set by isDOT
1160 let Inst{6-10} = RS;
1161 let Inst{11-15} = RA;
1162 let Inst{16-20} = SH{4,3,2,1,0};
1163 let Inst{21-26} = MBE{4,3,2,1,0,5};
1164 let Inst{27-29} = xo;
1165 let Inst{30} = SH{5};
1169 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1170 InstrItinClass itin, list<dag> pattern>
1171 : I<opcode, OOL, IOL, asmstr, itin> {
1177 let Pattern = pattern;
1179 bit RC = 0; // set by isDOT
1181 let Inst{6-10} = RS;
1182 let Inst{11-15} = RA;
1183 let Inst{16-20} = RB;
1184 let Inst{21-26} = MBE{4,3,2,1,0,5};
1185 let Inst{27-30} = xo;
1192 // VAForm_1 - DACB ordering.
1193 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1194 InstrItinClass itin, list<dag> pattern>
1195 : I<4, OOL, IOL, asmstr, itin> {
1201 let Pattern = pattern;
1203 let Inst{6-10} = VD;
1204 let Inst{11-15} = VA;
1205 let Inst{16-20} = VB;
1206 let Inst{21-25} = VC;
1207 let Inst{26-31} = xo;
1210 // VAForm_1a - DABC ordering.
1211 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1212 InstrItinClass itin, list<dag> pattern>
1213 : I<4, OOL, IOL, asmstr, itin> {
1219 let Pattern = pattern;
1221 let Inst{6-10} = VD;
1222 let Inst{11-15} = VA;
1223 let Inst{16-20} = VB;
1224 let Inst{21-25} = VC;
1225 let Inst{26-31} = xo;
1228 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1229 InstrItinClass itin, list<dag> pattern>
1230 : I<4, OOL, IOL, asmstr, itin> {
1236 let Pattern = pattern;
1238 let Inst{6-10} = VD;
1239 let Inst{11-15} = VA;
1240 let Inst{16-20} = VB;
1242 let Inst{22-25} = SH;
1243 let Inst{26-31} = xo;
1247 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1248 InstrItinClass itin, list<dag> pattern>
1249 : I<4, OOL, IOL, asmstr, itin> {
1254 let Pattern = pattern;
1256 let Inst{6-10} = VD;
1257 let Inst{11-15} = VA;
1258 let Inst{16-20} = VB;
1259 let Inst{21-31} = xo;
1262 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1263 InstrItinClass itin, list<dag> pattern>
1264 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1270 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1271 InstrItinClass itin, list<dag> pattern>
1272 : I<4, OOL, IOL, asmstr, itin> {
1276 let Pattern = pattern;
1278 let Inst{6-10} = VD;
1279 let Inst{11-15} = 0;
1280 let Inst{16-20} = VB;
1281 let Inst{21-31} = xo;
1284 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1285 InstrItinClass itin, list<dag> pattern>
1286 : I<4, OOL, IOL, asmstr, itin> {
1290 let Pattern = pattern;
1292 let Inst{6-10} = VD;
1293 let Inst{11-15} = IMM;
1294 let Inst{16-20} = 0;
1295 let Inst{21-31} = xo;
1298 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1299 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1300 InstrItinClass itin, list<dag> pattern>
1301 : I<4, OOL, IOL, asmstr, itin> {
1304 let Pattern = pattern;
1306 let Inst{6-10} = VD;
1307 let Inst{11-15} = 0;
1308 let Inst{16-20} = 0;
1309 let Inst{21-31} = xo;
1312 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1313 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1314 InstrItinClass itin, list<dag> pattern>
1315 : I<4, OOL, IOL, asmstr, itin> {
1318 let Pattern = pattern;
1321 let Inst{11-15} = 0;
1322 let Inst{16-20} = VB;
1323 let Inst{21-31} = xo;
1327 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1328 InstrItinClass itin, list<dag> pattern>
1329 : I<4, OOL, IOL, asmstr, itin> {
1335 let Pattern = pattern;
1337 let Inst{6-10} = VD;
1338 let Inst{11-15} = VA;
1339 let Inst{16-20} = VB;
1341 let Inst{22-31} = xo;
1344 //===----------------------------------------------------------------------===//
1345 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1346 : I<0, OOL, IOL, asmstr, NoItinerary> {
1347 let isCodeGenOnly = 1;
1349 let Pattern = pattern;