1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
39 // Fields used for relation models.
42 // For cases where multiple instruction definitions really represent the
43 // same underlying instruction but with one definition for 64-bit arguments
44 // and one for 32-bit arguments, this bit breaks the degeneracy between
45 // the two forms and allows TableGen to generate mapping tables.
46 bit Interpretation64Bit = 0;
49 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
50 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
51 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
52 class PPC970_MicroCode;
54 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
55 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
56 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
57 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
58 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
59 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
60 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
61 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
63 // Two joined instructions; used to emit two adjacent instructions as one.
64 // The itinerary from the first instruction is used for scheduling and
66 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
71 bit PPC64 = 0; // Default value, override with isPPC64
73 let Namespace = "PPC";
74 let Inst{0-5} = opcode1;
75 let Inst{32-37} = opcode2;
76 let OutOperandList = OOL;
77 let InOperandList = IOL;
78 let AsmString = asmstr;
81 bits<1> PPC970_First = 0;
82 bits<1> PPC970_Single = 0;
83 bits<1> PPC970_Cracked = 0;
84 bits<3> PPC970_Unit = 0;
86 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
87 /// these must be reflected there! See comments there for what these are.
88 let TSFlags{0} = PPC970_First;
89 let TSFlags{1} = PPC970_Single;
90 let TSFlags{2} = PPC970_Cracked;
91 let TSFlags{5-3} = PPC970_Unit;
93 // Fields used for relation models.
95 bit Interpretation64Bit = 0;
99 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
100 InstrItinClass itin, list<dag> pattern>
101 : I<opcode, OOL, IOL, asmstr, itin> {
102 let Pattern = pattern;
111 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
112 : I<opcode, OOL, IOL, asmstr, BrB> {
113 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
118 let BI{0-1} = BIBO{5-6};
119 let BI{2-4} = CR{0-2};
121 let Inst{6-10} = BIBO{4-0};
122 let Inst{11-15} = BI;
123 let Inst{16-29} = BD;
128 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
130 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
136 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
137 dag OOL, dag IOL, string asmstr>
138 : I<opcode, OOL, IOL, asmstr, BrB> {
142 let Inst{11-15} = bi;
143 let Inst{16-29} = BD;
149 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
150 InstrItinClass itin, list<dag> pattern>
151 : I<opcode, OOL, IOL, asmstr, itin> {
156 let Pattern = pattern;
163 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
164 InstrItinClass itin, list<dag> pattern>
165 : I<opcode, OOL, IOL, asmstr, itin> {
169 let Pattern = pattern;
172 let Inst{11-15} = Addr{20-16}; // Base Reg
173 let Inst{16-31} = Addr{15-0}; // Displacement
176 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
177 InstrItinClass itin, list<dag> pattern>
178 : I<opcode, OOL, IOL, asmstr, itin> {
183 let Pattern = pattern;
191 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
192 InstrItinClass itin, list<dag> pattern>
193 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
195 // Even though ADDICo does not really have an RC bit, provide
196 // the declaration of one here so that isDOT has something to set.
200 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
201 InstrItinClass itin, list<dag> pattern>
202 : I<opcode, OOL, IOL, asmstr, itin> {
206 let Pattern = pattern;
213 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
214 InstrItinClass itin, list<dag> pattern>
215 : I<opcode, OOL, IOL, asmstr, itin> {
220 let Pattern = pattern;
227 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
228 InstrItinClass itin, list<dag> pattern>
229 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
234 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
235 dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
241 let Pattern = pattern;
249 let Inst{43-47} = Addr{20-16}; // Base Reg
250 let Inst{48-63} = Addr{15-0}; // Displacement
253 // This is used to emit BL8+NOP.
254 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
255 dag OOL, dag IOL, string asmstr,
256 InstrItinClass itin, list<dag> pattern>
257 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
258 OOL, IOL, asmstr, itin, pattern> {
263 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
265 : I<opcode, OOL, IOL, asmstr, itin> {
274 let Inst{11-15} = RA;
278 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
280 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
284 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
286 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
288 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
290 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
296 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
297 InstrItinClass itin, list<dag> pattern>
298 : I<opcode, OOL, IOL, asmstr, itin> {
302 let Pattern = pattern;
304 let Inst{6-10} = RST;
305 let Inst{11-15} = DS_RA{18-14}; // Register #
306 let Inst{16-29} = DS_RA{13-0}; // Displacement.
307 let Inst{30-31} = xo;
310 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
311 InstrItinClass itin, list<dag> pattern>
312 : I<opcode, OOL, IOL, asmstr, itin> {
317 let Pattern = pattern;
319 let Inst{6-10} = RST;
320 let Inst{11-15} = RA;
321 let Inst{16-29} = DS;
322 let Inst{30-31} = xo;
326 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
327 InstrItinClass itin, list<dag> pattern>
328 : I<opcode, OOL, IOL, asmstr, itin> {
333 let Pattern = pattern;
335 bit RC = 0; // set by isDOT
337 let Inst{6-10} = RST;
340 let Inst{21-30} = xo;
344 // This is the same as XForm_base_r3xo, but the first two operands are swapped
345 // when code is emitted.
346 class XForm_base_r3xo_swapped
347 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
349 : I<opcode, OOL, IOL, asmstr, itin> {
354 bit RC = 0; // set by isDOT
356 let Inst{6-10} = RST;
359 let Inst{21-30} = xo;
364 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
365 InstrItinClass itin, list<dag> pattern>
366 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
368 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
369 InstrItinClass itin, list<dag> pattern>
370 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
371 let Pattern = pattern;
374 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
375 InstrItinClass itin, list<dag> pattern>
376 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
378 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
379 InstrItinClass itin, list<dag> pattern>
380 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
381 let Pattern = pattern;
384 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
385 InstrItinClass itin, list<dag> pattern>
386 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
388 let Pattern = pattern;
391 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
393 : I<opcode, OOL, IOL, asmstr, itin> {
402 let Inst{11-15} = RA;
403 let Inst{16-20} = RB;
404 let Inst{21-30} = xo;
408 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
410 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
414 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
416 : I<opcode, OOL, IOL, asmstr, itin> {
423 let Inst{11-15} = FRA;
424 let Inst{16-20} = FRB;
425 let Inst{21-30} = xo;
429 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
430 InstrItinClass itin, list<dag> pattern>
431 : I<opcode, OOL, IOL, asmstr, itin> {
432 let Pattern = pattern;
436 let Inst{21-30} = xo;
440 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
441 string asmstr, InstrItinClass itin, list<dag> pattern>
442 : I<opcode, OOL, IOL, asmstr, itin> {
443 let Pattern = pattern;
447 let Inst{21-30} = xo;
451 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
452 InstrItinClass itin, list<dag> pattern>
453 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
456 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
457 InstrItinClass itin, list<dag> pattern>
458 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
462 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
463 InstrItinClass itin, list<dag> pattern>
464 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
467 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
468 // numbers presumably relates to some document, but I haven't found it.
469 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
470 InstrItinClass itin, list<dag> pattern>
471 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
472 let Pattern = pattern;
474 bit RC = 0; // set by isDOT
476 let Inst{6-10} = RST;
478 let Inst{21-30} = xo;
481 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
482 InstrItinClass itin, list<dag> pattern>
483 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
484 let Pattern = pattern;
487 bit RC = 0; // set by isDOT
491 let Inst{21-30} = xo;
495 // DCB_Form - Form X instruction, used for dcb* instructions.
496 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
497 InstrItinClass itin, list<dag> pattern>
498 : I<31, OOL, IOL, asmstr, itin> {
502 let Pattern = pattern;
504 let Inst{6-10} = immfield;
507 let Inst{21-30} = xo;
512 // DSS_Form - Form X instruction, used for altivec dss* instructions.
513 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
514 InstrItinClass itin, list<dag> pattern>
515 : I<31, OOL, IOL, asmstr, itin> {
521 let Pattern = pattern;
525 let Inst{9-10} = STRM;
528 let Inst{21-30} = xo;
533 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
534 InstrItinClass itin, list<dag> pattern>
535 : I<opcode, OOL, IOL, asmstr, itin> {
540 let Pattern = pattern;
542 let Inst{6-10} = CRD;
543 let Inst{11-15} = CRA;
544 let Inst{16-20} = CRB;
545 let Inst{21-30} = xo;
549 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
550 InstrItinClass itin, list<dag> pattern>
551 : I<opcode, OOL, IOL, asmstr, itin> {
554 let Pattern = pattern;
556 let Inst{6-10} = CRD;
557 let Inst{11-15} = CRD;
558 let Inst{16-20} = CRD;
559 let Inst{21-30} = xo;
563 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
564 InstrItinClass itin, list<dag> pattern>
565 : I<opcode, OOL, IOL, asmstr, itin> {
570 let Pattern = pattern;
573 let Inst{11-15} = BI;
575 let Inst{19-20} = BH;
576 let Inst{21-30} = xo;
580 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
581 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
582 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
583 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
587 let BI{0-1} = BIBO{5-6};
588 let BI{2-4} = CR{0-2};
593 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
594 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
595 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
601 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
603 : I<opcode, OOL, IOL, asmstr, itin> {
609 let Inst{11-13} = BFA;
612 let Inst{21-30} = xo;
617 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
619 : I<opcode, OOL, IOL, asmstr, itin> {
624 let Inst{11} = SPR{4};
625 let Inst{12} = SPR{3};
626 let Inst{13} = SPR{2};
627 let Inst{14} = SPR{1};
628 let Inst{15} = SPR{0};
629 let Inst{16} = SPR{9};
630 let Inst{17} = SPR{8};
631 let Inst{18} = SPR{7};
632 let Inst{19} = SPR{6};
633 let Inst{20} = SPR{5};
634 let Inst{21-30} = xo;
638 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
639 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
640 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
644 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
646 : I<opcode, OOL, IOL, asmstr, itin> {
651 let Inst{21-30} = xo;
655 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
657 : I<opcode, OOL, IOL, asmstr, itin> {
663 let Inst{12-19} = FXM;
665 let Inst{21-30} = xo;
669 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
671 : I<opcode, OOL, IOL, asmstr, itin> {
677 let Inst{12-19} = FXM;
679 let Inst{21-30} = xo;
683 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
685 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
687 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
688 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
689 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
694 // This is probably 1.7.9, but I don't have the reference that uses this
695 // numbering scheme...
696 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
697 InstrItinClass itin, list<dag>pattern>
698 : I<opcode, OOL, IOL, asmstr, itin> {
702 bit RC = 0; // set by isDOT
703 let Pattern = pattern;
708 let Inst{16-20} = rT;
709 let Inst{21-30} = xo;
713 // 1.7.10 XS-Form - SRADI.
714 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
715 InstrItinClass itin, list<dag> pattern>
716 : I<opcode, OOL, IOL, asmstr, itin> {
721 bit RC = 0; // set by isDOT
722 let Pattern = pattern;
726 let Inst{16-20} = SH{4,3,2,1,0};
727 let Inst{21-29} = xo;
728 let Inst{30} = SH{5};
733 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
734 InstrItinClass itin, list<dag> pattern>
735 : I<opcode, OOL, IOL, asmstr, itin> {
740 let Pattern = pattern;
742 bit RC = 0; // set by isDOT
745 let Inst{11-15} = RA;
746 let Inst{16-20} = RB;
748 let Inst{22-30} = xo;
752 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
753 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
754 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
759 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
760 InstrItinClass itin, list<dag> pattern>
761 : I<opcode, OOL, IOL, asmstr, itin> {
767 let Pattern = pattern;
769 bit RC = 0; // set by isDOT
771 let Inst{6-10} = FRT;
772 let Inst{11-15} = FRA;
773 let Inst{16-20} = FRB;
774 let Inst{21-25} = FRC;
775 let Inst{26-30} = xo;
779 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
780 InstrItinClass itin, list<dag> pattern>
781 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
785 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
786 InstrItinClass itin, list<dag> pattern>
787 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
791 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
792 InstrItinClass itin, list<dag> pattern>
793 : I<opcode, OOL, IOL, asmstr, itin> {
799 let Pattern = pattern;
802 let Inst{11-15} = RA;
803 let Inst{16-20} = RB;
804 let Inst{21-25} = COND;
805 let Inst{26-30} = xo;
810 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
811 InstrItinClass itin, list<dag> pattern>
812 : I<opcode, OOL, IOL, asmstr, itin> {
819 let Pattern = pattern;
821 bit RC = 0; // set by isDOT
824 let Inst{11-15} = RA;
825 let Inst{16-20} = RB;
826 let Inst{21-25} = MB;
827 let Inst{26-30} = ME;
831 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
832 InstrItinClass itin, list<dag> pattern>
833 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
837 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
838 InstrItinClass itin, list<dag> pattern>
839 : I<opcode, OOL, IOL, asmstr, itin> {
845 let Pattern = pattern;
847 bit RC = 0; // set by isDOT
850 let Inst{11-15} = RA;
851 let Inst{16-20} = SH{4,3,2,1,0};
852 let Inst{21-26} = MBE{4,3,2,1,0,5};
853 let Inst{27-29} = xo;
854 let Inst{30} = SH{5};
862 // VAForm_1 - DACB ordering.
863 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
864 InstrItinClass itin, list<dag> pattern>
865 : I<4, OOL, IOL, asmstr, itin> {
871 let Pattern = pattern;
874 let Inst{11-15} = VA;
875 let Inst{16-20} = VB;
876 let Inst{21-25} = VC;
877 let Inst{26-31} = xo;
880 // VAForm_1a - DABC ordering.
881 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
882 InstrItinClass itin, list<dag> pattern>
883 : I<4, OOL, IOL, asmstr, itin> {
889 let Pattern = pattern;
892 let Inst{11-15} = VA;
893 let Inst{16-20} = VB;
894 let Inst{21-25} = VC;
895 let Inst{26-31} = xo;
898 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
899 InstrItinClass itin, list<dag> pattern>
900 : I<4, OOL, IOL, asmstr, itin> {
906 let Pattern = pattern;
909 let Inst{11-15} = VA;
910 let Inst{16-20} = VB;
912 let Inst{22-25} = SH;
913 let Inst{26-31} = xo;
917 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
918 InstrItinClass itin, list<dag> pattern>
919 : I<4, OOL, IOL, asmstr, itin> {
924 let Pattern = pattern;
927 let Inst{11-15} = VA;
928 let Inst{16-20} = VB;
929 let Inst{21-31} = xo;
932 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
933 InstrItinClass itin, list<dag> pattern>
934 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
940 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
941 InstrItinClass itin, list<dag> pattern>
942 : I<4, OOL, IOL, asmstr, itin> {
946 let Pattern = pattern;
950 let Inst{16-20} = VB;
951 let Inst{21-31} = xo;
954 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
955 InstrItinClass itin, list<dag> pattern>
956 : I<4, OOL, IOL, asmstr, itin> {
960 let Pattern = pattern;
963 let Inst{11-15} = IMM;
965 let Inst{21-31} = xo;
968 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
969 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
970 InstrItinClass itin, list<dag> pattern>
971 : I<4, OOL, IOL, asmstr, itin> {
974 let Pattern = pattern;
979 let Inst{21-31} = xo;
982 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
983 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
984 InstrItinClass itin, list<dag> pattern>
985 : I<4, OOL, IOL, asmstr, itin> {
988 let Pattern = pattern;
992 let Inst{16-20} = VB;
993 let Inst{21-31} = xo;
997 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
998 InstrItinClass itin, list<dag> pattern>
999 : I<4, OOL, IOL, asmstr, itin> {
1005 let Pattern = pattern;
1007 let Inst{6-10} = VD;
1008 let Inst{11-15} = VA;
1009 let Inst{16-20} = VB;
1011 let Inst{22-31} = xo;
1014 //===----------------------------------------------------------------------===//
1015 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1016 : I<0, OOL, IOL, asmstr, NoItinerary> {
1017 let isCodeGenOnly = 1;
1019 let Pattern = pattern;