1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
39 // Fields used for relation models.
41 bit Interpretation64Bit = 0;
44 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
45 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
46 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
47 class PPC970_MicroCode;
49 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
50 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
51 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
52 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
53 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
54 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
55 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
56 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
58 // Two joined instructions; used to emit two adjacent instructions as one.
59 // The itinerary from the first instruction is used for scheduling and
61 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
66 bit PPC64 = 0; // Default value, override with isPPC64
68 let Namespace = "PPC";
69 let Inst{0-5} = opcode1;
70 let Inst{32-37} = opcode2;
71 let OutOperandList = OOL;
72 let InOperandList = IOL;
73 let AsmString = asmstr;
76 bits<1> PPC970_First = 0;
77 bits<1> PPC970_Single = 0;
78 bits<1> PPC970_Cracked = 0;
79 bits<3> PPC970_Unit = 0;
81 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
82 /// these must be reflected there! See comments there for what these are.
83 let TSFlags{0} = PPC970_First;
84 let TSFlags{1} = PPC970_Single;
85 let TSFlags{2} = PPC970_Cracked;
86 let TSFlags{5-3} = PPC970_Unit;
88 // Fields used for relation models.
90 bit Interpretation64Bit = 0;
94 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
95 InstrItinClass itin, list<dag> pattern>
96 : I<opcode, OOL, IOL, asmstr, itin> {
97 let Pattern = pattern;
106 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
107 : I<opcode, OOL, IOL, asmstr, BrB> {
108 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
113 let BI{0-1} = BIBO{5-6};
114 let BI{2-4} = CR{0-2};
116 let Inst{6-10} = BIBO{4-0};
117 let Inst{11-15} = BI;
118 let Inst{16-29} = BD;
123 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
125 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
131 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
132 dag OOL, dag IOL, string asmstr>
133 : I<opcode, OOL, IOL, asmstr, BrB> {
137 let Inst{11-15} = bi;
138 let Inst{16-29} = BD;
144 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
145 InstrItinClass itin, list<dag> pattern>
146 : I<opcode, OOL, IOL, asmstr, itin> {
151 let Pattern = pattern;
158 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
159 InstrItinClass itin, list<dag> pattern>
160 : I<opcode, OOL, IOL, asmstr, itin> {
164 let Pattern = pattern;
167 let Inst{11-15} = Addr{20-16}; // Base Reg
168 let Inst{16-31} = Addr{15-0}; // Displacement
171 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
172 InstrItinClass itin, list<dag> pattern>
173 : I<opcode, OOL, IOL, asmstr, itin> {
178 let Pattern = pattern;
186 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
187 InstrItinClass itin, list<dag> pattern>
188 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
190 // Even though ADDICo does not really have an RC bit, provide
191 // the declaration of one here so that isDOT has something to set.
195 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
196 InstrItinClass itin, list<dag> pattern>
197 : I<opcode, OOL, IOL, asmstr, itin> {
201 let Pattern = pattern;
208 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
209 InstrItinClass itin, list<dag> pattern>
210 : I<opcode, OOL, IOL, asmstr, itin> {
215 let Pattern = pattern;
222 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
223 InstrItinClass itin, list<dag> pattern>
224 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
229 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
230 dag OOL, dag IOL, string asmstr,
231 InstrItinClass itin, list<dag> pattern>
232 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
236 let Pattern = pattern;
244 let Inst{43-47} = Addr{20-16}; // Base Reg
245 let Inst{48-63} = Addr{15-0}; // Displacement
248 // This is used to emit BL8+NOP.
249 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
250 dag OOL, dag IOL, string asmstr,
251 InstrItinClass itin, list<dag> pattern>
252 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
253 OOL, IOL, asmstr, itin, pattern> {
258 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
260 : I<opcode, OOL, IOL, asmstr, itin> {
269 let Inst{11-15} = RA;
273 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
275 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
279 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
281 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
283 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
285 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
291 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
292 InstrItinClass itin, list<dag> pattern>
293 : I<opcode, OOL, IOL, asmstr, itin> {
297 let Pattern = pattern;
299 let Inst{6-10} = RST;
300 let Inst{11-15} = DS_RA{18-14}; // Register #
301 let Inst{16-29} = DS_RA{13-0}; // Displacement.
302 let Inst{30-31} = xo;
305 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
306 InstrItinClass itin, list<dag> pattern>
307 : I<opcode, OOL, IOL, asmstr, itin> {
312 let Pattern = pattern;
314 let Inst{6-10} = RST;
315 let Inst{11-15} = RA;
316 let Inst{16-29} = DS;
317 let Inst{30-31} = xo;
321 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
322 InstrItinClass itin, list<dag> pattern>
323 : I<opcode, OOL, IOL, asmstr, itin> {
328 let Pattern = pattern;
330 bit RC = 0; // set by isDOT
332 let Inst{6-10} = RST;
335 let Inst{21-30} = xo;
339 // This is the same as XForm_base_r3xo, but the first two operands are swapped
340 // when code is emitted.
341 class XForm_base_r3xo_swapped
342 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
344 : I<opcode, OOL, IOL, asmstr, itin> {
349 bit RC = 0; // set by isDOT
351 let Inst{6-10} = RST;
354 let Inst{21-30} = xo;
359 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
360 InstrItinClass itin, list<dag> pattern>
361 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
363 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
364 InstrItinClass itin, list<dag> pattern>
365 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
366 let Pattern = pattern;
369 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
370 InstrItinClass itin, list<dag> pattern>
371 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
373 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
374 InstrItinClass itin, list<dag> pattern>
375 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
376 let Pattern = pattern;
379 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
380 InstrItinClass itin, list<dag> pattern>
381 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
383 let Pattern = pattern;
386 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
388 : I<opcode, OOL, IOL, asmstr, itin> {
397 let Inst{11-15} = RA;
398 let Inst{16-20} = RB;
399 let Inst{21-30} = xo;
403 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
405 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
409 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
411 : I<opcode, OOL, IOL, asmstr, itin> {
418 let Inst{11-15} = FRA;
419 let Inst{16-20} = FRB;
420 let Inst{21-30} = xo;
424 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
425 InstrItinClass itin, list<dag> pattern>
426 : I<opcode, OOL, IOL, asmstr, itin> {
427 let Pattern = pattern;
431 let Inst{21-30} = xo;
435 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
436 string asmstr, InstrItinClass itin, list<dag> pattern>
437 : I<opcode, OOL, IOL, asmstr, itin> {
438 let Pattern = pattern;
442 let Inst{21-30} = xo;
446 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
447 InstrItinClass itin, list<dag> pattern>
448 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
451 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
452 InstrItinClass itin, list<dag> pattern>
453 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
457 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
458 InstrItinClass itin, list<dag> pattern>
459 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
462 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
463 // numbers presumably relates to some document, but I haven't found it.
464 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
465 InstrItinClass itin, list<dag> pattern>
466 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
467 let Pattern = pattern;
469 bit RC = 0; // set by isDOT
471 let Inst{6-10} = RST;
473 let Inst{21-30} = xo;
476 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
477 InstrItinClass itin, list<dag> pattern>
478 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
479 let Pattern = pattern;
482 bit RC = 0; // set by isDOT
486 let Inst{21-30} = xo;
490 // DCB_Form - Form X instruction, used for dcb* instructions.
491 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
492 InstrItinClass itin, list<dag> pattern>
493 : I<31, OOL, IOL, asmstr, itin> {
497 let Pattern = pattern;
499 let Inst{6-10} = immfield;
502 let Inst{21-30} = xo;
507 // DSS_Form - Form X instruction, used for altivec dss* instructions.
508 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
509 InstrItinClass itin, list<dag> pattern>
510 : I<31, OOL, IOL, asmstr, itin> {
516 let Pattern = pattern;
520 let Inst{9-10} = STRM;
523 let Inst{21-30} = xo;
528 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
529 InstrItinClass itin, list<dag> pattern>
530 : I<opcode, OOL, IOL, asmstr, itin> {
535 let Pattern = pattern;
537 let Inst{6-10} = CRD;
538 let Inst{11-15} = CRA;
539 let Inst{16-20} = CRB;
540 let Inst{21-30} = xo;
544 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
545 InstrItinClass itin, list<dag> pattern>
546 : I<opcode, OOL, IOL, asmstr, itin> {
549 let Pattern = pattern;
551 let Inst{6-10} = CRD;
552 let Inst{11-15} = CRD;
553 let Inst{16-20} = CRD;
554 let Inst{21-30} = xo;
558 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
559 InstrItinClass itin, list<dag> pattern>
560 : I<opcode, OOL, IOL, asmstr, itin> {
565 let Pattern = pattern;
568 let Inst{11-15} = BI;
570 let Inst{19-20} = BH;
571 let Inst{21-30} = xo;
575 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
576 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
577 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
578 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
582 let BI{0-1} = BIBO{5-6};
583 let BI{2-4} = CR{0-2};
588 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
589 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
590 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
596 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
598 : I<opcode, OOL, IOL, asmstr, itin> {
604 let Inst{11-13} = BFA;
607 let Inst{21-30} = xo;
612 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
614 : I<opcode, OOL, IOL, asmstr, itin> {
619 let Inst{11} = SPR{4};
620 let Inst{12} = SPR{3};
621 let Inst{13} = SPR{2};
622 let Inst{14} = SPR{1};
623 let Inst{15} = SPR{0};
624 let Inst{16} = SPR{9};
625 let Inst{17} = SPR{8};
626 let Inst{18} = SPR{7};
627 let Inst{19} = SPR{6};
628 let Inst{20} = SPR{5};
629 let Inst{21-30} = xo;
633 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
634 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
635 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
639 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
641 : I<opcode, OOL, IOL, asmstr, itin> {
646 let Inst{21-30} = xo;
650 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
652 : I<opcode, OOL, IOL, asmstr, itin> {
658 let Inst{12-19} = FXM;
660 let Inst{21-30} = xo;
664 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
666 : I<opcode, OOL, IOL, asmstr, itin> {
672 let Inst{12-19} = FXM;
674 let Inst{21-30} = xo;
678 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
680 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
682 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
683 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
684 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
689 // This is probably 1.7.9, but I don't have the reference that uses this
690 // numbering scheme...
691 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
692 InstrItinClass itin, list<dag>pattern>
693 : I<opcode, OOL, IOL, asmstr, itin> {
697 bit RC = 0; // set by isDOT
698 let Pattern = pattern;
703 let Inst{16-20} = rT;
704 let Inst{21-30} = xo;
708 // 1.7.10 XS-Form - SRADI.
709 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
710 InstrItinClass itin, list<dag> pattern>
711 : I<opcode, OOL, IOL, asmstr, itin> {
716 bit RC = 0; // set by isDOT
717 let Pattern = pattern;
721 let Inst{16-20} = SH{4,3,2,1,0};
722 let Inst{21-29} = xo;
723 let Inst{30} = SH{5};
728 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
729 InstrItinClass itin, list<dag> pattern>
730 : I<opcode, OOL, IOL, asmstr, itin> {
735 let Pattern = pattern;
737 bit RC = 0; // set by isDOT
740 let Inst{11-15} = RA;
741 let Inst{16-20} = RB;
743 let Inst{22-30} = xo;
747 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
748 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
749 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
754 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
755 InstrItinClass itin, list<dag> pattern>
756 : I<opcode, OOL, IOL, asmstr, itin> {
762 let Pattern = pattern;
764 bit RC = 0; // set by isDOT
766 let Inst{6-10} = FRT;
767 let Inst{11-15} = FRA;
768 let Inst{16-20} = FRB;
769 let Inst{21-25} = FRC;
770 let Inst{26-30} = xo;
774 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
775 InstrItinClass itin, list<dag> pattern>
776 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
780 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
781 InstrItinClass itin, list<dag> pattern>
782 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
786 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
787 InstrItinClass itin, list<dag> pattern>
788 : I<opcode, OOL, IOL, asmstr, itin> {
794 let Pattern = pattern;
797 let Inst{11-15} = RA;
798 let Inst{16-20} = RB;
799 let Inst{21-25} = COND;
800 let Inst{26-30} = xo;
805 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
806 InstrItinClass itin, list<dag> pattern>
807 : I<opcode, OOL, IOL, asmstr, itin> {
814 let Pattern = pattern;
816 bit RC = 0; // set by isDOT
819 let Inst{11-15} = RA;
820 let Inst{16-20} = RB;
821 let Inst{21-25} = MB;
822 let Inst{26-30} = ME;
826 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
827 InstrItinClass itin, list<dag> pattern>
828 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
832 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
833 InstrItinClass itin, list<dag> pattern>
834 : I<opcode, OOL, IOL, asmstr, itin> {
840 let Pattern = pattern;
842 bit RC = 0; // set by isDOT
845 let Inst{11-15} = RA;
846 let Inst{16-20} = SH{4,3,2,1,0};
847 let Inst{21-26} = MBE{4,3,2,1,0,5};
848 let Inst{27-29} = xo;
849 let Inst{30} = SH{5};
857 // VAForm_1 - DACB ordering.
858 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
859 InstrItinClass itin, list<dag> pattern>
860 : I<4, OOL, IOL, asmstr, itin> {
866 let Pattern = pattern;
869 let Inst{11-15} = VA;
870 let Inst{16-20} = VB;
871 let Inst{21-25} = VC;
872 let Inst{26-31} = xo;
875 // VAForm_1a - DABC ordering.
876 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
877 InstrItinClass itin, list<dag> pattern>
878 : I<4, OOL, IOL, asmstr, itin> {
884 let Pattern = pattern;
887 let Inst{11-15} = VA;
888 let Inst{16-20} = VB;
889 let Inst{21-25} = VC;
890 let Inst{26-31} = xo;
893 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
894 InstrItinClass itin, list<dag> pattern>
895 : I<4, OOL, IOL, asmstr, itin> {
901 let Pattern = pattern;
904 let Inst{11-15} = VA;
905 let Inst{16-20} = VB;
907 let Inst{22-25} = SH;
908 let Inst{26-31} = xo;
912 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
913 InstrItinClass itin, list<dag> pattern>
914 : I<4, OOL, IOL, asmstr, itin> {
919 let Pattern = pattern;
922 let Inst{11-15} = VA;
923 let Inst{16-20} = VB;
924 let Inst{21-31} = xo;
927 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
928 InstrItinClass itin, list<dag> pattern>
929 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
935 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
936 InstrItinClass itin, list<dag> pattern>
937 : I<4, OOL, IOL, asmstr, itin> {
941 let Pattern = pattern;
945 let Inst{16-20} = VB;
946 let Inst{21-31} = xo;
949 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
950 InstrItinClass itin, list<dag> pattern>
951 : I<4, OOL, IOL, asmstr, itin> {
955 let Pattern = pattern;
958 let Inst{11-15} = IMM;
960 let Inst{21-31} = xo;
963 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
964 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
965 InstrItinClass itin, list<dag> pattern>
966 : I<4, OOL, IOL, asmstr, itin> {
969 let Pattern = pattern;
974 let Inst{21-31} = xo;
977 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
978 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
979 InstrItinClass itin, list<dag> pattern>
980 : I<4, OOL, IOL, asmstr, itin> {
983 let Pattern = pattern;
987 let Inst{16-20} = VB;
988 let Inst{21-31} = xo;
992 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
993 InstrItinClass itin, list<dag> pattern>
994 : I<4, OOL, IOL, asmstr, itin> {
1000 let Pattern = pattern;
1002 let Inst{6-10} = VD;
1003 let Inst{11-15} = VA;
1004 let Inst{16-20} = VB;
1006 let Inst{22-31} = xo;
1009 //===----------------------------------------------------------------------===//
1010 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1011 : I<0, OOL, IOL, asmstr, NoItinerary> {
1012 let isCodeGenOnly = 1;
1014 let Pattern = pattern;