1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
40 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
41 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
42 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
43 class PPC970_MicroCode;
45 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
46 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
47 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
48 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
49 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
50 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
51 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
52 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
54 // Two joined instructions; used to emit two adjacent instructions as one.
55 // The itinerary from the first instruction is used for scheduling and
57 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
62 bit PPC64 = 0; // Default value, override with isPPC64
64 let Namespace = "PPC";
65 let Inst{0-5} = opcode1;
66 let Inst{32-37} = opcode2;
67 let OutOperandList = OOL;
68 let InOperandList = IOL;
69 let AsmString = asmstr;
72 bits<1> PPC970_First = 0;
73 bits<1> PPC970_Single = 0;
74 bits<1> PPC970_Cracked = 0;
75 bits<3> PPC970_Unit = 0;
77 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
78 /// these must be reflected there! See comments there for what these are.
79 let TSFlags{0} = PPC970_First;
80 let TSFlags{1} = PPC970_Single;
81 let TSFlags{2} = PPC970_Cracked;
82 let TSFlags{5-3} = PPC970_Unit;
86 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
87 InstrItinClass itin, list<dag> pattern>
88 : I<opcode, OOL, IOL, asmstr, itin> {
89 let Pattern = pattern;
98 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
99 : I<opcode, OOL, IOL, asmstr, BrB> {
100 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
105 let BI{0-1} = BIBO{5-6};
106 let BI{2-4} = CR{0-2};
108 let Inst{6-10} = BIBO{4-0};
109 let Inst{11-15} = BI;
110 let Inst{16-29} = BD;
115 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
117 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
123 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
124 dag OOL, dag IOL, string asmstr>
125 : I<opcode, OOL, IOL, asmstr, BrB> {
129 let Inst{11-15} = bi;
130 let Inst{16-29} = BD;
136 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
137 InstrItinClass itin, list<dag> pattern>
138 : I<opcode, OOL, IOL, asmstr, itin> {
143 let Pattern = pattern;
150 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
151 InstrItinClass itin, list<dag> pattern>
152 : I<opcode, OOL, IOL, asmstr, itin> {
156 let Pattern = pattern;
159 let Inst{11-15} = Addr{20-16}; // Base Reg
160 let Inst{16-31} = Addr{15-0}; // Displacement
163 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
164 InstrItinClass itin, list<dag> pattern>
165 : I<opcode, OOL, IOL, asmstr, itin> {
170 let Pattern = pattern;
178 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
179 InstrItinClass itin, list<dag> pattern>
180 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>;
182 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
183 InstrItinClass itin, list<dag> pattern>
184 : I<opcode, OOL, IOL, asmstr, itin> {
188 let Pattern = pattern;
195 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
196 InstrItinClass itin, list<dag> pattern>
197 : I<opcode, OOL, IOL, asmstr, itin> {
202 let Pattern = pattern;
209 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
210 InstrItinClass itin, list<dag> pattern>
211 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
216 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
217 dag OOL, dag IOL, string asmstr,
218 InstrItinClass itin, list<dag> pattern>
219 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
223 let Pattern = pattern;
231 let Inst{43-47} = Addr{20-16}; // Base Reg
232 let Inst{48-63} = Addr{15-0}; // Displacement
235 // This is used to emit BL8+NOP.
236 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
237 dag OOL, dag IOL, string asmstr,
238 InstrItinClass itin, list<dag> pattern>
239 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
240 OOL, IOL, asmstr, itin, pattern> {
245 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
247 : I<opcode, OOL, IOL, asmstr, itin> {
256 let Inst{11-15} = RA;
260 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
262 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
266 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
268 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
270 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
278 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
279 InstrItinClass itin, list<dag> pattern>
280 : I<opcode, OOL, IOL, asmstr, itin> {
284 let Pattern = pattern;
286 let Inst{6-10} = RST;
287 let Inst{11-15} = DS_RA{18-14}; // Register #
288 let Inst{16-29} = DS_RA{13-0}; // Displacement.
289 let Inst{30-31} = xo;
292 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
293 InstrItinClass itin, list<dag> pattern>
294 : I<opcode, OOL, IOL, asmstr, itin> {
299 let Pattern = pattern;
301 let Inst{6-10} = RST;
302 let Inst{11-15} = RA;
303 let Inst{16-29} = DS;
304 let Inst{30-31} = xo;
308 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : I<opcode, OOL, IOL, asmstr, itin> {
315 let Pattern = pattern;
317 bit RC = 0; // set by isDOT
319 let Inst{6-10} = RST;
322 let Inst{21-30} = xo;
326 // This is the same as XForm_base_r3xo, but the first two operands are swapped
327 // when code is emitted.
328 class XForm_base_r3xo_swapped
329 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
331 : I<opcode, OOL, IOL, asmstr, itin> {
336 bit RC = 0; // set by isDOT
338 let Inst{6-10} = RST;
341 let Inst{21-30} = xo;
346 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
347 InstrItinClass itin, list<dag> pattern>
348 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
350 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
351 InstrItinClass itin, list<dag> pattern>
352 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
353 let Pattern = pattern;
356 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
357 InstrItinClass itin, list<dag> pattern>
358 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
360 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
361 InstrItinClass itin, list<dag> pattern>
362 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
363 let Pattern = pattern;
366 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
367 InstrItinClass itin, list<dag> pattern>
368 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
370 let Pattern = pattern;
373 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
375 : I<opcode, OOL, IOL, asmstr, itin> {
384 let Inst{11-15} = RA;
385 let Inst{16-20} = RB;
386 let Inst{21-30} = xo;
390 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
392 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
396 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
398 : I<opcode, OOL, IOL, asmstr, itin> {
405 let Inst{11-15} = FRA;
406 let Inst{16-20} = FRB;
407 let Inst{21-30} = xo;
411 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
412 InstrItinClass itin, list<dag> pattern>
413 : I<opcode, OOL, IOL, asmstr, itin> {
414 let Pattern = pattern;
418 let Inst{21-30} = xo;
422 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
423 string asmstr, InstrItinClass itin, list<dag> pattern>
424 : I<opcode, OOL, IOL, asmstr, itin> {
425 let Pattern = pattern;
429 let Inst{21-30} = xo;
433 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
434 InstrItinClass itin, list<dag> pattern>
435 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
438 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
439 InstrItinClass itin, list<dag> pattern>
440 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
444 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
445 InstrItinClass itin, list<dag> pattern>
446 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
449 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
450 // numbers presumably relates to some document, but I haven't found it.
451 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
452 InstrItinClass itin, list<dag> pattern>
453 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
454 let Pattern = pattern;
456 bit RC = 0; // set by isDOT
458 let Inst{6-10} = RST;
460 let Inst{21-30} = xo;
463 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
464 InstrItinClass itin, list<dag> pattern>
465 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
466 let Pattern = pattern;
469 bit RC = 0; // set by isDOT
473 let Inst{21-30} = xo;
477 // DCB_Form - Form X instruction, used for dcb* instructions.
478 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
479 InstrItinClass itin, list<dag> pattern>
480 : I<31, OOL, IOL, asmstr, itin> {
484 let Pattern = pattern;
486 let Inst{6-10} = immfield;
489 let Inst{21-30} = xo;
494 // DSS_Form - Form X instruction, used for altivec dss* instructions.
495 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
496 InstrItinClass itin, list<dag> pattern>
497 : I<31, OOL, IOL, asmstr, itin> {
503 let Pattern = pattern;
507 let Inst{9-10} = STRM;
510 let Inst{21-30} = xo;
515 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
516 InstrItinClass itin, list<dag> pattern>
517 : I<opcode, OOL, IOL, asmstr, itin> {
522 let Pattern = pattern;
524 let Inst{6-10} = CRD;
525 let Inst{11-15} = CRA;
526 let Inst{16-20} = CRB;
527 let Inst{21-30} = xo;
531 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
532 InstrItinClass itin, list<dag> pattern>
533 : I<opcode, OOL, IOL, asmstr, itin> {
536 let Pattern = pattern;
538 let Inst{6-10} = CRD;
539 let Inst{11-15} = CRD;
540 let Inst{16-20} = CRD;
541 let Inst{21-30} = xo;
545 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
546 InstrItinClass itin, list<dag> pattern>
547 : I<opcode, OOL, IOL, asmstr, itin> {
552 let Pattern = pattern;
555 let Inst{11-15} = BI;
557 let Inst{19-20} = BH;
558 let Inst{21-30} = xo;
562 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
563 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
564 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
565 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
569 let BI{0-1} = BIBO{0-1};
575 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
576 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
577 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
583 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
585 : I<opcode, OOL, IOL, asmstr, itin> {
591 let Inst{11-13} = BFA;
594 let Inst{21-30} = xo;
599 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
601 : I<opcode, OOL, IOL, asmstr, itin> {
606 let Inst{11} = SPR{4};
607 let Inst{12} = SPR{3};
608 let Inst{13} = SPR{2};
609 let Inst{14} = SPR{1};
610 let Inst{15} = SPR{0};
611 let Inst{16} = SPR{9};
612 let Inst{17} = SPR{8};
613 let Inst{18} = SPR{7};
614 let Inst{19} = SPR{6};
615 let Inst{20} = SPR{5};
616 let Inst{21-30} = xo;
620 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
621 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
622 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
626 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
628 : I<opcode, OOL, IOL, asmstr, itin> {
633 let Inst{21-30} = xo;
637 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
639 : I<opcode, OOL, IOL, asmstr, itin> {
645 let Inst{12-19} = FXM;
647 let Inst{21-30} = xo;
651 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
653 : I<opcode, OOL, IOL, asmstr, itin> {
659 let Inst{12-19} = FXM;
661 let Inst{21-30} = xo;
665 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
667 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
669 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
670 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
671 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
676 // This is probably 1.7.9, but I don't have the reference that uses this
677 // numbering scheme...
678 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
679 InstrItinClass itin, list<dag>pattern>
680 : I<opcode, OOL, IOL, asmstr, itin> {
684 bit RC = 0; // set by isDOT
685 let Pattern = pattern;
690 let Inst{16-20} = rT;
691 let Inst{21-30} = xo;
695 // 1.7.10 XS-Form - SRADI.
696 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
697 InstrItinClass itin, list<dag> pattern>
698 : I<opcode, OOL, IOL, asmstr, itin> {
703 bit RC = 0; // set by isDOT
704 let Pattern = pattern;
708 let Inst{16-20} = SH{4,3,2,1,0};
709 let Inst{21-29} = xo;
710 let Inst{30} = SH{5};
715 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
716 InstrItinClass itin, list<dag> pattern>
717 : I<opcode, OOL, IOL, asmstr, itin> {
722 let Pattern = pattern;
724 bit RC = 0; // set by isDOT
727 let Inst{11-15} = RA;
728 let Inst{16-20} = RB;
730 let Inst{22-30} = xo;
734 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
735 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
736 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
741 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
742 InstrItinClass itin, list<dag> pattern>
743 : I<opcode, OOL, IOL, asmstr, itin> {
749 let Pattern = pattern;
751 bit RC = 0; // set by isDOT
753 let Inst{6-10} = FRT;
754 let Inst{11-15} = FRA;
755 let Inst{16-20} = FRB;
756 let Inst{21-25} = FRC;
757 let Inst{26-30} = xo;
761 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
762 InstrItinClass itin, list<dag> pattern>
763 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
767 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
768 InstrItinClass itin, list<dag> pattern>
769 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
773 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
774 InstrItinClass itin, list<dag> pattern>
775 : I<opcode, OOL, IOL, asmstr, itin> {
781 let Pattern = pattern;
784 let Inst{11-15} = RA;
785 let Inst{16-20} = RB;
786 let Inst{21-25} = COND;
787 let Inst{26-30} = xo;
792 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
793 InstrItinClass itin, list<dag> pattern>
794 : I<opcode, OOL, IOL, asmstr, itin> {
801 let Pattern = pattern;
803 bit RC = 0; // set by isDOT
806 let Inst{11-15} = RA;
807 let Inst{16-20} = RB;
808 let Inst{21-25} = MB;
809 let Inst{26-30} = ME;
813 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
814 InstrItinClass itin, list<dag> pattern>
815 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
819 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
820 InstrItinClass itin, list<dag> pattern>
821 : I<opcode, OOL, IOL, asmstr, itin> {
827 let Pattern = pattern;
829 bit RC = 0; // set by isDOT
832 let Inst{11-15} = RA;
833 let Inst{16-20} = SH{4,3,2,1,0};
834 let Inst{21-26} = MBE{4,3,2,1,0,5};
835 let Inst{27-29} = xo;
836 let Inst{30} = SH{5};
844 // VAForm_1 - DACB ordering.
845 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
846 InstrItinClass itin, list<dag> pattern>
847 : I<4, OOL, IOL, asmstr, itin> {
853 let Pattern = pattern;
856 let Inst{11-15} = VA;
857 let Inst{16-20} = VB;
858 let Inst{21-25} = VC;
859 let Inst{26-31} = xo;
862 // VAForm_1a - DABC ordering.
863 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
864 InstrItinClass itin, list<dag> pattern>
865 : I<4, OOL, IOL, asmstr, itin> {
871 let Pattern = pattern;
874 let Inst{11-15} = VA;
875 let Inst{16-20} = VB;
876 let Inst{21-25} = VC;
877 let Inst{26-31} = xo;
880 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
881 InstrItinClass itin, list<dag> pattern>
882 : I<4, OOL, IOL, asmstr, itin> {
888 let Pattern = pattern;
891 let Inst{11-15} = VA;
892 let Inst{16-20} = VB;
894 let Inst{22-25} = SH;
895 let Inst{26-31} = xo;
899 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
900 InstrItinClass itin, list<dag> pattern>
901 : I<4, OOL, IOL, asmstr, itin> {
906 let Pattern = pattern;
909 let Inst{11-15} = VA;
910 let Inst{16-20} = VB;
911 let Inst{21-31} = xo;
914 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
915 InstrItinClass itin, list<dag> pattern>
916 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
922 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
923 InstrItinClass itin, list<dag> pattern>
924 : I<4, OOL, IOL, asmstr, itin> {
928 let Pattern = pattern;
932 let Inst{16-20} = VB;
933 let Inst{21-31} = xo;
936 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
937 InstrItinClass itin, list<dag> pattern>
938 : I<4, OOL, IOL, asmstr, itin> {
942 let Pattern = pattern;
945 let Inst{11-15} = IMM;
947 let Inst{21-31} = xo;
950 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
951 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
952 InstrItinClass itin, list<dag> pattern>
953 : I<4, OOL, IOL, asmstr, itin> {
956 let Pattern = pattern;
961 let Inst{21-31} = xo;
964 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
965 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
966 InstrItinClass itin, list<dag> pattern>
967 : I<4, OOL, IOL, asmstr, itin> {
970 let Pattern = pattern;
974 let Inst{16-20} = VB;
975 let Inst{21-31} = xo;
979 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
980 InstrItinClass itin, list<dag> pattern>
981 : I<4, OOL, IOL, asmstr, itin> {
987 let Pattern = pattern;
990 let Inst{11-15} = VA;
991 let Inst{16-20} = VB;
993 let Inst{22-31} = xo;
996 //===----------------------------------------------------------------------===//
997 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
998 : I<0, OOL, IOL, asmstr, NoItinerary> {
999 let isCodeGenOnly = 1;
1001 let Pattern = pattern;