1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class Format<bits<5> val> {
17 def Pseudo: Format<0>;
20 def Simm16 : Format<3>;
21 def PCRelimm24 : Format<5>;
22 def Imm24 : Format<6>;
24 def PCRelimm14 : Format<8>;
25 def Imm14 : Format<9>;
26 def Imm2 : Format<10>;
28 def Imm3 : Format<12>;
29 def Imm1 : Format<13>;
31 def Imm4 : Format<15>;
32 def Imm8 : Format<16>;
33 def Disimm16 : Format<17>;
34 def Disimm14 : Format<18>;
37 def Imm15 : Format<21>;
39 def Imm6 : Format<23>;
41 //===----------------------------------------------------------------------===//
43 // PowerPC instruction formats
45 class I<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
53 let Namespace = "PPC";
54 let Inst{0-5} = opcode;
56 let AsmString = asmstr;
60 class IForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
61 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
70 class BForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
71 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
78 let Inst{11-13} = CRNum;
79 let Inst{14-15} = BICode;
85 class BForm_ext<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode,
86 bit ppc64, bit vmx, dag OL, string asmstr>
87 : BForm<opcode, aa, lk, ppc64, vmx, OL, asmstr> {
93 class DForm_base<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
94 : I<opcode, ppc64, vmx, OL, asmstr> {
104 class DForm_1<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
105 : I<opcode, ppc64, vmx, OL, asmstr> {
115 class DForm_2<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
116 : DForm_base<opcode, ppc64, vmx, OL, asmstr>;
118 class DForm_2_r0<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
119 : I<opcode, ppc64, vmx, OL, asmstr> {
128 // Currently we make the use/def reg distinction in ISel, not tablegen
129 class DForm_3<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
130 : DForm_1<opcode, ppc64, vmx, OL, asmstr>;
132 class DForm_4<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
133 : I<opcode, ppc64, vmx, OL, asmstr> {
143 class DForm_4_zero<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
144 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
150 class DForm_5<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
151 : I<opcode, ppc64, vmx, OL, asmstr> {
160 let Inst{11-15} = RA;
164 class DForm_5_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
165 : DForm_5<opcode, ppc64, vmx, OL, asmstr> {
169 class DForm_6<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
170 : DForm_5<opcode, ppc64, vmx, OL, asmstr>;
172 class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
173 : DForm_6<opcode, ppc64, vmx, OL, asmstr> {
177 class DForm_8<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
178 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
181 class DForm_9<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
182 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
186 class DSForm_1<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
187 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
192 let Inst{6-10} = RST;
193 let Inst{11-15} = RA;
194 let Inst{16-29} = DS;
195 let Inst{30-31} = xo;
198 class DSForm_2<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
199 dag OL, string asmstr>
200 : DSForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
203 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc,
204 dag OL, string asmstr>
205 : I<opcode, 0, 0, OL, asmstr> {
210 let Inst{6-10} = RST;
213 let Inst{21-30} = xo;
217 // This is the same as XForm_base_r3xo, but the first two operands are swapped
218 // when code is emitted.
219 class XForm_base_r3xo_swapped
220 <bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
221 : I<opcode, 0, 0, OL, asmstr> {
226 let Inst{6-10} = RST;
229 let Inst{21-30} = xo;
234 class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
235 : XForm_base_r3xo<opcode, xo, 0, OL, asmstr>;
237 class XForm_6<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
238 : XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr>;
240 class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
241 : XForm_base_r3xo<opcode, xo, 0, OL, asmstr>;
243 class XForm_10<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
244 : XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr> {
247 class XForm_11<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
248 : XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr> {
252 class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
253 : I<opcode, 0, 0, OL, asmstr> {
262 let Inst{11-15} = RA;
263 let Inst{16-20} = RB;
264 let Inst{21-30} = xo;
268 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
269 : XForm_16<opcode, xo, OL, asmstr> {
273 class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
274 : I<opcode, 0, 0, OL, asmstr> {
281 let Inst{11-15} = FRA;
282 let Inst{16-20} = FRB;
283 let Inst{21-30} = xo;
287 class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
288 : XForm_base_r3xo<opcode, xo, 0, OL, asmstr> {
291 class XForm_26<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
292 : XForm_base_r3xo<opcode, xo, rc, OL, asmstr> {
296 class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
297 : XForm_base_r3xo<opcode, xo, 0, OL, asmstr> {
301 class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
302 : I<opcode, 0, 0, OL, asmstr> {
311 let Inst{9-10} = CRDb;
312 let Inst{11-13} = CRA;
313 let Inst{14-15} = CRAb;
314 let Inst{16-18} = CRB;
315 let Inst{19-20} = CRBb;
316 let Inst{21-30} = xo;
320 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk,
321 dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
327 let Inst{11-15} = BI;
329 let Inst{19-20} = BH;
330 let Inst{21-30} = xo;
334 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
335 bits<5> bi, bit lk, dag OL, string asmstr>
336 : XLForm_2<opcode, xo, lk, OL, asmstr> {
342 class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
343 : I<opcode, 0, 0, OL, asmstr> {
349 let Inst{11-13} = BFA;
352 let Inst{21-30} = xo;
357 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
358 : I<opcode, 0, 0, OL, asmstr> {
363 let Inst{11-20} = SPR;
364 let Inst{21-30} = xo;
368 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
369 dag OL, string asmstr>
370 : XFXForm_1<opcode, xo, OL, asmstr> {
374 class XFXForm_3<bits<6> opcode, bits<10> xo,
375 dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
380 let Inst{21-30} = xo;
384 class XFXForm_5<bits<6> opcode, bit mfcrf, bits<10> xo,
385 dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
390 let Inst{11} = mfcrf;
391 let Inst{12-19} = FXM;
393 let Inst{21-30} = xo;
397 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
398 : XFXForm_1<opcode, xo, OL, asmstr>;
400 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
401 dag OL, string asmstr>
402 : XFXForm_7<opcode, xo, OL, asmstr> {
407 class XSForm_1<bits<6> opcode, bits<9> xo, bit rc,
408 dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
415 let Inst{16-20} = SH{1-5};
416 let Inst{21-29} = xo;
417 let Inst{30} = SH{0};
422 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc,
423 dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
429 let Inst{11-15} = RA;
430 let Inst{16-20} = RB;
432 let Inst{22-30} = xo;
436 class XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, bit rc,
437 dag OL, string asmstr>
438 : XOForm_1<opcode, xo, oe, rc, OL, asmstr> {
439 let Inst{11-15} = RB;
440 let Inst{16-20} = RA;
443 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, bit rc,
444 dag OL, string asmstr>
445 : XOForm_1<opcode, xo, oe, rc, OL, asmstr> {
450 class AForm_1<bits<6> opcode, bits<5> xo, bit rc, dag OL, string asmstr>
451 : I<opcode, 0, 0, OL, asmstr> {
457 let Inst{6-10} = FRT;
458 let Inst{11-15} = FRA;
459 let Inst{16-20} = FRB;
460 let Inst{21-25} = FRC;
461 let Inst{26-30} = xo;
465 class AForm_2<bits<6> opcode, bits<5> xo, bit rc, dag OL, string asmstr>
466 : AForm_1<opcode, xo, rc, OL, asmstr> {
470 class AForm_3<bits<6> opcode, bits<5> xo, bit rc, dag OL,
472 : AForm_1<opcode, xo, rc, OL, asmstr> {
477 class MForm_1<bits<6> opcode, bit rc, dag OL, string asmstr>
478 : I<opcode, 0, 0, OL, asmstr> {
486 let Inst{11-15} = RA;
487 let Inst{16-20} = RB;
488 let Inst{21-25} = MB;
489 let Inst{26-30} = ME;
493 class MForm_2<bits<6> opcode, bit rc, dag OL, string asmstr>
494 : MForm_1<opcode, rc, OL, asmstr> {
498 class MDForm_1<bits<6> opcode, bits<3> xo, bit rc,
499 dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
506 let Inst{11-15} = RA;
507 let Inst{16-20} = SH{1-5};
508 let Inst{21-26} = MBE;
509 let Inst{27-29} = xo;
510 let Inst{30} = SH{0};
514 //===----------------------------------------------------------------------===//
516 class Pseudo<dag OL, string asmstr> : I<0, 0, 0, OL, asmstr> {