1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
363 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
364 InstrItinClass itin, list<dag> pattern>
365 : I<opcode, OOL, IOL, asmstr, itin> {
370 let Pattern = pattern;
372 let Inst{6-10} = RST;
373 let Inst{11-15} = RA;
374 let Inst{16-29} = DS;
375 let Inst{30-31} = xo;
379 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
380 InstrItinClass itin, list<dag> pattern>
381 : I<opcode, OOL, IOL, asmstr, itin> {
386 let Pattern = pattern;
388 bit RC = 0; // set by isDOT
390 let Inst{6-10} = RST;
393 let Inst{21-30} = xo;
397 // This is the same as XForm_base_r3xo, but the first two operands are swapped
398 // when code is emitted.
399 class XForm_base_r3xo_swapped
400 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
402 : I<opcode, OOL, IOL, asmstr, itin> {
407 bit RC = 0; // set by isDOT
409 let Inst{6-10} = RST;
412 let Inst{21-30} = xo;
417 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
418 InstrItinClass itin, list<dag> pattern>
419 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
421 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
422 InstrItinClass itin, list<dag> pattern>
423 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
427 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
428 InstrItinClass itin, list<dag> pattern>
429 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
434 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
435 InstrItinClass itin, list<dag> pattern>
436 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
437 let Pattern = pattern;
440 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
441 InstrItinClass itin, list<dag> pattern>
442 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
444 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
445 InstrItinClass itin, list<dag> pattern>
446 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
447 let Pattern = pattern;
450 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
451 InstrItinClass itin, list<dag> pattern>
452 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
454 let Pattern = pattern;
457 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
459 : I<opcode, OOL, IOL, asmstr, itin> {
468 let Inst{11-15} = RA;
469 let Inst{16-20} = RB;
470 let Inst{21-30} = xo;
474 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
476 : I<opcode, OOL, IOL, asmstr, itin> {
482 let Inst{21-30} = xo;
485 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
487 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
491 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
493 : I<opcode, OOL, IOL, asmstr, itin> {
500 let Inst{11-15} = FRA;
501 let Inst{16-20} = FRB;
502 let Inst{21-30} = xo;
506 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
507 InstrItinClass itin, list<dag> pattern>
508 : I<opcode, OOL, IOL, asmstr, itin> {
509 let Pattern = pattern;
513 let Inst{21-30} = xo;
517 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
518 string asmstr, InstrItinClass itin, list<dag> pattern>
519 : I<opcode, OOL, IOL, asmstr, itin> {
522 let Pattern = pattern;
527 let Inst{21-30} = xo;
531 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
532 string asmstr, InstrItinClass itin, list<dag> pattern>
533 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
537 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
538 InstrItinClass itin, list<dag> pattern>
539 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
542 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
543 InstrItinClass itin, list<dag> pattern>
544 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
548 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
549 InstrItinClass itin, list<dag> pattern>
550 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
553 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
554 // numbers presumably relates to some document, but I haven't found it.
555 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
556 InstrItinClass itin, list<dag> pattern>
557 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
558 let Pattern = pattern;
560 bit RC = 0; // set by isDOT
562 let Inst{6-10} = RST;
564 let Inst{21-30} = xo;
567 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
568 InstrItinClass itin, list<dag> pattern>
569 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
570 let Pattern = pattern;
573 bit RC = 0; // set by isDOT
577 let Inst{21-30} = xo;
581 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
582 InstrItinClass itin, list<dag> pattern>
583 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
589 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
590 InstrItinClass itin, list<dag> pattern>
591 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
596 // DCB_Form - Form X instruction, used for dcb* instructions.
597 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
598 InstrItinClass itin, list<dag> pattern>
599 : I<31, OOL, IOL, asmstr, itin> {
603 let Pattern = pattern;
605 let Inst{6-10} = immfield;
608 let Inst{21-30} = xo;
613 // DSS_Form - Form X instruction, used for altivec dss* instructions.
614 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
615 InstrItinClass itin, list<dag> pattern>
616 : I<31, OOL, IOL, asmstr, itin> {
622 let Pattern = pattern;
626 let Inst{9-10} = STRM;
629 let Inst{21-30} = xo;
634 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
635 InstrItinClass itin, list<dag> pattern>
636 : I<opcode, OOL, IOL, asmstr, itin> {
641 let Pattern = pattern;
643 let Inst{6-10} = CRD;
644 let Inst{11-15} = CRA;
645 let Inst{16-20} = CRB;
646 let Inst{21-30} = xo;
650 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
651 InstrItinClass itin, list<dag> pattern>
652 : I<opcode, OOL, IOL, asmstr, itin> {
655 let Pattern = pattern;
657 let Inst{6-10} = CRD;
658 let Inst{11-15} = CRD;
659 let Inst{16-20} = CRD;
660 let Inst{21-30} = xo;
664 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
665 InstrItinClass itin, list<dag> pattern>
666 : I<opcode, OOL, IOL, asmstr, itin> {
671 let Pattern = pattern;
674 let Inst{11-15} = BI;
676 let Inst{19-20} = BH;
677 let Inst{21-30} = xo;
681 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
682 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
683 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
684 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
688 let BI{0-1} = BIBO{5-6};
689 let BI{2-4} = CR{0-2};
693 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
694 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
695 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
700 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
701 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
702 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
708 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
710 : I<opcode, OOL, IOL, asmstr, itin> {
716 let Inst{11-13} = BFA;
719 let Inst{21-30} = xo;
724 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
726 : I<opcode, OOL, IOL, asmstr, itin> {
731 let Inst{11} = SPR{4};
732 let Inst{12} = SPR{3};
733 let Inst{13} = SPR{2};
734 let Inst{14} = SPR{1};
735 let Inst{15} = SPR{0};
736 let Inst{16} = SPR{9};
737 let Inst{17} = SPR{8};
738 let Inst{18} = SPR{7};
739 let Inst{19} = SPR{6};
740 let Inst{20} = SPR{5};
741 let Inst{21-30} = xo;
745 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
746 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
747 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
751 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
753 : I<opcode, OOL, IOL, asmstr, itin> {
758 let Inst{21-30} = xo;
762 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
764 : I<opcode, OOL, IOL, asmstr, itin> {
770 let Inst{12-19} = FXM;
772 let Inst{21-30} = xo;
776 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
778 : I<opcode, OOL, IOL, asmstr, itin> {
784 let Inst{12-19} = FXM;
786 let Inst{21-30} = xo;
790 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
792 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
794 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
795 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
796 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
801 // This is probably 1.7.9, but I don't have the reference that uses this
802 // numbering scheme...
803 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
804 InstrItinClass itin, list<dag>pattern>
805 : I<opcode, OOL, IOL, asmstr, itin> {
809 bit RC = 0; // set by isDOT
810 let Pattern = pattern;
815 let Inst{16-20} = rT;
816 let Inst{21-30} = xo;
820 // 1.7.10 XS-Form - SRADI.
821 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
822 InstrItinClass itin, list<dag> pattern>
823 : I<opcode, OOL, IOL, asmstr, itin> {
828 bit RC = 0; // set by isDOT
829 let Pattern = pattern;
833 let Inst{16-20} = SH{4,3,2,1,0};
834 let Inst{21-29} = xo;
835 let Inst{30} = SH{5};
840 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
841 InstrItinClass itin, list<dag> pattern>
842 : I<opcode, OOL, IOL, asmstr, itin> {
847 let Pattern = pattern;
849 bit RC = 0; // set by isDOT
852 let Inst{11-15} = RA;
853 let Inst{16-20} = RB;
855 let Inst{22-30} = xo;
859 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
860 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
861 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
866 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
867 InstrItinClass itin, list<dag> pattern>
868 : I<opcode, OOL, IOL, asmstr, itin> {
874 let Pattern = pattern;
876 bit RC = 0; // set by isDOT
878 let Inst{6-10} = FRT;
879 let Inst{11-15} = FRA;
880 let Inst{16-20} = FRB;
881 let Inst{21-25} = FRC;
882 let Inst{26-30} = xo;
886 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
887 InstrItinClass itin, list<dag> pattern>
888 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
892 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
893 InstrItinClass itin, list<dag> pattern>
894 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
898 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
899 InstrItinClass itin, list<dag> pattern>
900 : I<opcode, OOL, IOL, asmstr, itin> {
906 let Pattern = pattern;
909 let Inst{11-15} = RA;
910 let Inst{16-20} = RB;
911 let Inst{21-25} = COND;
912 let Inst{26-30} = xo;
917 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
918 InstrItinClass itin, list<dag> pattern>
919 : I<opcode, OOL, IOL, asmstr, itin> {
926 let Pattern = pattern;
928 bit RC = 0; // set by isDOT
931 let Inst{11-15} = RA;
932 let Inst{16-20} = RB;
933 let Inst{21-25} = MB;
934 let Inst{26-30} = ME;
938 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
939 InstrItinClass itin, list<dag> pattern>
940 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
944 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
945 InstrItinClass itin, list<dag> pattern>
946 : I<opcode, OOL, IOL, asmstr, itin> {
952 let Pattern = pattern;
954 bit RC = 0; // set by isDOT
957 let Inst{11-15} = RA;
958 let Inst{16-20} = SH{4,3,2,1,0};
959 let Inst{21-26} = MBE{4,3,2,1,0,5};
960 let Inst{27-29} = xo;
961 let Inst{30} = SH{5};
965 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
966 InstrItinClass itin, list<dag> pattern>
967 : I<opcode, OOL, IOL, asmstr, itin> {
973 let Pattern = pattern;
975 bit RC = 0; // set by isDOT
978 let Inst{11-15} = RA;
979 let Inst{16-20} = RB;
980 let Inst{21-26} = MBE{4,3,2,1,0,5};
981 let Inst{27-30} = xo;
988 // VAForm_1 - DACB ordering.
989 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
990 InstrItinClass itin, list<dag> pattern>
991 : I<4, OOL, IOL, asmstr, itin> {
997 let Pattern = pattern;
1000 let Inst{11-15} = VA;
1001 let Inst{16-20} = VB;
1002 let Inst{21-25} = VC;
1003 let Inst{26-31} = xo;
1006 // VAForm_1a - DABC ordering.
1007 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1008 InstrItinClass itin, list<dag> pattern>
1009 : I<4, OOL, IOL, asmstr, itin> {
1015 let Pattern = pattern;
1017 let Inst{6-10} = VD;
1018 let Inst{11-15} = VA;
1019 let Inst{16-20} = VB;
1020 let Inst{21-25} = VC;
1021 let Inst{26-31} = xo;
1024 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1025 InstrItinClass itin, list<dag> pattern>
1026 : I<4, OOL, IOL, asmstr, itin> {
1032 let Pattern = pattern;
1034 let Inst{6-10} = VD;
1035 let Inst{11-15} = VA;
1036 let Inst{16-20} = VB;
1038 let Inst{22-25} = SH;
1039 let Inst{26-31} = xo;
1043 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1044 InstrItinClass itin, list<dag> pattern>
1045 : I<4, OOL, IOL, asmstr, itin> {
1050 let Pattern = pattern;
1052 let Inst{6-10} = VD;
1053 let Inst{11-15} = VA;
1054 let Inst{16-20} = VB;
1055 let Inst{21-31} = xo;
1058 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1059 InstrItinClass itin, list<dag> pattern>
1060 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1066 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1067 InstrItinClass itin, list<dag> pattern>
1068 : I<4, OOL, IOL, asmstr, itin> {
1072 let Pattern = pattern;
1074 let Inst{6-10} = VD;
1075 let Inst{11-15} = 0;
1076 let Inst{16-20} = VB;
1077 let Inst{21-31} = xo;
1080 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1081 InstrItinClass itin, list<dag> pattern>
1082 : I<4, OOL, IOL, asmstr, itin> {
1086 let Pattern = pattern;
1088 let Inst{6-10} = VD;
1089 let Inst{11-15} = IMM;
1090 let Inst{16-20} = 0;
1091 let Inst{21-31} = xo;
1094 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1095 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1096 InstrItinClass itin, list<dag> pattern>
1097 : I<4, OOL, IOL, asmstr, itin> {
1100 let Pattern = pattern;
1102 let Inst{6-10} = VD;
1103 let Inst{11-15} = 0;
1104 let Inst{16-20} = 0;
1105 let Inst{21-31} = xo;
1108 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1109 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1110 InstrItinClass itin, list<dag> pattern>
1111 : I<4, OOL, IOL, asmstr, itin> {
1114 let Pattern = pattern;
1117 let Inst{11-15} = 0;
1118 let Inst{16-20} = VB;
1119 let Inst{21-31} = xo;
1123 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1124 InstrItinClass itin, list<dag> pattern>
1125 : I<4, OOL, IOL, asmstr, itin> {
1131 let Pattern = pattern;
1133 let Inst{6-10} = VD;
1134 let Inst{11-15} = VA;
1135 let Inst{16-20} = VB;
1137 let Inst{22-31} = xo;
1140 //===----------------------------------------------------------------------===//
1141 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1142 : I<0, OOL, IOL, asmstr, NoItinerary> {
1143 let isCodeGenOnly = 1;
1145 let Pattern = pattern;