1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
39 // Fields used for relation models.
42 // For cases where multiple instruction definitions really represent the
43 // same underlying instruction but with one definition for 64-bit arguments
44 // and one for 32-bit arguments, this bit breaks the degeneracy between
45 // the two forms and allows TableGen to generate mapping tables.
46 bit Interpretation64Bit = 0;
49 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
50 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
51 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
52 class PPC970_MicroCode;
54 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
55 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
56 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
57 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
58 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
59 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
60 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
61 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
63 // Two joined instructions; used to emit two adjacent instructions as one.
64 // The itinerary from the first instruction is used for scheduling and
66 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
71 bit PPC64 = 0; // Default value, override with isPPC64
73 let Namespace = "PPC";
74 let Inst{0-5} = opcode1;
75 let Inst{32-37} = opcode2;
76 let OutOperandList = OOL;
77 let InOperandList = IOL;
78 let AsmString = asmstr;
81 bits<1> PPC970_First = 0;
82 bits<1> PPC970_Single = 0;
83 bits<1> PPC970_Cracked = 0;
84 bits<3> PPC970_Unit = 0;
86 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
87 /// these must be reflected there! See comments there for what these are.
88 let TSFlags{0} = PPC970_First;
89 let TSFlags{1} = PPC970_Single;
90 let TSFlags{2} = PPC970_Cracked;
91 let TSFlags{5-3} = PPC970_Unit;
93 // Fields used for relation models.
95 bit Interpretation64Bit = 0;
99 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
100 InstrItinClass itin, list<dag> pattern>
101 : I<opcode, OOL, IOL, asmstr, itin> {
102 let Pattern = pattern;
111 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
112 : I<opcode, OOL, IOL, asmstr, BrB> {
113 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
118 let BI{0-1} = BIBO{5-6};
119 let BI{2-4} = CR{0-2};
121 let Inst{6-10} = BIBO{4-0};
122 let Inst{11-15} = BI;
123 let Inst{16-29} = BD;
128 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
130 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
136 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
137 dag OOL, dag IOL, string asmstr>
138 : I<opcode, OOL, IOL, asmstr, BrB> {
142 let Inst{11-15} = bi;
143 let Inst{16-29} = BD;
149 class SCForm<bits<6> opcode, bits<1> xo,
150 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
152 : I<opcode, OOL, IOL, asmstr, itin> {
155 let Pattern = pattern;
157 let Inst{20-26} = LEV;
162 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
163 InstrItinClass itin, list<dag> pattern>
164 : I<opcode, OOL, IOL, asmstr, itin> {
169 let Pattern = pattern;
176 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
177 InstrItinClass itin, list<dag> pattern>
178 : I<opcode, OOL, IOL, asmstr, itin> {
182 let Pattern = pattern;
185 let Inst{11-15} = Addr{20-16}; // Base Reg
186 let Inst{16-31} = Addr{15-0}; // Displacement
189 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
190 InstrItinClass itin, list<dag> pattern>
191 : I<opcode, OOL, IOL, asmstr, itin> {
196 let Pattern = pattern;
204 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
205 InstrItinClass itin, list<dag> pattern>
206 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
208 // Even though ADDICo does not really have an RC bit, provide
209 // the declaration of one here so that isDOT has something to set.
213 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
214 InstrItinClass itin, list<dag> pattern>
215 : I<opcode, OOL, IOL, asmstr, itin> {
219 let Pattern = pattern;
226 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
227 InstrItinClass itin, list<dag> pattern>
228 : I<opcode, OOL, IOL, asmstr, itin> {
233 let Pattern = pattern;
240 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
241 InstrItinClass itin, list<dag> pattern>
242 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
247 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
248 dag OOL, dag IOL, string asmstr,
249 InstrItinClass itin, list<dag> pattern>
250 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
254 let Pattern = pattern;
262 let Inst{43-47} = Addr{20-16}; // Base Reg
263 let Inst{48-63} = Addr{15-0}; // Displacement
266 // This is used to emit BL8+NOP.
267 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
268 dag OOL, dag IOL, string asmstr,
269 InstrItinClass itin, list<dag> pattern>
270 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
271 OOL, IOL, asmstr, itin, pattern> {
276 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
278 : I<opcode, OOL, IOL, asmstr, itin> {
287 let Inst{11-15} = RA;
291 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
293 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
297 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
299 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
301 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
303 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
309 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
310 InstrItinClass itin, list<dag> pattern>
311 : I<opcode, OOL, IOL, asmstr, itin> {
315 let Pattern = pattern;
317 let Inst{6-10} = RST;
318 let Inst{11-15} = DS_RA{18-14}; // Register #
319 let Inst{16-29} = DS_RA{13-0}; // Displacement.
320 let Inst{30-31} = xo;
323 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
324 InstrItinClass itin, list<dag> pattern>
325 : I<opcode, OOL, IOL, asmstr, itin> {
330 let Pattern = pattern;
332 let Inst{6-10} = RST;
333 let Inst{11-15} = RA;
334 let Inst{16-29} = DS;
335 let Inst{30-31} = xo;
339 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
340 InstrItinClass itin, list<dag> pattern>
341 : I<opcode, OOL, IOL, asmstr, itin> {
346 let Pattern = pattern;
348 bit RC = 0; // set by isDOT
350 let Inst{6-10} = RST;
353 let Inst{21-30} = xo;
357 // This is the same as XForm_base_r3xo, but the first two operands are swapped
358 // when code is emitted.
359 class XForm_base_r3xo_swapped
360 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
362 : I<opcode, OOL, IOL, asmstr, itin> {
367 bit RC = 0; // set by isDOT
369 let Inst{6-10} = RST;
372 let Inst{21-30} = xo;
377 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
378 InstrItinClass itin, list<dag> pattern>
379 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
381 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
382 InstrItinClass itin, list<dag> pattern>
383 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
387 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
388 InstrItinClass itin, list<dag> pattern>
389 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
390 let Pattern = pattern;
393 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
394 InstrItinClass itin, list<dag> pattern>
395 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
397 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
398 InstrItinClass itin, list<dag> pattern>
399 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
400 let Pattern = pattern;
403 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
404 InstrItinClass itin, list<dag> pattern>
405 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
407 let Pattern = pattern;
410 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
412 : I<opcode, OOL, IOL, asmstr, itin> {
421 let Inst{11-15} = RA;
422 let Inst{16-20} = RB;
423 let Inst{21-30} = xo;
427 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
429 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
433 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
435 : I<opcode, OOL, IOL, asmstr, itin> {
442 let Inst{11-15} = FRA;
443 let Inst{16-20} = FRB;
444 let Inst{21-30} = xo;
448 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
449 InstrItinClass itin, list<dag> pattern>
450 : I<opcode, OOL, IOL, asmstr, itin> {
451 let Pattern = pattern;
455 let Inst{21-30} = xo;
459 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
460 string asmstr, InstrItinClass itin, list<dag> pattern>
461 : I<opcode, OOL, IOL, asmstr, itin> {
462 let Pattern = pattern;
466 let Inst{21-30} = xo;
470 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
471 InstrItinClass itin, list<dag> pattern>
472 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
475 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
476 InstrItinClass itin, list<dag> pattern>
477 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
481 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
482 InstrItinClass itin, list<dag> pattern>
483 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
486 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
487 // numbers presumably relates to some document, but I haven't found it.
488 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
489 InstrItinClass itin, list<dag> pattern>
490 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
491 let Pattern = pattern;
493 bit RC = 0; // set by isDOT
495 let Inst{6-10} = RST;
497 let Inst{21-30} = xo;
500 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
501 InstrItinClass itin, list<dag> pattern>
502 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
503 let Pattern = pattern;
506 bit RC = 0; // set by isDOT
510 let Inst{21-30} = xo;
514 // DCB_Form - Form X instruction, used for dcb* instructions.
515 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
516 InstrItinClass itin, list<dag> pattern>
517 : I<31, OOL, IOL, asmstr, itin> {
521 let Pattern = pattern;
523 let Inst{6-10} = immfield;
526 let Inst{21-30} = xo;
531 // DSS_Form - Form X instruction, used for altivec dss* instructions.
532 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
533 InstrItinClass itin, list<dag> pattern>
534 : I<31, OOL, IOL, asmstr, itin> {
540 let Pattern = pattern;
544 let Inst{9-10} = STRM;
547 let Inst{21-30} = xo;
552 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
553 InstrItinClass itin, list<dag> pattern>
554 : I<opcode, OOL, IOL, asmstr, itin> {
559 let Pattern = pattern;
561 let Inst{6-10} = CRD;
562 let Inst{11-15} = CRA;
563 let Inst{16-20} = CRB;
564 let Inst{21-30} = xo;
568 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
569 InstrItinClass itin, list<dag> pattern>
570 : I<opcode, OOL, IOL, asmstr, itin> {
573 let Pattern = pattern;
575 let Inst{6-10} = CRD;
576 let Inst{11-15} = CRD;
577 let Inst{16-20} = CRD;
578 let Inst{21-30} = xo;
582 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
583 InstrItinClass itin, list<dag> pattern>
584 : I<opcode, OOL, IOL, asmstr, itin> {
589 let Pattern = pattern;
592 let Inst{11-15} = BI;
594 let Inst{19-20} = BH;
595 let Inst{21-30} = xo;
599 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
600 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
601 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
602 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
606 let BI{0-1} = BIBO{5-6};
607 let BI{2-4} = CR{0-2};
612 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
613 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
614 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
620 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
622 : I<opcode, OOL, IOL, asmstr, itin> {
628 let Inst{11-13} = BFA;
631 let Inst{21-30} = xo;
636 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
638 : I<opcode, OOL, IOL, asmstr, itin> {
643 let Inst{11} = SPR{4};
644 let Inst{12} = SPR{3};
645 let Inst{13} = SPR{2};
646 let Inst{14} = SPR{1};
647 let Inst{15} = SPR{0};
648 let Inst{16} = SPR{9};
649 let Inst{17} = SPR{8};
650 let Inst{18} = SPR{7};
651 let Inst{19} = SPR{6};
652 let Inst{20} = SPR{5};
653 let Inst{21-30} = xo;
657 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
658 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
659 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
663 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
665 : I<opcode, OOL, IOL, asmstr, itin> {
670 let Inst{21-30} = xo;
674 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
676 : I<opcode, OOL, IOL, asmstr, itin> {
682 let Inst{12-19} = FXM;
684 let Inst{21-30} = xo;
688 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
690 : I<opcode, OOL, IOL, asmstr, itin> {
696 let Inst{12-19} = FXM;
698 let Inst{21-30} = xo;
702 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
704 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
706 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
707 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
708 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
713 // This is probably 1.7.9, but I don't have the reference that uses this
714 // numbering scheme...
715 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
716 InstrItinClass itin, list<dag>pattern>
717 : I<opcode, OOL, IOL, asmstr, itin> {
721 bit RC = 0; // set by isDOT
722 let Pattern = pattern;
727 let Inst{16-20} = rT;
728 let Inst{21-30} = xo;
732 // 1.7.10 XS-Form - SRADI.
733 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
734 InstrItinClass itin, list<dag> pattern>
735 : I<opcode, OOL, IOL, asmstr, itin> {
740 bit RC = 0; // set by isDOT
741 let Pattern = pattern;
745 let Inst{16-20} = SH{4,3,2,1,0};
746 let Inst{21-29} = xo;
747 let Inst{30} = SH{5};
752 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
753 InstrItinClass itin, list<dag> pattern>
754 : I<opcode, OOL, IOL, asmstr, itin> {
759 let Pattern = pattern;
761 bit RC = 0; // set by isDOT
764 let Inst{11-15} = RA;
765 let Inst{16-20} = RB;
767 let Inst{22-30} = xo;
771 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
772 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
773 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
778 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
779 InstrItinClass itin, list<dag> pattern>
780 : I<opcode, OOL, IOL, asmstr, itin> {
786 let Pattern = pattern;
788 bit RC = 0; // set by isDOT
790 let Inst{6-10} = FRT;
791 let Inst{11-15} = FRA;
792 let Inst{16-20} = FRB;
793 let Inst{21-25} = FRC;
794 let Inst{26-30} = xo;
798 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
799 InstrItinClass itin, list<dag> pattern>
800 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
804 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
805 InstrItinClass itin, list<dag> pattern>
806 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
810 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
811 InstrItinClass itin, list<dag> pattern>
812 : I<opcode, OOL, IOL, asmstr, itin> {
818 let Pattern = pattern;
821 let Inst{11-15} = RA;
822 let Inst{16-20} = RB;
823 let Inst{21-25} = COND;
824 let Inst{26-30} = xo;
829 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
830 InstrItinClass itin, list<dag> pattern>
831 : I<opcode, OOL, IOL, asmstr, itin> {
838 let Pattern = pattern;
840 bit RC = 0; // set by isDOT
843 let Inst{11-15} = RA;
844 let Inst{16-20} = RB;
845 let Inst{21-25} = MB;
846 let Inst{26-30} = ME;
850 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
851 InstrItinClass itin, list<dag> pattern>
852 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
856 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
857 InstrItinClass itin, list<dag> pattern>
858 : I<opcode, OOL, IOL, asmstr, itin> {
864 let Pattern = pattern;
866 bit RC = 0; // set by isDOT
869 let Inst{11-15} = RA;
870 let Inst{16-20} = SH{4,3,2,1,0};
871 let Inst{21-26} = MBE{4,3,2,1,0,5};
872 let Inst{27-29} = xo;
873 let Inst{30} = SH{5};
877 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
878 InstrItinClass itin, list<dag> pattern>
879 : I<opcode, OOL, IOL, asmstr, itin> {
885 let Pattern = pattern;
887 bit RC = 0; // set by isDOT
890 let Inst{11-15} = RA;
891 let Inst{16-20} = RB;
892 let Inst{21-26} = MBE{4,3,2,1,0,5};
893 let Inst{27-30} = xo;
900 // VAForm_1 - DACB ordering.
901 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
902 InstrItinClass itin, list<dag> pattern>
903 : I<4, OOL, IOL, asmstr, itin> {
909 let Pattern = pattern;
912 let Inst{11-15} = VA;
913 let Inst{16-20} = VB;
914 let Inst{21-25} = VC;
915 let Inst{26-31} = xo;
918 // VAForm_1a - DABC ordering.
919 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
920 InstrItinClass itin, list<dag> pattern>
921 : I<4, OOL, IOL, asmstr, itin> {
927 let Pattern = pattern;
930 let Inst{11-15} = VA;
931 let Inst{16-20} = VB;
932 let Inst{21-25} = VC;
933 let Inst{26-31} = xo;
936 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
937 InstrItinClass itin, list<dag> pattern>
938 : I<4, OOL, IOL, asmstr, itin> {
944 let Pattern = pattern;
947 let Inst{11-15} = VA;
948 let Inst{16-20} = VB;
950 let Inst{22-25} = SH;
951 let Inst{26-31} = xo;
955 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
956 InstrItinClass itin, list<dag> pattern>
957 : I<4, OOL, IOL, asmstr, itin> {
962 let Pattern = pattern;
965 let Inst{11-15} = VA;
966 let Inst{16-20} = VB;
967 let Inst{21-31} = xo;
970 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
971 InstrItinClass itin, list<dag> pattern>
972 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
978 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
979 InstrItinClass itin, list<dag> pattern>
980 : I<4, OOL, IOL, asmstr, itin> {
984 let Pattern = pattern;
988 let Inst{16-20} = VB;
989 let Inst{21-31} = xo;
992 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
993 InstrItinClass itin, list<dag> pattern>
994 : I<4, OOL, IOL, asmstr, itin> {
998 let Pattern = pattern;
1000 let Inst{6-10} = VD;
1001 let Inst{11-15} = IMM;
1002 let Inst{16-20} = 0;
1003 let Inst{21-31} = xo;
1006 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1007 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1008 InstrItinClass itin, list<dag> pattern>
1009 : I<4, OOL, IOL, asmstr, itin> {
1012 let Pattern = pattern;
1014 let Inst{6-10} = VD;
1015 let Inst{11-15} = 0;
1016 let Inst{16-20} = 0;
1017 let Inst{21-31} = xo;
1020 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1021 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1022 InstrItinClass itin, list<dag> pattern>
1023 : I<4, OOL, IOL, asmstr, itin> {
1026 let Pattern = pattern;
1029 let Inst{11-15} = 0;
1030 let Inst{16-20} = VB;
1031 let Inst{21-31} = xo;
1035 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1036 InstrItinClass itin, list<dag> pattern>
1037 : I<4, OOL, IOL, asmstr, itin> {
1043 let Pattern = pattern;
1045 let Inst{6-10} = VD;
1046 let Inst{11-15} = VA;
1047 let Inst{16-20} = VB;
1049 let Inst{22-31} = xo;
1052 //===----------------------------------------------------------------------===//
1053 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1054 : I<0, OOL, IOL, asmstr, NoItinerary> {
1055 let isCodeGenOnly = 1;
1057 let Pattern = pattern;