1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
388 // This is the same as XForm_base_r3xo, but the first two operands are swapped
389 // when code is emitted.
390 class XForm_base_r3xo_swapped
391 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
393 : I<opcode, OOL, IOL, asmstr, itin> {
398 bit RC = 0; // set by isDOT
400 let Inst{6-10} = RST;
403 let Inst{21-30} = xo;
408 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
409 InstrItinClass itin, list<dag> pattern>
410 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
412 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
413 InstrItinClass itin, list<dag> pattern>
414 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
418 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
419 InstrItinClass itin, list<dag> pattern>
420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
425 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
426 InstrItinClass itin, list<dag> pattern>
427 : I<opcode, OOL, IOL, asmstr, itin> {
432 let Pattern = pattern;
434 let Inst{6-10} = RST;
437 let Inst{21-30} = xo;
441 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
442 InstrItinClass itin, list<dag> pattern>
443 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
444 let Pattern = pattern;
447 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
448 InstrItinClass itin, list<dag> pattern>
449 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
451 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
452 InstrItinClass itin, list<dag> pattern>
453 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
454 let Pattern = pattern;
457 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
458 InstrItinClass itin, list<dag> pattern>
459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
461 let Pattern = pattern;
464 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
466 : I<opcode, OOL, IOL, asmstr, itin> {
475 let Inst{11-15} = RA;
476 let Inst{16-20} = RB;
477 let Inst{21-30} = xo;
481 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
483 : I<opcode, OOL, IOL, asmstr, itin> {
490 let Inst{11-15} = RA;
491 let Inst{16-20} = RB;
492 let Inst{21-30} = xo;
496 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
498 : I<opcode, OOL, IOL, asmstr, itin> {
503 let Inst{12-15} = SR;
504 let Inst{21-30} = xo;
507 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
509 : I<opcode, OOL, IOL, asmstr, itin> {
513 let Inst{21-30} = xo;
516 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
518 : I<opcode, OOL, IOL, asmstr, itin> {
523 let Inst{16-20} = RB;
524 let Inst{21-30} = xo;
527 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
529 : I<opcode, OOL, IOL, asmstr, itin> {
535 let Inst{21-30} = xo;
538 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
540 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
544 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
546 : I<opcode, OOL, IOL, asmstr, itin> {
553 let Inst{11-15} = FRA;
554 let Inst{16-20} = FRB;
555 let Inst{21-30} = xo;
559 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
560 InstrItinClass itin, list<dag> pattern>
561 : I<opcode, OOL, IOL, asmstr, itin> {
562 let Pattern = pattern;
566 let Inst{21-30} = xo;
570 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
571 string asmstr, InstrItinClass itin, list<dag> pattern>
572 : I<opcode, OOL, IOL, asmstr, itin> {
575 let Pattern = pattern;
580 let Inst{21-30} = xo;
584 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
585 string asmstr, InstrItinClass itin, list<dag> pattern>
586 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
590 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
591 InstrItinClass itin, list<dag> pattern>
592 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
595 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
596 InstrItinClass itin, list<dag> pattern>
597 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
601 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
602 InstrItinClass itin, list<dag> pattern>
603 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
606 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
607 // numbers presumably relates to some document, but I haven't found it.
608 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
609 InstrItinClass itin, list<dag> pattern>
610 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
611 let Pattern = pattern;
613 bit RC = 0; // set by isDOT
615 let Inst{6-10} = RST;
617 let Inst{21-30} = xo;
620 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
621 InstrItinClass itin, list<dag> pattern>
622 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
623 let Pattern = pattern;
626 bit RC = 0; // set by isDOT
630 let Inst{21-30} = xo;
634 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
635 InstrItinClass itin, list<dag> pattern>
636 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
642 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
643 InstrItinClass itin, list<dag> pattern>
644 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
650 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
651 InstrItinClass itin, list<dag> pattern>
652 : I<opcode, OOL, IOL, asmstr, itin> {
657 let Pattern = pattern;
659 let Inst{6-10} = XT{4-0};
662 let Inst{21-30} = xo;
663 let Inst{31} = XT{5};
666 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
667 InstrItinClass itin, list<dag> pattern>
668 : I<opcode, OOL, IOL, asmstr, itin> {
672 let Pattern = pattern;
674 let Inst{6-10} = XT{4-0};
676 let Inst{16-20} = XB{4-0};
677 let Inst{21-29} = xo;
678 let Inst{30} = XB{5};
679 let Inst{31} = XT{5};
682 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
683 InstrItinClass itin, list<dag> pattern>
684 : I<opcode, OOL, IOL, asmstr, itin> {
688 let Pattern = pattern;
692 let Inst{16-20} = XB{4-0};
693 let Inst{21-29} = xo;
694 let Inst{30} = XB{5};
698 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
699 InstrItinClass itin, list<dag> pattern>
700 : I<opcode, OOL, IOL, asmstr, itin> {
705 let Pattern = pattern;
707 let Inst{6-10} = XT{4-0};
710 let Inst{16-20} = XB{4-0};
711 let Inst{21-29} = xo;
712 let Inst{30} = XB{5};
713 let Inst{31} = XT{5};
716 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
717 InstrItinClass itin, list<dag> pattern>
718 : I<opcode, OOL, IOL, asmstr, itin> {
723 let Pattern = pattern;
725 let Inst{6-10} = XT{4-0};
726 let Inst{11-15} = XA{4-0};
727 let Inst{16-20} = XB{4-0};
728 let Inst{21-28} = xo;
729 let Inst{29} = XA{5};
730 let Inst{30} = XB{5};
731 let Inst{31} = XT{5};
734 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
735 InstrItinClass itin, list<dag> pattern>
736 : I<opcode, OOL, IOL, asmstr, itin> {
741 let Pattern = pattern;
745 let Inst{11-15} = XA{4-0};
746 let Inst{16-20} = XB{4-0};
747 let Inst{21-28} = xo;
748 let Inst{29} = XA{5};
749 let Inst{30} = XB{5};
753 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
754 InstrItinClass itin, list<dag> pattern>
755 : I<opcode, OOL, IOL, asmstr, itin> {
761 let Pattern = pattern;
763 let Inst{6-10} = XT{4-0};
764 let Inst{11-15} = XA{4-0};
765 let Inst{16-20} = XB{4-0};
768 let Inst{24-28} = xo;
769 let Inst{29} = XA{5};
770 let Inst{30} = XB{5};
771 let Inst{31} = XT{5};
774 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
775 InstrItinClass itin, list<dag> pattern>
776 : I<opcode, OOL, IOL, asmstr, itin> {
781 let Pattern = pattern;
783 bit RC = 0; // set by isDOT
785 let Inst{6-10} = XT{4-0};
786 let Inst{11-15} = XA{4-0};
787 let Inst{16-20} = XB{4-0};
789 let Inst{22-28} = xo;
790 let Inst{29} = XA{5};
791 let Inst{30} = XB{5};
792 let Inst{31} = XT{5};
795 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
796 InstrItinClass itin, list<dag> pattern>
797 : I<opcode, OOL, IOL, asmstr, itin> {
803 let Pattern = pattern;
805 let Inst{6-10} = XT{4-0};
806 let Inst{11-15} = XA{4-0};
807 let Inst{16-20} = XB{4-0};
808 let Inst{21-25} = XC{4-0};
809 let Inst{26-27} = xo;
810 let Inst{28} = XC{5};
811 let Inst{29} = XA{5};
812 let Inst{30} = XB{5};
813 let Inst{31} = XT{5};
816 // DCB_Form - Form X instruction, used for dcb* instructions.
817 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
818 InstrItinClass itin, list<dag> pattern>
819 : I<31, OOL, IOL, asmstr, itin> {
823 let Pattern = pattern;
825 let Inst{6-10} = immfield;
828 let Inst{21-30} = xo;
833 // DSS_Form - Form X instruction, used for altivec dss* instructions.
834 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
835 InstrItinClass itin, list<dag> pattern>
836 : I<31, OOL, IOL, asmstr, itin> {
841 let Pattern = pattern;
845 let Inst{9-10} = STRM;
848 let Inst{21-30} = xo;
853 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
854 InstrItinClass itin, list<dag> pattern>
855 : I<opcode, OOL, IOL, asmstr, itin> {
860 let Pattern = pattern;
862 let Inst{6-10} = CRD;
863 let Inst{11-15} = CRA;
864 let Inst{16-20} = CRB;
865 let Inst{21-30} = xo;
869 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
870 InstrItinClass itin, list<dag> pattern>
871 : I<opcode, OOL, IOL, asmstr, itin> {
874 let Pattern = pattern;
876 let Inst{6-10} = CRD;
877 let Inst{11-15} = CRD;
878 let Inst{16-20} = CRD;
879 let Inst{21-30} = xo;
883 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
884 InstrItinClass itin, list<dag> pattern>
885 : I<opcode, OOL, IOL, asmstr, itin> {
890 let Pattern = pattern;
893 let Inst{11-15} = BI;
895 let Inst{19-20} = BH;
896 let Inst{21-30} = xo;
900 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
901 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
902 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
903 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
907 let BI{0-1} = BIBO{5-6};
908 let BI{2-4} = CR{0-2};
912 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
913 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
914 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
919 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
920 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
921 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
927 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
929 : I<opcode, OOL, IOL, asmstr, itin> {
935 let Inst{11-13} = BFA;
938 let Inst{21-30} = xo;
943 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
945 : I<opcode, OOL, IOL, asmstr, itin> {
950 let Inst{11} = SPR{4};
951 let Inst{12} = SPR{3};
952 let Inst{13} = SPR{2};
953 let Inst{14} = SPR{1};
954 let Inst{15} = SPR{0};
955 let Inst{16} = SPR{9};
956 let Inst{17} = SPR{8};
957 let Inst{18} = SPR{7};
958 let Inst{19} = SPR{6};
959 let Inst{20} = SPR{5};
960 let Inst{21-30} = xo;
964 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
965 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
966 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
970 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
972 : I<opcode, OOL, IOL, asmstr, itin> {
977 let Inst{21-30} = xo;
981 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
983 : I<opcode, OOL, IOL, asmstr, itin> {
989 let Inst{12-19} = FXM;
991 let Inst{21-30} = xo;
995 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
997 : I<opcode, OOL, IOL, asmstr, itin> {
1001 let Inst{6-10} = ST;
1003 let Inst{12-19} = FXM;
1005 let Inst{21-30} = xo;
1009 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1010 InstrItinClass itin>
1011 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1013 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1014 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1015 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1020 // This is probably 1.7.9, but I don't have the reference that uses this
1021 // numbering scheme...
1022 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1023 InstrItinClass itin, list<dag>pattern>
1024 : I<opcode, OOL, IOL, asmstr, itin> {
1028 bit RC = 0; // set by isDOT
1029 let Pattern = pattern;
1032 let Inst{7-14} = FM;
1034 let Inst{16-20} = rT;
1035 let Inst{21-30} = xo;
1039 // 1.7.10 XS-Form - SRADI.
1040 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1041 InstrItinClass itin, list<dag> pattern>
1042 : I<opcode, OOL, IOL, asmstr, itin> {
1047 bit RC = 0; // set by isDOT
1048 let Pattern = pattern;
1050 let Inst{6-10} = RS;
1051 let Inst{11-15} = A;
1052 let Inst{16-20} = SH{4,3,2,1,0};
1053 let Inst{21-29} = xo;
1054 let Inst{30} = SH{5};
1059 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1060 InstrItinClass itin, list<dag> pattern>
1061 : I<opcode, OOL, IOL, asmstr, itin> {
1066 let Pattern = pattern;
1068 bit RC = 0; // set by isDOT
1070 let Inst{6-10} = RT;
1071 let Inst{11-15} = RA;
1072 let Inst{16-20} = RB;
1074 let Inst{22-30} = xo;
1078 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1079 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1080 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1085 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1086 InstrItinClass itin, list<dag> pattern>
1087 : I<opcode, OOL, IOL, asmstr, itin> {
1093 let Pattern = pattern;
1095 bit RC = 0; // set by isDOT
1097 let Inst{6-10} = FRT;
1098 let Inst{11-15} = FRA;
1099 let Inst{16-20} = FRB;
1100 let Inst{21-25} = FRC;
1101 let Inst{26-30} = xo;
1105 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1106 InstrItinClass itin, list<dag> pattern>
1107 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1111 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1112 InstrItinClass itin, list<dag> pattern>
1113 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1117 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1118 InstrItinClass itin, list<dag> pattern>
1119 : I<opcode, OOL, IOL, asmstr, itin> {
1125 let Pattern = pattern;
1127 let Inst{6-10} = RT;
1128 let Inst{11-15} = RA;
1129 let Inst{16-20} = RB;
1130 let Inst{21-25} = COND;
1131 let Inst{26-30} = xo;
1136 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1137 InstrItinClass itin, list<dag> pattern>
1138 : I<opcode, OOL, IOL, asmstr, itin> {
1145 let Pattern = pattern;
1147 bit RC = 0; // set by isDOT
1149 let Inst{6-10} = RS;
1150 let Inst{11-15} = RA;
1151 let Inst{16-20} = RB;
1152 let Inst{21-25} = MB;
1153 let Inst{26-30} = ME;
1157 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1158 InstrItinClass itin, list<dag> pattern>
1159 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1163 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1164 InstrItinClass itin, list<dag> pattern>
1165 : I<opcode, OOL, IOL, asmstr, itin> {
1171 let Pattern = pattern;
1173 bit RC = 0; // set by isDOT
1175 let Inst{6-10} = RS;
1176 let Inst{11-15} = RA;
1177 let Inst{16-20} = SH{4,3,2,1,0};
1178 let Inst{21-26} = MBE{4,3,2,1,0,5};
1179 let Inst{27-29} = xo;
1180 let Inst{30} = SH{5};
1184 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1185 InstrItinClass itin, list<dag> pattern>
1186 : I<opcode, OOL, IOL, asmstr, itin> {
1192 let Pattern = pattern;
1194 bit RC = 0; // set by isDOT
1196 let Inst{6-10} = RS;
1197 let Inst{11-15} = RA;
1198 let Inst{16-20} = RB;
1199 let Inst{21-26} = MBE{4,3,2,1,0,5};
1200 let Inst{27-30} = xo;
1207 // VAForm_1 - DACB ordering.
1208 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1209 InstrItinClass itin, list<dag> pattern>
1210 : I<4, OOL, IOL, asmstr, itin> {
1216 let Pattern = pattern;
1218 let Inst{6-10} = VD;
1219 let Inst{11-15} = VA;
1220 let Inst{16-20} = VB;
1221 let Inst{21-25} = VC;
1222 let Inst{26-31} = xo;
1225 // VAForm_1a - DABC ordering.
1226 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1227 InstrItinClass itin, list<dag> pattern>
1228 : I<4, OOL, IOL, asmstr, itin> {
1234 let Pattern = pattern;
1236 let Inst{6-10} = VD;
1237 let Inst{11-15} = VA;
1238 let Inst{16-20} = VB;
1239 let Inst{21-25} = VC;
1240 let Inst{26-31} = xo;
1243 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1244 InstrItinClass itin, list<dag> pattern>
1245 : I<4, OOL, IOL, asmstr, itin> {
1251 let Pattern = pattern;
1253 let Inst{6-10} = VD;
1254 let Inst{11-15} = VA;
1255 let Inst{16-20} = VB;
1257 let Inst{22-25} = SH;
1258 let Inst{26-31} = xo;
1262 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1263 InstrItinClass itin, list<dag> pattern>
1264 : I<4, OOL, IOL, asmstr, itin> {
1269 let Pattern = pattern;
1271 let Inst{6-10} = VD;
1272 let Inst{11-15} = VA;
1273 let Inst{16-20} = VB;
1274 let Inst{21-31} = xo;
1277 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1278 InstrItinClass itin, list<dag> pattern>
1279 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1285 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1286 InstrItinClass itin, list<dag> pattern>
1287 : I<4, OOL, IOL, asmstr, itin> {
1291 let Pattern = pattern;
1293 let Inst{6-10} = VD;
1294 let Inst{11-15} = 0;
1295 let Inst{16-20} = VB;
1296 let Inst{21-31} = xo;
1299 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1300 InstrItinClass itin, list<dag> pattern>
1301 : I<4, OOL, IOL, asmstr, itin> {
1305 let Pattern = pattern;
1307 let Inst{6-10} = VD;
1308 let Inst{11-15} = IMM;
1309 let Inst{16-20} = 0;
1310 let Inst{21-31} = xo;
1313 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1314 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1315 InstrItinClass itin, list<dag> pattern>
1316 : I<4, OOL, IOL, asmstr, itin> {
1319 let Pattern = pattern;
1321 let Inst{6-10} = VD;
1322 let Inst{11-15} = 0;
1323 let Inst{16-20} = 0;
1324 let Inst{21-31} = xo;
1327 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1328 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1329 InstrItinClass itin, list<dag> pattern>
1330 : I<4, OOL, IOL, asmstr, itin> {
1333 let Pattern = pattern;
1336 let Inst{11-15} = 0;
1337 let Inst{16-20} = VB;
1338 let Inst{21-31} = xo;
1342 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1343 InstrItinClass itin, list<dag> pattern>
1344 : I<4, OOL, IOL, asmstr, itin> {
1350 let Pattern = pattern;
1352 let Inst{6-10} = VD;
1353 let Inst{11-15} = VA;
1354 let Inst{16-20} = VB;
1356 let Inst{22-31} = xo;
1359 //===----------------------------------------------------------------------===//
1360 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1361 : I<0, OOL, IOL, asmstr, NoItinerary> {
1362 let isCodeGenOnly = 1;
1364 let Pattern = pattern;