1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
388 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
390 : I<opcode, OOL, IOL, asmstr, itin> {
391 let Inst{21-30} = xo;
394 // This is the same as XForm_base_r3xo, but the first two operands are swapped
395 // when code is emitted.
396 class XForm_base_r3xo_swapped
397 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
399 : I<opcode, OOL, IOL, asmstr, itin> {
404 bit RC = 0; // set by isDOT
406 let Inst{6-10} = RST;
409 let Inst{21-30} = xo;
414 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
415 InstrItinClass itin, list<dag> pattern>
416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
418 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
419 InstrItinClass itin, list<dag> pattern>
420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
424 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
425 InstrItinClass itin, list<dag> pattern>
426 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
431 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
432 InstrItinClass itin, list<dag> pattern>
433 : I<opcode, OOL, IOL, asmstr, itin> {
438 let Pattern = pattern;
440 let Inst{6-10} = RST;
443 let Inst{21-30} = xo;
447 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
448 InstrItinClass itin, list<dag> pattern>
449 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
450 let Pattern = pattern;
453 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
454 InstrItinClass itin, list<dag> pattern>
455 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
457 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
458 InstrItinClass itin, list<dag> pattern>
459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
460 let Pattern = pattern;
463 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
464 InstrItinClass itin, list<dag> pattern>
465 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
467 let Pattern = pattern;
470 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
472 : I<opcode, OOL, IOL, asmstr, itin> {
481 let Inst{11-15} = RA;
482 let Inst{16-20} = RB;
483 let Inst{21-30} = xo;
487 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
489 : I<opcode, OOL, IOL, asmstr, itin> {
496 let Inst{11-15} = RA;
497 let Inst{16-20} = RB;
498 let Inst{21-30} = xo;
502 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
504 : I<opcode, OOL, IOL, asmstr, itin> {
509 let Inst{12-15} = SR;
510 let Inst{21-30} = xo;
513 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
515 : I<opcode, OOL, IOL, asmstr, itin> {
519 let Inst{21-30} = xo;
522 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
524 : I<opcode, OOL, IOL, asmstr, itin> {
529 let Inst{16-20} = RB;
530 let Inst{21-30} = xo;
533 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
535 : I<opcode, OOL, IOL, asmstr, itin> {
541 let Inst{21-30} = xo;
544 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
546 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
550 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
552 : I<opcode, OOL, IOL, asmstr, itin> {
559 let Inst{11-15} = FRA;
560 let Inst{16-20} = FRB;
561 let Inst{21-30} = xo;
566 class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
567 InstrItinClass itin, list<dag> pattern>
568 : I<opcode, OOL, IOL, asmstr, itin> {
573 let Pattern = pattern;
575 let Inst{6-10} = FRT;
576 let Inst{11-15} = FRA;
577 let Inst{16-20} = FRB;
578 let Inst{21-30} = xo;
582 class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
583 InstrItinClass itin, list<dag> pattern>
584 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
588 class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
589 InstrItinClass itin, list<dag> pattern>
590 : I<opcode, OOL, IOL, asmstr, itin> {
596 let Pattern = pattern;
598 let Inst{6-10} = FRT;
599 let Inst{11-15} = FRA;
600 let Inst{16-20} = FRB;
601 let Inst{21-24} = tttt;
602 let Inst{25-30} = xo;
606 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
607 InstrItinClass itin, list<dag> pattern>
608 : I<opcode, OOL, IOL, asmstr, itin> {
609 let Pattern = pattern;
613 let Inst{21-30} = xo;
617 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
618 string asmstr, InstrItinClass itin, list<dag> pattern>
619 : I<opcode, OOL, IOL, asmstr, itin> {
622 let Pattern = pattern;
627 let Inst{21-30} = xo;
631 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
632 string asmstr, InstrItinClass itin, list<dag> pattern>
633 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
637 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
638 InstrItinClass itin, list<dag> pattern>
639 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
642 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
643 InstrItinClass itin, list<dag> pattern>
644 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
648 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
649 InstrItinClass itin, list<dag> pattern>
650 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
653 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
654 // numbers presumably relates to some document, but I haven't found it.
655 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
656 InstrItinClass itin, list<dag> pattern>
657 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
658 let Pattern = pattern;
660 bit RC = 0; // set by isDOT
662 let Inst{6-10} = RST;
664 let Inst{21-30} = xo;
667 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
668 InstrItinClass itin, list<dag> pattern>
669 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
670 let Pattern = pattern;
673 bit RC = 0; // set by isDOT
677 let Inst{21-30} = xo;
681 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
682 InstrItinClass itin, list<dag> pattern>
683 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
689 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
690 InstrItinClass itin, list<dag> pattern>
691 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
696 class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
697 string asmstr, InstrItinClass itin, list<dag> pattern>
698 : I<opcode, OOL, IOL, asmstr, itin> {
706 let Inst{21-30} = xo;
710 class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
711 string asmstr, InstrItinClass itin, list<dag> pattern>
712 : I<opcode, OOL, IOL, asmstr, itin> {
719 let Inst{21-30} = xo;
723 class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
724 InstrItinClass itin, list<dag> pattern>
725 : I<opcode, OOL, IOL, asmstr, itin> {
728 bit RC = 0; // set by isDOT
733 let Inst{21-30} = xo;
737 class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
738 InstrItinClass itin, list<dag> pattern>
739 : I<opcode, OOL, IOL, asmstr, itin> {
746 let Inst{21-30} = xo;
751 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
752 InstrItinClass itin, list<dag> pattern>
753 : I<opcode, OOL, IOL, asmstr, itin> {
758 let Pattern = pattern;
760 let Inst{6-10} = XT{4-0};
763 let Inst{21-30} = xo;
764 let Inst{31} = XT{5};
767 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
768 InstrItinClass itin, list<dag> pattern>
769 : I<opcode, OOL, IOL, asmstr, itin> {
773 let Pattern = pattern;
775 let Inst{6-10} = XT{4-0};
777 let Inst{16-20} = XB{4-0};
778 let Inst{21-29} = xo;
779 let Inst{30} = XB{5};
780 let Inst{31} = XT{5};
783 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
784 InstrItinClass itin, list<dag> pattern>
785 : I<opcode, OOL, IOL, asmstr, itin> {
789 let Pattern = pattern;
793 let Inst{16-20} = XB{4-0};
794 let Inst{21-29} = xo;
795 let Inst{30} = XB{5};
799 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
800 InstrItinClass itin, list<dag> pattern>
801 : I<opcode, OOL, IOL, asmstr, itin> {
806 let Pattern = pattern;
808 let Inst{6-10} = XT{4-0};
811 let Inst{16-20} = XB{4-0};
812 let Inst{21-29} = xo;
813 let Inst{30} = XB{5};
814 let Inst{31} = XT{5};
817 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
818 InstrItinClass itin, list<dag> pattern>
819 : I<opcode, OOL, IOL, asmstr, itin> {
824 let Pattern = pattern;
826 let Inst{6-10} = XT{4-0};
827 let Inst{11-15} = XA{4-0};
828 let Inst{16-20} = XB{4-0};
829 let Inst{21-28} = xo;
830 let Inst{29} = XA{5};
831 let Inst{30} = XB{5};
832 let Inst{31} = XT{5};
835 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
836 InstrItinClass itin, list<dag> pattern>
837 : I<opcode, OOL, IOL, asmstr, itin> {
842 let Pattern = pattern;
846 let Inst{11-15} = XA{4-0};
847 let Inst{16-20} = XB{4-0};
848 let Inst{21-28} = xo;
849 let Inst{29} = XA{5};
850 let Inst{30} = XB{5};
854 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
855 InstrItinClass itin, list<dag> pattern>
856 : I<opcode, OOL, IOL, asmstr, itin> {
862 let Pattern = pattern;
864 let Inst{6-10} = XT{4-0};
865 let Inst{11-15} = XA{4-0};
866 let Inst{16-20} = XB{4-0};
869 let Inst{24-28} = xo;
870 let Inst{29} = XA{5};
871 let Inst{30} = XB{5};
872 let Inst{31} = XT{5};
875 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
876 InstrItinClass itin, list<dag> pattern>
877 : I<opcode, OOL, IOL, asmstr, itin> {
882 let Pattern = pattern;
884 bit RC = 0; // set by isDOT
886 let Inst{6-10} = XT{4-0};
887 let Inst{11-15} = XA{4-0};
888 let Inst{16-20} = XB{4-0};
890 let Inst{22-28} = xo;
891 let Inst{29} = XA{5};
892 let Inst{30} = XB{5};
893 let Inst{31} = XT{5};
896 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
897 InstrItinClass itin, list<dag> pattern>
898 : I<opcode, OOL, IOL, asmstr, itin> {
904 let Pattern = pattern;
906 let Inst{6-10} = XT{4-0};
907 let Inst{11-15} = XA{4-0};
908 let Inst{16-20} = XB{4-0};
909 let Inst{21-25} = XC{4-0};
910 let Inst{26-27} = xo;
911 let Inst{28} = XC{5};
912 let Inst{29} = XA{5};
913 let Inst{30} = XB{5};
914 let Inst{31} = XT{5};
917 // DCB_Form - Form X instruction, used for dcb* instructions.
918 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
919 InstrItinClass itin, list<dag> pattern>
920 : I<31, OOL, IOL, asmstr, itin> {
924 let Pattern = pattern;
926 let Inst{6-10} = immfield;
929 let Inst{21-30} = xo;
934 // DSS_Form - Form X instruction, used for altivec dss* instructions.
935 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
936 InstrItinClass itin, list<dag> pattern>
937 : I<31, OOL, IOL, asmstr, itin> {
942 let Pattern = pattern;
946 let Inst{9-10} = STRM;
949 let Inst{21-30} = xo;
954 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
955 InstrItinClass itin, list<dag> pattern>
956 : I<opcode, OOL, IOL, asmstr, itin> {
961 let Pattern = pattern;
963 let Inst{6-10} = CRD;
964 let Inst{11-15} = CRA;
965 let Inst{16-20} = CRB;
966 let Inst{21-30} = xo;
970 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
971 InstrItinClass itin, list<dag> pattern>
972 : I<opcode, OOL, IOL, asmstr, itin> {
975 let Pattern = pattern;
977 let Inst{6-10} = CRD;
978 let Inst{11-15} = CRD;
979 let Inst{16-20} = CRD;
980 let Inst{21-30} = xo;
984 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
985 InstrItinClass itin, list<dag> pattern>
986 : I<opcode, OOL, IOL, asmstr, itin> {
991 let Pattern = pattern;
994 let Inst{11-15} = BI;
996 let Inst{19-20} = BH;
997 let Inst{21-30} = xo;
1001 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
1002 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1003 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1004 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
1008 let BI{0-1} = BIBO{5-6};
1009 let BI{2-4} = CR{0-2};
1013 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
1014 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1015 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1020 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
1021 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1022 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1028 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1029 InstrItinClass itin>
1030 : I<opcode, OOL, IOL, asmstr, itin> {
1036 let Inst{11-13} = BFA;
1037 let Inst{14-15} = 0;
1038 let Inst{16-20} = 0;
1039 let Inst{21-30} = xo;
1043 class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1044 InstrItinClass itin>
1045 : I<opcode, OOL, IOL, asmstr, itin> {
1054 let Inst{11-14} = 0;
1056 let Inst{16-19} = U;
1058 let Inst{21-30} = xo;
1062 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1063 bits<6> opcode2, bits<2> xo2,
1064 dag OOL, dag IOL, string asmstr,
1065 InstrItinClass itin, list<dag> pattern>
1066 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1074 let Pattern = pattern;
1076 let Inst{6-10} = BO;
1077 let Inst{11-15} = BI;
1078 let Inst{16-18} = 0;
1079 let Inst{19-20} = BH;
1080 let Inst{21-30} = xo1;
1083 let Inst{38-42} = RST;
1084 let Inst{43-47} = DS_RA{18-14}; // Register #
1085 let Inst{48-61} = DS_RA{13-0}; // Displacement.
1086 let Inst{62-63} = xo2;
1089 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1090 bits<5> bo, bits<5> bi, bit lk,
1091 bits<6> opcode2, bits<2> xo2,
1092 dag OOL, dag IOL, string asmstr,
1093 InstrItinClass itin, list<dag> pattern>
1094 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1095 OOL, IOL, asmstr, itin, pattern> {
1102 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1103 InstrItinClass itin>
1104 : I<opcode, OOL, IOL, asmstr, itin> {
1108 let Inst{6-10} = RT;
1109 let Inst{11} = SPR{4};
1110 let Inst{12} = SPR{3};
1111 let Inst{13} = SPR{2};
1112 let Inst{14} = SPR{1};
1113 let Inst{15} = SPR{0};
1114 let Inst{16} = SPR{9};
1115 let Inst{17} = SPR{8};
1116 let Inst{18} = SPR{7};
1117 let Inst{19} = SPR{6};
1118 let Inst{20} = SPR{5};
1119 let Inst{21-30} = xo;
1123 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1124 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1125 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
1129 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1130 InstrItinClass itin>
1131 : I<opcode, OOL, IOL, asmstr, itin> {
1134 let Inst{6-10} = RT;
1135 let Inst{11-20} = 0;
1136 let Inst{21-30} = xo;
1140 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1141 InstrItinClass itin>
1142 : I<opcode, OOL, IOL, asmstr, itin> {
1146 let Inst{6-10} = rS;
1148 let Inst{12-19} = FXM;
1150 let Inst{21-30} = xo;
1154 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1155 InstrItinClass itin>
1156 : I<opcode, OOL, IOL, asmstr, itin> {
1160 let Inst{6-10} = ST;
1162 let Inst{12-19} = FXM;
1164 let Inst{21-30} = xo;
1168 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1169 InstrItinClass itin>
1170 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1172 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1173 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1174 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1179 // This is probably 1.7.9, but I don't have the reference that uses this
1180 // numbering scheme...
1181 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1182 InstrItinClass itin, list<dag>pattern>
1183 : I<opcode, OOL, IOL, asmstr, itin> {
1187 bit RC = 0; // set by isDOT
1188 let Pattern = pattern;
1191 let Inst{7-14} = FM;
1193 let Inst{16-20} = rT;
1194 let Inst{21-30} = xo;
1198 class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1199 InstrItinClass itin, list<dag>pattern>
1200 : I<opcode, OOL, IOL, asmstr, itin> {
1206 bit RC = 0; // set by isDOT
1207 let Pattern = pattern;
1210 let Inst{7-14} = FLM;
1212 let Inst{16-20} = FRB;
1213 let Inst{21-30} = xo;
1217 // 1.7.10 XS-Form - SRADI.
1218 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1219 InstrItinClass itin, list<dag> pattern>
1220 : I<opcode, OOL, IOL, asmstr, itin> {
1225 bit RC = 0; // set by isDOT
1226 let Pattern = pattern;
1228 let Inst{6-10} = RS;
1229 let Inst{11-15} = A;
1230 let Inst{16-20} = SH{4,3,2,1,0};
1231 let Inst{21-29} = xo;
1232 let Inst{30} = SH{5};
1237 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1238 InstrItinClass itin, list<dag> pattern>
1239 : I<opcode, OOL, IOL, asmstr, itin> {
1244 let Pattern = pattern;
1246 bit RC = 0; // set by isDOT
1248 let Inst{6-10} = RT;
1249 let Inst{11-15} = RA;
1250 let Inst{16-20} = RB;
1252 let Inst{22-30} = xo;
1256 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1257 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1258 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1263 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1264 InstrItinClass itin, list<dag> pattern>
1265 : I<opcode, OOL, IOL, asmstr, itin> {
1271 let Pattern = pattern;
1273 bit RC = 0; // set by isDOT
1275 let Inst{6-10} = FRT;
1276 let Inst{11-15} = FRA;
1277 let Inst{16-20} = FRB;
1278 let Inst{21-25} = FRC;
1279 let Inst{26-30} = xo;
1283 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1284 InstrItinClass itin, list<dag> pattern>
1285 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1289 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1290 InstrItinClass itin, list<dag> pattern>
1291 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1295 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1296 InstrItinClass itin, list<dag> pattern>
1297 : I<opcode, OOL, IOL, asmstr, itin> {
1303 let Pattern = pattern;
1305 let Inst{6-10} = RT;
1306 let Inst{11-15} = RA;
1307 let Inst{16-20} = RB;
1308 let Inst{21-25} = COND;
1309 let Inst{26-30} = xo;
1314 class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1315 InstrItinClass itin, list<dag> pattern>
1316 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1322 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1323 InstrItinClass itin, list<dag> pattern>
1324 : I<opcode, OOL, IOL, asmstr, itin> {
1331 let Pattern = pattern;
1333 bit RC = 0; // set by isDOT
1335 let Inst{6-10} = RS;
1336 let Inst{11-15} = RA;
1337 let Inst{16-20} = RB;
1338 let Inst{21-25} = MB;
1339 let Inst{26-30} = ME;
1343 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1344 InstrItinClass itin, list<dag> pattern>
1345 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1349 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1350 InstrItinClass itin, list<dag> pattern>
1351 : I<opcode, OOL, IOL, asmstr, itin> {
1357 let Pattern = pattern;
1359 bit RC = 0; // set by isDOT
1361 let Inst{6-10} = RS;
1362 let Inst{11-15} = RA;
1363 let Inst{16-20} = SH{4,3,2,1,0};
1364 let Inst{21-26} = MBE{4,3,2,1,0,5};
1365 let Inst{27-29} = xo;
1366 let Inst{30} = SH{5};
1370 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1371 InstrItinClass itin, list<dag> pattern>
1372 : I<opcode, OOL, IOL, asmstr, itin> {
1378 let Pattern = pattern;
1380 bit RC = 0; // set by isDOT
1382 let Inst{6-10} = RS;
1383 let Inst{11-15} = RA;
1384 let Inst{16-20} = RB;
1385 let Inst{21-26} = MBE{4,3,2,1,0,5};
1386 let Inst{27-30} = xo;
1393 // VAForm_1 - DACB ordering.
1394 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1395 InstrItinClass itin, list<dag> pattern>
1396 : I<4, OOL, IOL, asmstr, itin> {
1402 let Pattern = pattern;
1404 let Inst{6-10} = VD;
1405 let Inst{11-15} = VA;
1406 let Inst{16-20} = VB;
1407 let Inst{21-25} = VC;
1408 let Inst{26-31} = xo;
1411 // VAForm_1a - DABC ordering.
1412 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1413 InstrItinClass itin, list<dag> pattern>
1414 : I<4, OOL, IOL, asmstr, itin> {
1420 let Pattern = pattern;
1422 let Inst{6-10} = VD;
1423 let Inst{11-15} = VA;
1424 let Inst{16-20} = VB;
1425 let Inst{21-25} = VC;
1426 let Inst{26-31} = xo;
1429 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1430 InstrItinClass itin, list<dag> pattern>
1431 : I<4, OOL, IOL, asmstr, itin> {
1437 let Pattern = pattern;
1439 let Inst{6-10} = VD;
1440 let Inst{11-15} = VA;
1441 let Inst{16-20} = VB;
1443 let Inst{22-25} = SH;
1444 let Inst{26-31} = xo;
1448 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1449 InstrItinClass itin, list<dag> pattern>
1450 : I<4, OOL, IOL, asmstr, itin> {
1455 let Pattern = pattern;
1457 let Inst{6-10} = VD;
1458 let Inst{11-15} = VA;
1459 let Inst{16-20} = VB;
1460 let Inst{21-31} = xo;
1463 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1464 InstrItinClass itin, list<dag> pattern>
1465 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1471 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1472 InstrItinClass itin, list<dag> pattern>
1473 : I<4, OOL, IOL, asmstr, itin> {
1477 let Pattern = pattern;
1479 let Inst{6-10} = VD;
1480 let Inst{11-15} = 0;
1481 let Inst{16-20} = VB;
1482 let Inst{21-31} = xo;
1485 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1486 InstrItinClass itin, list<dag> pattern>
1487 : I<4, OOL, IOL, asmstr, itin> {
1491 let Pattern = pattern;
1493 let Inst{6-10} = VD;
1494 let Inst{11-15} = IMM;
1495 let Inst{16-20} = 0;
1496 let Inst{21-31} = xo;
1499 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1500 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1501 InstrItinClass itin, list<dag> pattern>
1502 : I<4, OOL, IOL, asmstr, itin> {
1505 let Pattern = pattern;
1507 let Inst{6-10} = VD;
1508 let Inst{11-15} = 0;
1509 let Inst{16-20} = 0;
1510 let Inst{21-31} = xo;
1513 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1514 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1515 InstrItinClass itin, list<dag> pattern>
1516 : I<4, OOL, IOL, asmstr, itin> {
1519 let Pattern = pattern;
1522 let Inst{11-15} = 0;
1523 let Inst{16-20} = VB;
1524 let Inst{21-31} = xo;
1527 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
1528 class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
1529 InstrItinClass itin, list<dag> pattern>
1530 : I<4, OOL, IOL, asmstr, itin> {
1536 let Pattern = pattern;
1538 let Inst{6-10} = VD;
1539 let Inst{11-15} = VA;
1541 let Inst{17-20} = SIX;
1542 let Inst{21-31} = xo;
1545 /// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
1546 class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr,
1547 InstrItinClass itin, list<dag> pattern>
1548 : I<4, OOL, IOL, asmstr, itin> {
1552 let Pattern = pattern;
1554 let Inst{6-10} = VD;
1555 let Inst{11-15} = VA;
1556 let Inst{16-20} = 0;
1557 let Inst{21-31} = xo;
1561 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1562 InstrItinClass itin, list<dag> pattern>
1563 : I<4, OOL, IOL, asmstr, itin> {
1569 let Pattern = pattern;
1571 let Inst{6-10} = VD;
1572 let Inst{11-15} = VA;
1573 let Inst{16-20} = VB;
1575 let Inst{22-31} = xo;
1578 // Z23-Form (used by QPX)
1579 class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1580 InstrItinClass itin, list<dag> pattern>
1581 : I<opcode, OOL, IOL, asmstr, itin> {
1587 let Pattern = pattern;
1589 bit RC = 0; // set by isDOT
1591 let Inst{6-10} = FRT;
1592 let Inst{11-15} = FRA;
1593 let Inst{16-20} = FRB;
1594 let Inst{21-22} = idx;
1595 let Inst{23-30} = xo;
1599 class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1600 InstrItinClass itin, list<dag> pattern>
1601 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1605 class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1606 InstrItinClass itin, list<dag> pattern>
1607 : I<opcode, OOL, IOL, asmstr, itin> {
1611 let Pattern = pattern;
1613 bit RC = 0; // set by isDOT
1615 let Inst{6-10} = FRT;
1616 let Inst{11-22} = idx;
1617 let Inst{23-30} = xo;
1621 //===----------------------------------------------------------------------===//
1622 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1623 : I<0, OOL, IOL, asmstr, NoItinerary> {
1624 let isCodeGenOnly = 1;
1626 let Pattern = pattern;