1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
40 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
41 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
42 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
43 class PPC970_MicroCode;
45 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
46 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
47 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
48 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
49 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
50 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
51 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
52 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
54 // Two joined instructions; used to emit two adjacent instructions as one.
55 // The itinerary from the first instruction is used for scheduling and
57 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
62 bit PPC64 = 0; // Default value, override with isPPC64
64 let Namespace = "PPC";
65 let Inst{0-5} = opcode1;
66 let Inst{32-37} = opcode2;
67 let OutOperandList = OOL;
68 let InOperandList = IOL;
69 let AsmString = asmstr;
72 bits<1> PPC970_First = 0;
73 bits<1> PPC970_Single = 0;
74 bits<1> PPC970_Cracked = 0;
75 bits<3> PPC970_Unit = 0;
77 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
78 /// these must be reflected there! See comments there for what these are.
79 let TSFlags{0} = PPC970_First;
80 let TSFlags{1} = PPC970_Single;
81 let TSFlags{2} = PPC970_Cracked;
82 let TSFlags{5-3} = PPC970_Unit;
86 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
87 InstrItinClass itin, list<dag> pattern>
88 : I<opcode, OOL, IOL, asmstr, itin> {
89 let Pattern = pattern;
98 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
99 : I<opcode, OOL, IOL, asmstr, BrB> {
100 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
105 let BI{0-1} = BIBO{5-6};
106 let BI{2-4} = CR{0-2};
108 let Inst{6-10} = BIBO{4-0};
109 let Inst{11-15} = BI;
110 let Inst{16-29} = BD;
115 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
117 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
124 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
125 InstrItinClass itin, list<dag> pattern>
126 : I<opcode, OOL, IOL, asmstr, itin> {
131 let Pattern = pattern;
138 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
139 InstrItinClass itin, list<dag> pattern>
140 : I<opcode, OOL, IOL, asmstr, itin> {
144 let Pattern = pattern;
147 let Inst{11-15} = Addr{20-16}; // Base Reg
148 let Inst{16-31} = Addr{15-0}; // Displacement
151 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
152 InstrItinClass itin, list<dag> pattern>
153 : I<opcode, OOL, IOL, asmstr, itin> {
158 let Pattern = pattern;
166 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
167 InstrItinClass itin, list<dag> pattern>
168 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>;
170 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
171 InstrItinClass itin, list<dag> pattern>
172 : I<opcode, OOL, IOL, asmstr, itin> {
176 let Pattern = pattern;
183 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
184 InstrItinClass itin, list<dag> pattern>
185 : I<opcode, OOL, IOL, asmstr, itin> {
190 let Pattern = pattern;
197 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
198 InstrItinClass itin, list<dag> pattern>
199 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
204 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
205 dag OOL, dag IOL, string asmstr,
206 InstrItinClass itin, list<dag> pattern>
207 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
211 let Pattern = pattern;
219 let Inst{43-47} = Addr{20-16}; // Base Reg
220 let Inst{48-63} = Addr{15-0}; // Displacement
223 // This is used to emit BL8+NOP.
224 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
225 dag OOL, dag IOL, string asmstr,
226 InstrItinClass itin, list<dag> pattern>
227 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
228 OOL, IOL, asmstr, itin, pattern> {
233 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
235 : I<opcode, OOL, IOL, asmstr, itin> {
244 let Inst{11-15} = RA;
248 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
250 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
254 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
256 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
258 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
260 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
266 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
267 InstrItinClass itin, list<dag> pattern>
268 : I<opcode, OOL, IOL, asmstr, itin> {
272 let Pattern = pattern;
274 let Inst{6-10} = RST;
275 let Inst{11-15} = DS_RA{18-14}; // Register #
276 let Inst{16-29} = DS_RA{13-0}; // Displacement.
277 let Inst{30-31} = xo;
280 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
281 InstrItinClass itin, list<dag> pattern>
282 : I<opcode, OOL, IOL, asmstr, itin> {
287 let Pattern = pattern;
289 let Inst{6-10} = RST;
290 let Inst{11-15} = RA;
291 let Inst{16-29} = DS;
292 let Inst{30-31} = xo;
296 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
297 InstrItinClass itin, list<dag> pattern>
298 : I<opcode, OOL, IOL, asmstr, itin> {
303 let Pattern = pattern;
305 bit RC = 0; // set by isDOT
307 let Inst{6-10} = RST;
310 let Inst{21-30} = xo;
314 // This is the same as XForm_base_r3xo, but the first two operands are swapped
315 // when code is emitted.
316 class XForm_base_r3xo_swapped
317 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
319 : I<opcode, OOL, IOL, asmstr, itin> {
324 bit RC = 0; // set by isDOT
326 let Inst{6-10} = RST;
329 let Inst{21-30} = xo;
334 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
335 InstrItinClass itin, list<dag> pattern>
336 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
338 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
339 InstrItinClass itin, list<dag> pattern>
340 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
341 let Pattern = pattern;
344 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
345 InstrItinClass itin, list<dag> pattern>
346 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
348 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
349 InstrItinClass itin, list<dag> pattern>
350 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
351 let Pattern = pattern;
354 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
355 InstrItinClass itin, list<dag> pattern>
356 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
358 let Pattern = pattern;
361 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
363 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Inst{11-15} = RA;
373 let Inst{16-20} = RB;
374 let Inst{21-30} = xo;
378 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
380 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
384 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
386 : I<opcode, OOL, IOL, asmstr, itin> {
393 let Inst{11-15} = FRA;
394 let Inst{16-20} = FRB;
395 let Inst{21-30} = xo;
399 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
400 InstrItinClass itin, list<dag> pattern>
401 : I<opcode, OOL, IOL, asmstr, itin> {
402 let Pattern = pattern;
406 let Inst{21-30} = xo;
410 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
411 string asmstr, InstrItinClass itin, list<dag> pattern>
412 : I<opcode, OOL, IOL, asmstr, itin> {
413 let Pattern = pattern;
417 let Inst{21-30} = xo;
421 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
422 InstrItinClass itin, list<dag> pattern>
423 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
426 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
427 InstrItinClass itin, list<dag> pattern>
428 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
432 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
433 InstrItinClass itin, list<dag> pattern>
434 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
437 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
438 // numbers presumably relates to some document, but I haven't found it.
439 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
440 InstrItinClass itin, list<dag> pattern>
441 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
442 let Pattern = pattern;
444 bit RC = 0; // set by isDOT
446 let Inst{6-10} = RST;
448 let Inst{21-30} = xo;
451 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
452 InstrItinClass itin, list<dag> pattern>
453 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
454 let Pattern = pattern;
457 bit RC = 0; // set by isDOT
461 let Inst{21-30} = xo;
465 // DCB_Form - Form X instruction, used for dcb* instructions.
466 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
467 InstrItinClass itin, list<dag> pattern>
468 : I<31, OOL, IOL, asmstr, itin> {
472 let Pattern = pattern;
474 let Inst{6-10} = immfield;
477 let Inst{21-30} = xo;
482 // DSS_Form - Form X instruction, used for altivec dss* instructions.
483 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
484 InstrItinClass itin, list<dag> pattern>
485 : I<31, OOL, IOL, asmstr, itin> {
491 let Pattern = pattern;
495 let Inst{9-10} = STRM;
498 let Inst{21-30} = xo;
503 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
504 InstrItinClass itin, list<dag> pattern>
505 : I<opcode, OOL, IOL, asmstr, itin> {
510 let Pattern = pattern;
512 let Inst{6-10} = CRD;
513 let Inst{11-15} = CRA;
514 let Inst{16-20} = CRB;
515 let Inst{21-30} = xo;
519 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
520 InstrItinClass itin, list<dag> pattern>
521 : I<opcode, OOL, IOL, asmstr, itin> {
524 let Pattern = pattern;
526 let Inst{6-10} = CRD;
527 let Inst{11-15} = CRD;
528 let Inst{16-20} = CRD;
529 let Inst{21-30} = xo;
533 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
534 InstrItinClass itin, list<dag> pattern>
535 : I<opcode, OOL, IOL, asmstr, itin> {
540 let Pattern = pattern;
543 let Inst{11-15} = BI;
545 let Inst{19-20} = BH;
546 let Inst{21-30} = xo;
550 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
551 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
552 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
553 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
557 let BI{0-1} = BIBO{0-1};
563 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
564 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
565 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
571 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
573 : I<opcode, OOL, IOL, asmstr, itin> {
579 let Inst{11-13} = BFA;
582 let Inst{21-30} = xo;
587 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
589 : I<opcode, OOL, IOL, asmstr, itin> {
594 let Inst{11} = SPR{4};
595 let Inst{12} = SPR{3};
596 let Inst{13} = SPR{2};
597 let Inst{14} = SPR{1};
598 let Inst{15} = SPR{0};
599 let Inst{16} = SPR{9};
600 let Inst{17} = SPR{8};
601 let Inst{18} = SPR{7};
602 let Inst{19} = SPR{6};
603 let Inst{20} = SPR{5};
604 let Inst{21-30} = xo;
608 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
609 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
610 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
614 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
616 : I<opcode, OOL, IOL, asmstr, itin> {
621 let Inst{21-30} = xo;
625 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
627 : I<opcode, OOL, IOL, asmstr, itin> {
633 let Inst{12-19} = FXM;
635 let Inst{21-30} = xo;
639 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
641 : I<opcode, OOL, IOL, asmstr, itin> {
647 let Inst{12-19} = FXM;
649 let Inst{21-30} = xo;
653 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
655 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
657 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
658 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
659 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
664 // This is probably 1.7.9, but I don't have the reference that uses this
665 // numbering scheme...
666 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
667 string cstr, InstrItinClass itin, list<dag>pattern>
668 : I<opcode, OOL, IOL, asmstr, itin> {
672 bit RC = 0; // set by isDOT
673 let Pattern = pattern;
674 let Constraints = cstr;
679 let Inst{16-20} = rT;
680 let Inst{21-30} = xo;
684 // 1.7.10 XS-Form - SRADI.
685 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
686 InstrItinClass itin, list<dag> pattern>
687 : I<opcode, OOL, IOL, asmstr, itin> {
692 bit RC = 0; // set by isDOT
693 let Pattern = pattern;
697 let Inst{16-20} = SH{4,3,2,1,0};
698 let Inst{21-29} = xo;
699 let Inst{30} = SH{5};
704 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
705 InstrItinClass itin, list<dag> pattern>
706 : I<opcode, OOL, IOL, asmstr, itin> {
711 let Pattern = pattern;
713 bit RC = 0; // set by isDOT
716 let Inst{11-15} = RA;
717 let Inst{16-20} = RB;
719 let Inst{22-30} = xo;
723 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
724 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
725 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
730 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
731 InstrItinClass itin, list<dag> pattern>
732 : I<opcode, OOL, IOL, asmstr, itin> {
738 let Pattern = pattern;
740 bit RC = 0; // set by isDOT
742 let Inst{6-10} = FRT;
743 let Inst{11-15} = FRA;
744 let Inst{16-20} = FRB;
745 let Inst{21-25} = FRC;
746 let Inst{26-30} = xo;
750 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
751 InstrItinClass itin, list<dag> pattern>
752 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
756 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
757 InstrItinClass itin, list<dag> pattern>
758 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
762 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
763 InstrItinClass itin, list<dag> pattern>
764 : I<opcode, OOL, IOL, asmstr, itin> {
768 bits<7> BIBO; // 2 bits of BI and 5 bits of BO (must be 12).
771 let Pattern = pattern;
774 let Inst{11-15} = RA;
775 let Inst{16-20} = RB;
776 let Inst{21-23} = CR;
777 let Inst{24-25} = BIBO{6-5};
778 let Inst{26-30} = xo;
783 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
784 InstrItinClass itin, list<dag> pattern>
785 : I<opcode, OOL, IOL, asmstr, itin> {
792 let Pattern = pattern;
794 bit RC = 0; // set by isDOT
797 let Inst{11-15} = RA;
798 let Inst{16-20} = RB;
799 let Inst{21-25} = MB;
800 let Inst{26-30} = ME;
804 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
805 InstrItinClass itin, list<dag> pattern>
806 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
810 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
811 InstrItinClass itin, list<dag> pattern>
812 : I<opcode, OOL, IOL, asmstr, itin> {
818 let Pattern = pattern;
820 bit RC = 0; // set by isDOT
823 let Inst{11-15} = RA;
824 let Inst{16-20} = SH{4,3,2,1,0};
825 let Inst{21-26} = MBE{4,3,2,1,0,5};
826 let Inst{27-29} = xo;
827 let Inst{30} = SH{5};
835 // VAForm_1 - DACB ordering.
836 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
837 InstrItinClass itin, list<dag> pattern>
838 : I<4, OOL, IOL, asmstr, itin> {
844 let Pattern = pattern;
847 let Inst{11-15} = VA;
848 let Inst{16-20} = VB;
849 let Inst{21-25} = VC;
850 let Inst{26-31} = xo;
853 // VAForm_1a - DABC ordering.
854 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
855 InstrItinClass itin, list<dag> pattern>
856 : I<4, OOL, IOL, asmstr, itin> {
862 let Pattern = pattern;
865 let Inst{11-15} = VA;
866 let Inst{16-20} = VB;
867 let Inst{21-25} = VC;
868 let Inst{26-31} = xo;
871 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
872 InstrItinClass itin, list<dag> pattern>
873 : I<4, OOL, IOL, asmstr, itin> {
879 let Pattern = pattern;
882 let Inst{11-15} = VA;
883 let Inst{16-20} = VB;
885 let Inst{22-25} = SH;
886 let Inst{26-31} = xo;
890 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
891 InstrItinClass itin, list<dag> pattern>
892 : I<4, OOL, IOL, asmstr, itin> {
897 let Pattern = pattern;
900 let Inst{11-15} = VA;
901 let Inst{16-20} = VB;
902 let Inst{21-31} = xo;
905 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
906 InstrItinClass itin, list<dag> pattern>
907 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
913 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
914 InstrItinClass itin, list<dag> pattern>
915 : I<4, OOL, IOL, asmstr, itin> {
919 let Pattern = pattern;
923 let Inst{16-20} = VB;
924 let Inst{21-31} = xo;
927 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
928 InstrItinClass itin, list<dag> pattern>
929 : I<4, OOL, IOL, asmstr, itin> {
933 let Pattern = pattern;
936 let Inst{11-15} = IMM;
938 let Inst{21-31} = xo;
941 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
942 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
943 InstrItinClass itin, list<dag> pattern>
944 : I<4, OOL, IOL, asmstr, itin> {
947 let Pattern = pattern;
952 let Inst{21-31} = xo;
955 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
956 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
957 InstrItinClass itin, list<dag> pattern>
958 : I<4, OOL, IOL, asmstr, itin> {
961 let Pattern = pattern;
965 let Inst{16-20} = VB;
966 let Inst{21-31} = xo;
970 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
971 InstrItinClass itin, list<dag> pattern>
972 : I<4, OOL, IOL, asmstr, itin> {
978 let Pattern = pattern;
981 let Inst{11-15} = VA;
982 let Inst{16-20} = VB;
984 let Inst{22-31} = xo;
987 //===----------------------------------------------------------------------===//
988 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
989 : I<0, OOL, IOL, asmstr, NoItinerary> {
991 let Pattern = pattern;