1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 // This is the same as XForm_base_r3xo, but the first two operands are swapped
384 // when code is emitted.
385 class XForm_base_r3xo_swapped
386 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
388 : I<opcode, OOL, IOL, asmstr, itin> {
393 bit RC = 0; // set by isDOT
395 let Inst{6-10} = RST;
398 let Inst{21-30} = xo;
403 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
404 InstrItinClass itin, list<dag> pattern>
405 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
407 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
408 InstrItinClass itin, list<dag> pattern>
409 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
413 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
414 InstrItinClass itin, list<dag> pattern>
415 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
420 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
421 InstrItinClass itin, list<dag> pattern>
422 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
423 let Pattern = pattern;
426 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
427 InstrItinClass itin, list<dag> pattern>
428 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
430 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
431 InstrItinClass itin, list<dag> pattern>
432 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
433 let Pattern = pattern;
436 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
437 InstrItinClass itin, list<dag> pattern>
438 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
440 let Pattern = pattern;
443 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
445 : I<opcode, OOL, IOL, asmstr, itin> {
454 let Inst{11-15} = RA;
455 let Inst{16-20} = RB;
456 let Inst{21-30} = xo;
460 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
462 : I<opcode, OOL, IOL, asmstr, itin> {
467 let Inst{12-15} = SR;
468 let Inst{21-30} = xo;
471 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
473 : I<opcode, OOL, IOL, asmstr, itin> {
478 let Inst{16-20} = RB;
479 let Inst{21-30} = xo;
482 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
484 : I<opcode, OOL, IOL, asmstr, itin> {
490 let Inst{21-30} = xo;
493 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
495 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
499 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
501 : I<opcode, OOL, IOL, asmstr, itin> {
508 let Inst{11-15} = FRA;
509 let Inst{16-20} = FRB;
510 let Inst{21-30} = xo;
514 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
515 InstrItinClass itin, list<dag> pattern>
516 : I<opcode, OOL, IOL, asmstr, itin> {
517 let Pattern = pattern;
521 let Inst{21-30} = xo;
525 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
526 string asmstr, InstrItinClass itin, list<dag> pattern>
527 : I<opcode, OOL, IOL, asmstr, itin> {
530 let Pattern = pattern;
535 let Inst{21-30} = xo;
539 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
540 string asmstr, InstrItinClass itin, list<dag> pattern>
541 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
545 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
546 InstrItinClass itin, list<dag> pattern>
547 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
550 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
551 InstrItinClass itin, list<dag> pattern>
552 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
556 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
557 InstrItinClass itin, list<dag> pattern>
558 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
561 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
562 // numbers presumably relates to some document, but I haven't found it.
563 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
564 InstrItinClass itin, list<dag> pattern>
565 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
566 let Pattern = pattern;
568 bit RC = 0; // set by isDOT
570 let Inst{6-10} = RST;
572 let Inst{21-30} = xo;
575 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
576 InstrItinClass itin, list<dag> pattern>
577 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
578 let Pattern = pattern;
581 bit RC = 0; // set by isDOT
585 let Inst{21-30} = xo;
589 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
590 InstrItinClass itin, list<dag> pattern>
591 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
597 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
598 InstrItinClass itin, list<dag> pattern>
599 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
605 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
606 InstrItinClass itin, list<dag> pattern>
607 : I<opcode, OOL, IOL, asmstr, itin> {
612 let Pattern = pattern;
614 let Inst{6-10} = XT{4-0};
617 let Inst{21-30} = xo;
618 let Inst{31} = XT{5};
621 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
622 InstrItinClass itin, list<dag> pattern>
623 : I<opcode, OOL, IOL, asmstr, itin> {
627 let Pattern = pattern;
629 let Inst{6-10} = XT{4-0};
631 let Inst{16-20} = XB{4-0};
632 let Inst{21-29} = xo;
633 let Inst{30} = XB{5};
634 let Inst{31} = XT{5};
637 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
638 InstrItinClass itin, list<dag> pattern>
639 : I<opcode, OOL, IOL, asmstr, itin> {
643 let Pattern = pattern;
647 let Inst{16-20} = XB{4-0};
648 let Inst{21-29} = xo;
649 let Inst{30} = XB{5};
653 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
654 InstrItinClass itin, list<dag> pattern>
655 : I<opcode, OOL, IOL, asmstr, itin> {
660 let Pattern = pattern;
662 let Inst{6-10} = XT{4-0};
665 let Inst{16-20} = XB{4-0};
666 let Inst{21-29} = xo;
667 let Inst{30} = XB{5};
668 let Inst{31} = XT{5};
671 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
672 InstrItinClass itin, list<dag> pattern>
673 : I<opcode, OOL, IOL, asmstr, itin> {
678 let Pattern = pattern;
680 let Inst{6-10} = XT{4-0};
681 let Inst{11-15} = XA{4-0};
682 let Inst{16-20} = XB{4-0};
683 let Inst{21-28} = xo;
684 let Inst{29} = XA{5};
685 let Inst{30} = XB{5};
686 let Inst{31} = XT{5};
689 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
690 InstrItinClass itin, list<dag> pattern>
691 : I<opcode, OOL, IOL, asmstr, itin> {
696 let Pattern = pattern;
700 let Inst{11-15} = XA{4-0};
701 let Inst{16-20} = XB{4-0};
702 let Inst{21-28} = xo;
703 let Inst{29} = XA{5};
704 let Inst{30} = XB{5};
708 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
709 InstrItinClass itin, list<dag> pattern>
710 : I<opcode, OOL, IOL, asmstr, itin> {
716 let Pattern = pattern;
718 let Inst{6-10} = XT{4-0};
719 let Inst{11-15} = XA{4-0};
720 let Inst{16-20} = XB{4-0};
723 let Inst{24-28} = xo;
724 let Inst{29} = XA{5};
725 let Inst{30} = XB{5};
726 let Inst{31} = XT{5};
729 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
730 InstrItinClass itin, list<dag> pattern>
731 : I<opcode, OOL, IOL, asmstr, itin> {
736 let Pattern = pattern;
738 bit RC = 0; // set by isDOT
740 let Inst{6-10} = XT{4-0};
741 let Inst{11-15} = XA{4-0};
742 let Inst{16-20} = XB{4-0};
744 let Inst{22-28} = xo;
745 let Inst{29} = XA{5};
746 let Inst{30} = XB{5};
747 let Inst{31} = XT{5};
750 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
751 InstrItinClass itin, list<dag> pattern>
752 : I<opcode, OOL, IOL, asmstr, itin> {
758 let Pattern = pattern;
760 let Inst{6-10} = XT{4-0};
761 let Inst{11-15} = XA{4-0};
762 let Inst{16-20} = XB{4-0};
763 let Inst{21-25} = XC{4-0};
764 let Inst{26-27} = xo;
765 let Inst{28} = XC{5};
766 let Inst{29} = XA{5};
767 let Inst{30} = XB{5};
768 let Inst{31} = XT{5};
771 // DCB_Form - Form X instruction, used for dcb* instructions.
772 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
773 InstrItinClass itin, list<dag> pattern>
774 : I<31, OOL, IOL, asmstr, itin> {
778 let Pattern = pattern;
780 let Inst{6-10} = immfield;
783 let Inst{21-30} = xo;
788 // DSS_Form - Form X instruction, used for altivec dss* instructions.
789 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
790 InstrItinClass itin, list<dag> pattern>
791 : I<31, OOL, IOL, asmstr, itin> {
797 let Pattern = pattern;
801 let Inst{9-10} = STRM;
804 let Inst{21-30} = xo;
809 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
810 InstrItinClass itin, list<dag> pattern>
811 : I<opcode, OOL, IOL, asmstr, itin> {
816 let Pattern = pattern;
818 let Inst{6-10} = CRD;
819 let Inst{11-15} = CRA;
820 let Inst{16-20} = CRB;
821 let Inst{21-30} = xo;
825 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
826 InstrItinClass itin, list<dag> pattern>
827 : I<opcode, OOL, IOL, asmstr, itin> {
830 let Pattern = pattern;
832 let Inst{6-10} = CRD;
833 let Inst{11-15} = CRD;
834 let Inst{16-20} = CRD;
835 let Inst{21-30} = xo;
839 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
840 InstrItinClass itin, list<dag> pattern>
841 : I<opcode, OOL, IOL, asmstr, itin> {
846 let Pattern = pattern;
849 let Inst{11-15} = BI;
851 let Inst{19-20} = BH;
852 let Inst{21-30} = xo;
856 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
857 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
858 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
859 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
863 let BI{0-1} = BIBO{5-6};
864 let BI{2-4} = CR{0-2};
868 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
869 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
870 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
875 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
876 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
877 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
883 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
885 : I<opcode, OOL, IOL, asmstr, itin> {
891 let Inst{11-13} = BFA;
894 let Inst{21-30} = xo;
899 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
901 : I<opcode, OOL, IOL, asmstr, itin> {
906 let Inst{11} = SPR{4};
907 let Inst{12} = SPR{3};
908 let Inst{13} = SPR{2};
909 let Inst{14} = SPR{1};
910 let Inst{15} = SPR{0};
911 let Inst{16} = SPR{9};
912 let Inst{17} = SPR{8};
913 let Inst{18} = SPR{7};
914 let Inst{19} = SPR{6};
915 let Inst{20} = SPR{5};
916 let Inst{21-30} = xo;
920 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
921 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
922 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
926 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
928 : I<opcode, OOL, IOL, asmstr, itin> {
933 let Inst{21-30} = xo;
937 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
939 : I<opcode, OOL, IOL, asmstr, itin> {
945 let Inst{12-19} = FXM;
947 let Inst{21-30} = xo;
951 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
953 : I<opcode, OOL, IOL, asmstr, itin> {
959 let Inst{12-19} = FXM;
961 let Inst{21-30} = xo;
965 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
967 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
969 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
970 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
971 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
976 // This is probably 1.7.9, but I don't have the reference that uses this
977 // numbering scheme...
978 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
979 InstrItinClass itin, list<dag>pattern>
980 : I<opcode, OOL, IOL, asmstr, itin> {
984 bit RC = 0; // set by isDOT
985 let Pattern = pattern;
990 let Inst{16-20} = rT;
991 let Inst{21-30} = xo;
995 // 1.7.10 XS-Form - SRADI.
996 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
997 InstrItinClass itin, list<dag> pattern>
998 : I<opcode, OOL, IOL, asmstr, itin> {
1003 bit RC = 0; // set by isDOT
1004 let Pattern = pattern;
1006 let Inst{6-10} = RS;
1007 let Inst{11-15} = A;
1008 let Inst{16-20} = SH{4,3,2,1,0};
1009 let Inst{21-29} = xo;
1010 let Inst{30} = SH{5};
1015 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1016 InstrItinClass itin, list<dag> pattern>
1017 : I<opcode, OOL, IOL, asmstr, itin> {
1022 let Pattern = pattern;
1024 bit RC = 0; // set by isDOT
1026 let Inst{6-10} = RT;
1027 let Inst{11-15} = RA;
1028 let Inst{16-20} = RB;
1030 let Inst{22-30} = xo;
1034 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1035 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1036 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1041 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1042 InstrItinClass itin, list<dag> pattern>
1043 : I<opcode, OOL, IOL, asmstr, itin> {
1049 let Pattern = pattern;
1051 bit RC = 0; // set by isDOT
1053 let Inst{6-10} = FRT;
1054 let Inst{11-15} = FRA;
1055 let Inst{16-20} = FRB;
1056 let Inst{21-25} = FRC;
1057 let Inst{26-30} = xo;
1061 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1062 InstrItinClass itin, list<dag> pattern>
1063 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1067 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1068 InstrItinClass itin, list<dag> pattern>
1069 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1073 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1074 InstrItinClass itin, list<dag> pattern>
1075 : I<opcode, OOL, IOL, asmstr, itin> {
1081 let Pattern = pattern;
1083 let Inst{6-10} = RT;
1084 let Inst{11-15} = RA;
1085 let Inst{16-20} = RB;
1086 let Inst{21-25} = COND;
1087 let Inst{26-30} = xo;
1092 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1093 InstrItinClass itin, list<dag> pattern>
1094 : I<opcode, OOL, IOL, asmstr, itin> {
1101 let Pattern = pattern;
1103 bit RC = 0; // set by isDOT
1105 let Inst{6-10} = RS;
1106 let Inst{11-15} = RA;
1107 let Inst{16-20} = RB;
1108 let Inst{21-25} = MB;
1109 let Inst{26-30} = ME;
1113 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1114 InstrItinClass itin, list<dag> pattern>
1115 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1119 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1120 InstrItinClass itin, list<dag> pattern>
1121 : I<opcode, OOL, IOL, asmstr, itin> {
1127 let Pattern = pattern;
1129 bit RC = 0; // set by isDOT
1131 let Inst{6-10} = RS;
1132 let Inst{11-15} = RA;
1133 let Inst{16-20} = SH{4,3,2,1,0};
1134 let Inst{21-26} = MBE{4,3,2,1,0,5};
1135 let Inst{27-29} = xo;
1136 let Inst{30} = SH{5};
1140 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1141 InstrItinClass itin, list<dag> pattern>
1142 : I<opcode, OOL, IOL, asmstr, itin> {
1148 let Pattern = pattern;
1150 bit RC = 0; // set by isDOT
1152 let Inst{6-10} = RS;
1153 let Inst{11-15} = RA;
1154 let Inst{16-20} = RB;
1155 let Inst{21-26} = MBE{4,3,2,1,0,5};
1156 let Inst{27-30} = xo;
1163 // VAForm_1 - DACB ordering.
1164 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1165 InstrItinClass itin, list<dag> pattern>
1166 : I<4, OOL, IOL, asmstr, itin> {
1172 let Pattern = pattern;
1174 let Inst{6-10} = VD;
1175 let Inst{11-15} = VA;
1176 let Inst{16-20} = VB;
1177 let Inst{21-25} = VC;
1178 let Inst{26-31} = xo;
1181 // VAForm_1a - DABC ordering.
1182 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1183 InstrItinClass itin, list<dag> pattern>
1184 : I<4, OOL, IOL, asmstr, itin> {
1190 let Pattern = pattern;
1192 let Inst{6-10} = VD;
1193 let Inst{11-15} = VA;
1194 let Inst{16-20} = VB;
1195 let Inst{21-25} = VC;
1196 let Inst{26-31} = xo;
1199 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1200 InstrItinClass itin, list<dag> pattern>
1201 : I<4, OOL, IOL, asmstr, itin> {
1207 let Pattern = pattern;
1209 let Inst{6-10} = VD;
1210 let Inst{11-15} = VA;
1211 let Inst{16-20} = VB;
1213 let Inst{22-25} = SH;
1214 let Inst{26-31} = xo;
1218 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1219 InstrItinClass itin, list<dag> pattern>
1220 : I<4, OOL, IOL, asmstr, itin> {
1225 let Pattern = pattern;
1227 let Inst{6-10} = VD;
1228 let Inst{11-15} = VA;
1229 let Inst{16-20} = VB;
1230 let Inst{21-31} = xo;
1233 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1234 InstrItinClass itin, list<dag> pattern>
1235 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1241 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1242 InstrItinClass itin, list<dag> pattern>
1243 : I<4, OOL, IOL, asmstr, itin> {
1247 let Pattern = pattern;
1249 let Inst{6-10} = VD;
1250 let Inst{11-15} = 0;
1251 let Inst{16-20} = VB;
1252 let Inst{21-31} = xo;
1255 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1256 InstrItinClass itin, list<dag> pattern>
1257 : I<4, OOL, IOL, asmstr, itin> {
1261 let Pattern = pattern;
1263 let Inst{6-10} = VD;
1264 let Inst{11-15} = IMM;
1265 let Inst{16-20} = 0;
1266 let Inst{21-31} = xo;
1269 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1270 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1271 InstrItinClass itin, list<dag> pattern>
1272 : I<4, OOL, IOL, asmstr, itin> {
1275 let Pattern = pattern;
1277 let Inst{6-10} = VD;
1278 let Inst{11-15} = 0;
1279 let Inst{16-20} = 0;
1280 let Inst{21-31} = xo;
1283 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1284 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1285 InstrItinClass itin, list<dag> pattern>
1286 : I<4, OOL, IOL, asmstr, itin> {
1289 let Pattern = pattern;
1292 let Inst{11-15} = 0;
1293 let Inst{16-20} = VB;
1294 let Inst{21-31} = xo;
1298 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1299 InstrItinClass itin, list<dag> pattern>
1300 : I<4, OOL, IOL, asmstr, itin> {
1306 let Pattern = pattern;
1308 let Inst{6-10} = VD;
1309 let Inst{11-15} = VA;
1310 let Inst{16-20} = VB;
1312 let Inst{22-31} = xo;
1315 //===----------------------------------------------------------------------===//
1316 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1317 : I<0, OOL, IOL, asmstr, NoItinerary> {
1318 let isCodeGenOnly = 1;
1320 let Pattern = pattern;