1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 // This is the same as XForm_base_r3xo, but the first two operands are swapped
384 // when code is emitted.
385 class XForm_base_r3xo_swapped
386 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
388 : I<opcode, OOL, IOL, asmstr, itin> {
393 bit RC = 0; // set by isDOT
395 let Inst{6-10} = RST;
398 let Inst{21-30} = xo;
403 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
404 InstrItinClass itin, list<dag> pattern>
405 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
407 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
408 InstrItinClass itin, list<dag> pattern>
409 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
413 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
414 InstrItinClass itin, list<dag> pattern>
415 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
420 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
421 InstrItinClass itin, list<dag> pattern>
422 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
423 let Pattern = pattern;
426 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
427 InstrItinClass itin, list<dag> pattern>
428 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
430 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
431 InstrItinClass itin, list<dag> pattern>
432 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
433 let Pattern = pattern;
436 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
437 InstrItinClass itin, list<dag> pattern>
438 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
440 let Pattern = pattern;
443 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
445 : I<opcode, OOL, IOL, asmstr, itin> {
454 let Inst{11-15} = RA;
455 let Inst{16-20} = RB;
456 let Inst{21-30} = xo;
460 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
462 : I<opcode, OOL, IOL, asmstr, itin> {
467 let Inst{12-15} = SR;
468 let Inst{21-30} = xo;
471 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
473 : I<opcode, OOL, IOL, asmstr, itin> {
477 let Inst{21-30} = xo;
480 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
482 : I<opcode, OOL, IOL, asmstr, itin> {
487 let Inst{16-20} = RB;
488 let Inst{21-30} = xo;
491 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
493 : I<opcode, OOL, IOL, asmstr, itin> {
499 let Inst{21-30} = xo;
502 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
504 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
508 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
510 : I<opcode, OOL, IOL, asmstr, itin> {
517 let Inst{11-15} = FRA;
518 let Inst{16-20} = FRB;
519 let Inst{21-30} = xo;
523 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
524 InstrItinClass itin, list<dag> pattern>
525 : I<opcode, OOL, IOL, asmstr, itin> {
526 let Pattern = pattern;
530 let Inst{21-30} = xo;
534 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
535 string asmstr, InstrItinClass itin, list<dag> pattern>
536 : I<opcode, OOL, IOL, asmstr, itin> {
539 let Pattern = pattern;
544 let Inst{21-30} = xo;
548 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
549 string asmstr, InstrItinClass itin, list<dag> pattern>
550 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
554 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
555 InstrItinClass itin, list<dag> pattern>
556 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
559 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
560 InstrItinClass itin, list<dag> pattern>
561 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
565 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
566 InstrItinClass itin, list<dag> pattern>
567 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
570 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
571 // numbers presumably relates to some document, but I haven't found it.
572 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
573 InstrItinClass itin, list<dag> pattern>
574 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
575 let Pattern = pattern;
577 bit RC = 0; // set by isDOT
579 let Inst{6-10} = RST;
581 let Inst{21-30} = xo;
584 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
585 InstrItinClass itin, list<dag> pattern>
586 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
587 let Pattern = pattern;
590 bit RC = 0; // set by isDOT
594 let Inst{21-30} = xo;
598 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
599 InstrItinClass itin, list<dag> pattern>
600 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
606 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
607 InstrItinClass itin, list<dag> pattern>
608 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
614 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
615 InstrItinClass itin, list<dag> pattern>
616 : I<opcode, OOL, IOL, asmstr, itin> {
621 let Pattern = pattern;
623 let Inst{6-10} = XT{4-0};
626 let Inst{21-30} = xo;
627 let Inst{31} = XT{5};
630 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
631 InstrItinClass itin, list<dag> pattern>
632 : I<opcode, OOL, IOL, asmstr, itin> {
636 let Pattern = pattern;
638 let Inst{6-10} = XT{4-0};
640 let Inst{16-20} = XB{4-0};
641 let Inst{21-29} = xo;
642 let Inst{30} = XB{5};
643 let Inst{31} = XT{5};
646 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
647 InstrItinClass itin, list<dag> pattern>
648 : I<opcode, OOL, IOL, asmstr, itin> {
652 let Pattern = pattern;
656 let Inst{16-20} = XB{4-0};
657 let Inst{21-29} = xo;
658 let Inst{30} = XB{5};
662 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
663 InstrItinClass itin, list<dag> pattern>
664 : I<opcode, OOL, IOL, asmstr, itin> {
669 let Pattern = pattern;
671 let Inst{6-10} = XT{4-0};
674 let Inst{16-20} = XB{4-0};
675 let Inst{21-29} = xo;
676 let Inst{30} = XB{5};
677 let Inst{31} = XT{5};
680 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
681 InstrItinClass itin, list<dag> pattern>
682 : I<opcode, OOL, IOL, asmstr, itin> {
687 let Pattern = pattern;
689 let Inst{6-10} = XT{4-0};
690 let Inst{11-15} = XA{4-0};
691 let Inst{16-20} = XB{4-0};
692 let Inst{21-28} = xo;
693 let Inst{29} = XA{5};
694 let Inst{30} = XB{5};
695 let Inst{31} = XT{5};
698 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
699 InstrItinClass itin, list<dag> pattern>
700 : I<opcode, OOL, IOL, asmstr, itin> {
705 let Pattern = pattern;
709 let Inst{11-15} = XA{4-0};
710 let Inst{16-20} = XB{4-0};
711 let Inst{21-28} = xo;
712 let Inst{29} = XA{5};
713 let Inst{30} = XB{5};
717 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
718 InstrItinClass itin, list<dag> pattern>
719 : I<opcode, OOL, IOL, asmstr, itin> {
725 let Pattern = pattern;
727 let Inst{6-10} = XT{4-0};
728 let Inst{11-15} = XA{4-0};
729 let Inst{16-20} = XB{4-0};
732 let Inst{24-28} = xo;
733 let Inst{29} = XA{5};
734 let Inst{30} = XB{5};
735 let Inst{31} = XT{5};
738 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
739 InstrItinClass itin, list<dag> pattern>
740 : I<opcode, OOL, IOL, asmstr, itin> {
745 let Pattern = pattern;
747 bit RC = 0; // set by isDOT
749 let Inst{6-10} = XT{4-0};
750 let Inst{11-15} = XA{4-0};
751 let Inst{16-20} = XB{4-0};
753 let Inst{22-28} = xo;
754 let Inst{29} = XA{5};
755 let Inst{30} = XB{5};
756 let Inst{31} = XT{5};
759 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
760 InstrItinClass itin, list<dag> pattern>
761 : I<opcode, OOL, IOL, asmstr, itin> {
767 let Pattern = pattern;
769 let Inst{6-10} = XT{4-0};
770 let Inst{11-15} = XA{4-0};
771 let Inst{16-20} = XB{4-0};
772 let Inst{21-25} = XC{4-0};
773 let Inst{26-27} = xo;
774 let Inst{28} = XC{5};
775 let Inst{29} = XA{5};
776 let Inst{30} = XB{5};
777 let Inst{31} = XT{5};
780 // DCB_Form - Form X instruction, used for dcb* instructions.
781 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
782 InstrItinClass itin, list<dag> pattern>
783 : I<31, OOL, IOL, asmstr, itin> {
787 let Pattern = pattern;
789 let Inst{6-10} = immfield;
792 let Inst{21-30} = xo;
797 // DSS_Form - Form X instruction, used for altivec dss* instructions.
798 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
799 InstrItinClass itin, list<dag> pattern>
800 : I<31, OOL, IOL, asmstr, itin> {
806 let Pattern = pattern;
810 let Inst{9-10} = STRM;
813 let Inst{21-30} = xo;
818 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
819 InstrItinClass itin, list<dag> pattern>
820 : I<opcode, OOL, IOL, asmstr, itin> {
825 let Pattern = pattern;
827 let Inst{6-10} = CRD;
828 let Inst{11-15} = CRA;
829 let Inst{16-20} = CRB;
830 let Inst{21-30} = xo;
834 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
835 InstrItinClass itin, list<dag> pattern>
836 : I<opcode, OOL, IOL, asmstr, itin> {
839 let Pattern = pattern;
841 let Inst{6-10} = CRD;
842 let Inst{11-15} = CRD;
843 let Inst{16-20} = CRD;
844 let Inst{21-30} = xo;
848 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
849 InstrItinClass itin, list<dag> pattern>
850 : I<opcode, OOL, IOL, asmstr, itin> {
855 let Pattern = pattern;
858 let Inst{11-15} = BI;
860 let Inst{19-20} = BH;
861 let Inst{21-30} = xo;
865 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
866 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
867 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
868 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
872 let BI{0-1} = BIBO{5-6};
873 let BI{2-4} = CR{0-2};
877 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
878 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
879 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
884 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
885 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
886 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
892 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
894 : I<opcode, OOL, IOL, asmstr, itin> {
900 let Inst{11-13} = BFA;
903 let Inst{21-30} = xo;
908 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
910 : I<opcode, OOL, IOL, asmstr, itin> {
915 let Inst{11} = SPR{4};
916 let Inst{12} = SPR{3};
917 let Inst{13} = SPR{2};
918 let Inst{14} = SPR{1};
919 let Inst{15} = SPR{0};
920 let Inst{16} = SPR{9};
921 let Inst{17} = SPR{8};
922 let Inst{18} = SPR{7};
923 let Inst{19} = SPR{6};
924 let Inst{20} = SPR{5};
925 let Inst{21-30} = xo;
929 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
930 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
931 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
935 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
937 : I<opcode, OOL, IOL, asmstr, itin> {
942 let Inst{21-30} = xo;
946 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
948 : I<opcode, OOL, IOL, asmstr, itin> {
954 let Inst{12-19} = FXM;
956 let Inst{21-30} = xo;
960 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
962 : I<opcode, OOL, IOL, asmstr, itin> {
968 let Inst{12-19} = FXM;
970 let Inst{21-30} = xo;
974 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
976 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
978 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
979 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
980 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
985 // This is probably 1.7.9, but I don't have the reference that uses this
986 // numbering scheme...
987 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
988 InstrItinClass itin, list<dag>pattern>
989 : I<opcode, OOL, IOL, asmstr, itin> {
993 bit RC = 0; // set by isDOT
994 let Pattern = pattern;
999 let Inst{16-20} = rT;
1000 let Inst{21-30} = xo;
1004 // 1.7.10 XS-Form - SRADI.
1005 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1006 InstrItinClass itin, list<dag> pattern>
1007 : I<opcode, OOL, IOL, asmstr, itin> {
1012 bit RC = 0; // set by isDOT
1013 let Pattern = pattern;
1015 let Inst{6-10} = RS;
1016 let Inst{11-15} = A;
1017 let Inst{16-20} = SH{4,3,2,1,0};
1018 let Inst{21-29} = xo;
1019 let Inst{30} = SH{5};
1024 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1025 InstrItinClass itin, list<dag> pattern>
1026 : I<opcode, OOL, IOL, asmstr, itin> {
1031 let Pattern = pattern;
1033 bit RC = 0; // set by isDOT
1035 let Inst{6-10} = RT;
1036 let Inst{11-15} = RA;
1037 let Inst{16-20} = RB;
1039 let Inst{22-30} = xo;
1043 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1044 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1045 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1050 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1051 InstrItinClass itin, list<dag> pattern>
1052 : I<opcode, OOL, IOL, asmstr, itin> {
1058 let Pattern = pattern;
1060 bit RC = 0; // set by isDOT
1062 let Inst{6-10} = FRT;
1063 let Inst{11-15} = FRA;
1064 let Inst{16-20} = FRB;
1065 let Inst{21-25} = FRC;
1066 let Inst{26-30} = xo;
1070 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1071 InstrItinClass itin, list<dag> pattern>
1072 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1076 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1077 InstrItinClass itin, list<dag> pattern>
1078 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1082 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1083 InstrItinClass itin, list<dag> pattern>
1084 : I<opcode, OOL, IOL, asmstr, itin> {
1090 let Pattern = pattern;
1092 let Inst{6-10} = RT;
1093 let Inst{11-15} = RA;
1094 let Inst{16-20} = RB;
1095 let Inst{21-25} = COND;
1096 let Inst{26-30} = xo;
1101 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1102 InstrItinClass itin, list<dag> pattern>
1103 : I<opcode, OOL, IOL, asmstr, itin> {
1110 let Pattern = pattern;
1112 bit RC = 0; // set by isDOT
1114 let Inst{6-10} = RS;
1115 let Inst{11-15} = RA;
1116 let Inst{16-20} = RB;
1117 let Inst{21-25} = MB;
1118 let Inst{26-30} = ME;
1122 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1123 InstrItinClass itin, list<dag> pattern>
1124 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1128 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1129 InstrItinClass itin, list<dag> pattern>
1130 : I<opcode, OOL, IOL, asmstr, itin> {
1136 let Pattern = pattern;
1138 bit RC = 0; // set by isDOT
1140 let Inst{6-10} = RS;
1141 let Inst{11-15} = RA;
1142 let Inst{16-20} = SH{4,3,2,1,0};
1143 let Inst{21-26} = MBE{4,3,2,1,0,5};
1144 let Inst{27-29} = xo;
1145 let Inst{30} = SH{5};
1149 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1150 InstrItinClass itin, list<dag> pattern>
1151 : I<opcode, OOL, IOL, asmstr, itin> {
1157 let Pattern = pattern;
1159 bit RC = 0; // set by isDOT
1161 let Inst{6-10} = RS;
1162 let Inst{11-15} = RA;
1163 let Inst{16-20} = RB;
1164 let Inst{21-26} = MBE{4,3,2,1,0,5};
1165 let Inst{27-30} = xo;
1172 // VAForm_1 - DACB ordering.
1173 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1174 InstrItinClass itin, list<dag> pattern>
1175 : I<4, OOL, IOL, asmstr, itin> {
1181 let Pattern = pattern;
1183 let Inst{6-10} = VD;
1184 let Inst{11-15} = VA;
1185 let Inst{16-20} = VB;
1186 let Inst{21-25} = VC;
1187 let Inst{26-31} = xo;
1190 // VAForm_1a - DABC ordering.
1191 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1192 InstrItinClass itin, list<dag> pattern>
1193 : I<4, OOL, IOL, asmstr, itin> {
1199 let Pattern = pattern;
1201 let Inst{6-10} = VD;
1202 let Inst{11-15} = VA;
1203 let Inst{16-20} = VB;
1204 let Inst{21-25} = VC;
1205 let Inst{26-31} = xo;
1208 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1209 InstrItinClass itin, list<dag> pattern>
1210 : I<4, OOL, IOL, asmstr, itin> {
1216 let Pattern = pattern;
1218 let Inst{6-10} = VD;
1219 let Inst{11-15} = VA;
1220 let Inst{16-20} = VB;
1222 let Inst{22-25} = SH;
1223 let Inst{26-31} = xo;
1227 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1228 InstrItinClass itin, list<dag> pattern>
1229 : I<4, OOL, IOL, asmstr, itin> {
1234 let Pattern = pattern;
1236 let Inst{6-10} = VD;
1237 let Inst{11-15} = VA;
1238 let Inst{16-20} = VB;
1239 let Inst{21-31} = xo;
1242 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1243 InstrItinClass itin, list<dag> pattern>
1244 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1250 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1251 InstrItinClass itin, list<dag> pattern>
1252 : I<4, OOL, IOL, asmstr, itin> {
1256 let Pattern = pattern;
1258 let Inst{6-10} = VD;
1259 let Inst{11-15} = 0;
1260 let Inst{16-20} = VB;
1261 let Inst{21-31} = xo;
1264 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1265 InstrItinClass itin, list<dag> pattern>
1266 : I<4, OOL, IOL, asmstr, itin> {
1270 let Pattern = pattern;
1272 let Inst{6-10} = VD;
1273 let Inst{11-15} = IMM;
1274 let Inst{16-20} = 0;
1275 let Inst{21-31} = xo;
1278 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1279 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1280 InstrItinClass itin, list<dag> pattern>
1281 : I<4, OOL, IOL, asmstr, itin> {
1284 let Pattern = pattern;
1286 let Inst{6-10} = VD;
1287 let Inst{11-15} = 0;
1288 let Inst{16-20} = 0;
1289 let Inst{21-31} = xo;
1292 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1293 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1294 InstrItinClass itin, list<dag> pattern>
1295 : I<4, OOL, IOL, asmstr, itin> {
1298 let Pattern = pattern;
1301 let Inst{11-15} = 0;
1302 let Inst{16-20} = VB;
1303 let Inst{21-31} = xo;
1307 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1308 InstrItinClass itin, list<dag> pattern>
1309 : I<4, OOL, IOL, asmstr, itin> {
1315 let Pattern = pattern;
1317 let Inst{6-10} = VD;
1318 let Inst{11-15} = VA;
1319 let Inst{16-20} = VB;
1321 let Inst{22-31} = xo;
1324 //===----------------------------------------------------------------------===//
1325 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1326 : I<0, OOL, IOL, asmstr, NoItinerary> {
1327 let isCodeGenOnly = 1;
1329 let Pattern = pattern;