1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
40 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
41 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
42 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
43 class PPC970_MicroCode;
45 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
46 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
47 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
48 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
49 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
50 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
51 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
52 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
54 // Two joined instructions; used to emit two adjacent instructions as one.
55 // The itinerary from the first instruction is used for scheduling and
57 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
62 bit PPC64 = 0; // Default value, override with isPPC64
64 let Namespace = "PPC";
65 let Inst{0-5} = opcode1;
66 let Inst{32-37} = opcode2;
67 let OutOperandList = OOL;
68 let InOperandList = IOL;
69 let AsmString = asmstr;
72 bits<1> PPC970_First = 0;
73 bits<1> PPC970_Single = 0;
74 bits<1> PPC970_Cracked = 0;
75 bits<3> PPC970_Unit = 0;
77 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
78 /// these must be reflected there! See comments there for what these are.
79 let TSFlags{0} = PPC970_First;
80 let TSFlags{1} = PPC970_Single;
81 let TSFlags{2} = PPC970_Cracked;
82 let TSFlags{5-3} = PPC970_Unit;
86 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
87 InstrItinClass itin, list<dag> pattern>
88 : I<opcode, OOL, IOL, asmstr, itin> {
89 let Pattern = pattern;
98 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
99 : I<opcode, OOL, IOL, asmstr, BrB> {
100 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
105 let BI{0-1} = BIBO{5-6};
106 let BI{2-4} = CR{0-2};
108 let Inst{6-10} = BIBO{4-0};
109 let Inst{11-15} = BI;
110 let Inst{16-29} = BD;
117 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
118 InstrItinClass itin, list<dag> pattern>
119 : I<opcode, OOL, IOL, asmstr, itin> {
124 let Pattern = pattern;
131 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
132 InstrItinClass itin, list<dag> pattern>
133 : I<opcode, OOL, IOL, asmstr, itin> {
137 let Pattern = pattern;
140 let Inst{11-15} = Addr{20-16}; // Base Reg
141 let Inst{16-31} = Addr{15-0}; // Displacement
144 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
145 InstrItinClass itin, list<dag> pattern>
146 : I<opcode, OOL, IOL, asmstr, itin> {
151 let Pattern = pattern;
159 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
160 InstrItinClass itin, list<dag> pattern>
161 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>;
163 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
164 InstrItinClass itin, list<dag> pattern>
165 : I<opcode, OOL, IOL, asmstr, itin> {
169 let Pattern = pattern;
176 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
177 InstrItinClass itin, list<dag> pattern>
178 : I<opcode, OOL, IOL, asmstr, itin> {
183 let Pattern = pattern;
190 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
191 InstrItinClass itin, list<dag> pattern>
192 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
197 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
198 dag OOL, dag IOL, string asmstr,
199 InstrItinClass itin, list<dag> pattern>
200 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
204 let Pattern = pattern;
212 let Inst{43-47} = Addr{20-16}; // Base Reg
213 let Inst{48-63} = Addr{15-0}; // Displacement
216 // This is used to emit BL8+NOP.
217 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
218 dag OOL, dag IOL, string asmstr,
219 InstrItinClass itin, list<dag> pattern>
220 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
221 OOL, IOL, asmstr, itin, pattern> {
226 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
228 : I<opcode, OOL, IOL, asmstr, itin> {
237 let Inst{11-15} = RA;
241 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
243 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
247 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
249 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
251 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
253 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
259 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
260 InstrItinClass itin, list<dag> pattern>
261 : I<opcode, OOL, IOL, asmstr, itin> {
265 let Pattern = pattern;
267 let Inst{6-10} = RST;
268 let Inst{11-15} = DS_RA{18-14}; // Register #
269 let Inst{16-29} = DS_RA{13-0}; // Displacement.
270 let Inst{30-31} = xo;
273 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
274 InstrItinClass itin, list<dag> pattern>
275 : I<opcode, OOL, IOL, asmstr, itin> {
280 let Pattern = pattern;
282 let Inst{6-10} = RST;
283 let Inst{11-15} = RA;
284 let Inst{16-29} = DS;
285 let Inst{30-31} = xo;
289 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
290 InstrItinClass itin, list<dag> pattern>
291 : I<opcode, OOL, IOL, asmstr, itin> {
296 let Pattern = pattern;
298 bit RC = 0; // set by isDOT
300 let Inst{6-10} = RST;
303 let Inst{21-30} = xo;
307 // This is the same as XForm_base_r3xo, but the first two operands are swapped
308 // when code is emitted.
309 class XForm_base_r3xo_swapped
310 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
312 : I<opcode, OOL, IOL, asmstr, itin> {
317 bit RC = 0; // set by isDOT
319 let Inst{6-10} = RST;
322 let Inst{21-30} = xo;
327 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
328 InstrItinClass itin, list<dag> pattern>
329 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
331 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
332 InstrItinClass itin, list<dag> pattern>
333 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
334 let Pattern = pattern;
337 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
338 InstrItinClass itin, list<dag> pattern>
339 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
341 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
342 InstrItinClass itin, list<dag> pattern>
343 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
344 let Pattern = pattern;
347 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
348 InstrItinClass itin, list<dag> pattern>
349 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
351 let Pattern = pattern;
354 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
356 : I<opcode, OOL, IOL, asmstr, itin> {
365 let Inst{11-15} = RA;
366 let Inst{16-20} = RB;
367 let Inst{21-30} = xo;
371 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
373 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
377 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
379 : I<opcode, OOL, IOL, asmstr, itin> {
386 let Inst{11-15} = FRA;
387 let Inst{16-20} = FRB;
388 let Inst{21-30} = xo;
392 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
393 InstrItinClass itin, list<dag> pattern>
394 : I<opcode, OOL, IOL, asmstr, itin> {
395 let Pattern = pattern;
399 let Inst{21-30} = xo;
403 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
404 string asmstr, InstrItinClass itin, list<dag> pattern>
405 : I<opcode, OOL, IOL, asmstr, itin> {
406 let Pattern = pattern;
410 let Inst{21-30} = xo;
414 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
415 InstrItinClass itin, list<dag> pattern>
416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
419 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
420 InstrItinClass itin, list<dag> pattern>
421 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
425 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
426 InstrItinClass itin, list<dag> pattern>
427 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
430 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
431 // numbers presumably relates to some document, but I haven't found it.
432 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
433 InstrItinClass itin, list<dag> pattern>
434 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
435 let Pattern = pattern;
437 bit RC = 0; // set by isDOT
439 let Inst{6-10} = RST;
441 let Inst{21-30} = xo;
444 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
445 InstrItinClass itin, list<dag> pattern>
446 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
447 let Pattern = pattern;
450 bit RC = 0; // set by isDOT
454 let Inst{21-30} = xo;
458 // DCB_Form - Form X instruction, used for dcb* instructions.
459 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
460 InstrItinClass itin, list<dag> pattern>
461 : I<31, OOL, IOL, asmstr, itin> {
465 let Pattern = pattern;
467 let Inst{6-10} = immfield;
470 let Inst{21-30} = xo;
475 // DSS_Form - Form X instruction, used for altivec dss* instructions.
476 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
477 InstrItinClass itin, list<dag> pattern>
478 : I<31, OOL, IOL, asmstr, itin> {
484 let Pattern = pattern;
488 let Inst{9-10} = STRM;
491 let Inst{21-30} = xo;
496 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
497 InstrItinClass itin, list<dag> pattern>
498 : I<opcode, OOL, IOL, asmstr, itin> {
503 let Pattern = pattern;
505 let Inst{6-10} = CRD;
506 let Inst{11-15} = CRA;
507 let Inst{16-20} = CRB;
508 let Inst{21-30} = xo;
512 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
513 InstrItinClass itin, list<dag> pattern>
514 : I<opcode, OOL, IOL, asmstr, itin> {
517 let Pattern = pattern;
519 let Inst{6-10} = CRD;
520 let Inst{11-15} = CRD;
521 let Inst{16-20} = CRD;
522 let Inst{21-30} = xo;
526 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
527 InstrItinClass itin, list<dag> pattern>
528 : I<opcode, OOL, IOL, asmstr, itin> {
533 let Pattern = pattern;
536 let Inst{11-15} = BI;
538 let Inst{19-20} = BH;
539 let Inst{21-30} = xo;
543 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
544 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
545 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
546 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
550 let BI{0-1} = BIBO{0-1};
556 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
557 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
558 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
564 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
566 : I<opcode, OOL, IOL, asmstr, itin> {
572 let Inst{11-13} = BFA;
575 let Inst{21-30} = xo;
580 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
582 : I<opcode, OOL, IOL, asmstr, itin> {
587 let Inst{11} = SPR{4};
588 let Inst{12} = SPR{3};
589 let Inst{13} = SPR{2};
590 let Inst{14} = SPR{1};
591 let Inst{15} = SPR{0};
592 let Inst{16} = SPR{9};
593 let Inst{17} = SPR{8};
594 let Inst{18} = SPR{7};
595 let Inst{19} = SPR{6};
596 let Inst{20} = SPR{5};
597 let Inst{21-30} = xo;
601 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
602 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
603 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
607 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
609 : I<opcode, OOL, IOL, asmstr, itin> {
614 let Inst{21-30} = xo;
618 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
620 : I<opcode, OOL, IOL, asmstr, itin> {
626 let Inst{12-19} = FXM;
628 let Inst{21-30} = xo;
632 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
634 : I<opcode, OOL, IOL, asmstr, itin> {
640 let Inst{12-19} = FXM;
642 let Inst{21-30} = xo;
646 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
648 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
650 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
651 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
652 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
657 // This is probably 1.7.9, but I don't have the reference that uses this
658 // numbering scheme...
659 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
660 string cstr, InstrItinClass itin, list<dag>pattern>
661 : I<opcode, OOL, IOL, asmstr, itin> {
665 bit RC = 0; // set by isDOT
666 let Pattern = pattern;
667 let Constraints = cstr;
672 let Inst{16-20} = RT;
673 let Inst{21-30} = xo;
677 // 1.7.10 XS-Form - SRADI.
678 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
679 InstrItinClass itin, list<dag> pattern>
680 : I<opcode, OOL, IOL, asmstr, itin> {
685 bit RC = 0; // set by isDOT
686 let Pattern = pattern;
690 let Inst{16-20} = SH{4,3,2,1,0};
691 let Inst{21-29} = xo;
692 let Inst{30} = SH{5};
697 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
698 InstrItinClass itin, list<dag> pattern>
699 : I<opcode, OOL, IOL, asmstr, itin> {
704 let Pattern = pattern;
706 bit RC = 0; // set by isDOT
709 let Inst{11-15} = RA;
710 let Inst{16-20} = RB;
712 let Inst{22-30} = xo;
716 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
717 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
718 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
723 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
724 InstrItinClass itin, list<dag> pattern>
725 : I<opcode, OOL, IOL, asmstr, itin> {
731 let Pattern = pattern;
733 bit RC = 0; // set by isDOT
735 let Inst{6-10} = FRT;
736 let Inst{11-15} = FRA;
737 let Inst{16-20} = FRB;
738 let Inst{21-25} = FRC;
739 let Inst{26-30} = xo;
743 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
744 InstrItinClass itin, list<dag> pattern>
745 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
749 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
750 InstrItinClass itin, list<dag> pattern>
751 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
756 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
757 InstrItinClass itin, list<dag> pattern>
758 : I<opcode, OOL, IOL, asmstr, itin> {
765 let Pattern = pattern;
767 bit RC = 0; // set by isDOT
770 let Inst{11-15} = RA;
771 let Inst{16-20} = RB;
772 let Inst{21-25} = MB;
773 let Inst{26-30} = ME;
777 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
778 InstrItinClass itin, list<dag> pattern>
779 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
783 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
784 InstrItinClass itin, list<dag> pattern>
785 : I<opcode, OOL, IOL, asmstr, itin> {
791 let Pattern = pattern;
793 bit RC = 0; // set by isDOT
796 let Inst{11-15} = RA;
797 let Inst{16-20} = SH{4,3,2,1,0};
798 let Inst{21-26} = MBE{4,3,2,1,0,5};
799 let Inst{27-29} = xo;
800 let Inst{30} = SH{5};
808 // VAForm_1 - DACB ordering.
809 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
810 InstrItinClass itin, list<dag> pattern>
811 : I<4, OOL, IOL, asmstr, itin> {
817 let Pattern = pattern;
820 let Inst{11-15} = VA;
821 let Inst{16-20} = VB;
822 let Inst{21-25} = VC;
823 let Inst{26-31} = xo;
826 // VAForm_1a - DABC ordering.
827 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
828 InstrItinClass itin, list<dag> pattern>
829 : I<4, OOL, IOL, asmstr, itin> {
835 let Pattern = pattern;
838 let Inst{11-15} = VA;
839 let Inst{16-20} = VB;
840 let Inst{21-25} = VC;
841 let Inst{26-31} = xo;
844 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
845 InstrItinClass itin, list<dag> pattern>
846 : I<4, OOL, IOL, asmstr, itin> {
852 let Pattern = pattern;
855 let Inst{11-15} = VA;
856 let Inst{16-20} = VB;
858 let Inst{22-25} = SH;
859 let Inst{26-31} = xo;
863 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
864 InstrItinClass itin, list<dag> pattern>
865 : I<4, OOL, IOL, asmstr, itin> {
870 let Pattern = pattern;
873 let Inst{11-15} = VA;
874 let Inst{16-20} = VB;
875 let Inst{21-31} = xo;
878 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
879 InstrItinClass itin, list<dag> pattern>
880 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
886 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
887 InstrItinClass itin, list<dag> pattern>
888 : I<4, OOL, IOL, asmstr, itin> {
892 let Pattern = pattern;
896 let Inst{16-20} = VB;
897 let Inst{21-31} = xo;
900 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
901 InstrItinClass itin, list<dag> pattern>
902 : I<4, OOL, IOL, asmstr, itin> {
906 let Pattern = pattern;
909 let Inst{11-15} = IMM;
911 let Inst{21-31} = xo;
914 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
915 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
916 InstrItinClass itin, list<dag> pattern>
917 : I<4, OOL, IOL, asmstr, itin> {
920 let Pattern = pattern;
925 let Inst{21-31} = xo;
928 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
929 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
930 InstrItinClass itin, list<dag> pattern>
931 : I<4, OOL, IOL, asmstr, itin> {
934 let Pattern = pattern;
938 let Inst{16-20} = VB;
939 let Inst{21-31} = xo;
943 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
944 InstrItinClass itin, list<dag> pattern>
945 : I<4, OOL, IOL, asmstr, itin> {
951 let Pattern = pattern;
954 let Inst{11-15} = VA;
955 let Inst{16-20} = VB;
957 let Inst{22-31} = xo;
960 //===----------------------------------------------------------------------===//
961 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
962 : I<0, OOL, IOL, asmstr, NoItinerary> {
964 let Pattern = pattern;