1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
21 let Namespace = "PPC";
22 let Inst{0-5} = opcode;
24 let AsmString = asmstr;
27 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
28 /// these must be reflected there! See comments there for what these are.
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
35 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
36 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
37 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
38 class PPC970_MicroCode;
40 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
41 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
42 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
43 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
44 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
45 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
46 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
47 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
51 class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr,
52 InstrItinClass itin, list<dag> pattern>
53 : I<opcode, OL, asmstr, itin> {
54 let Pattern = pattern;
63 class BForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr>
64 : I<opcode, OL, asmstr, BrB> {
65 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
70 let BI{0-1} = BIBO{5-6};
71 let BI{2-4} = CR{0-2};
73 let Inst{6-10} = BIBO{4-0};
82 class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
84 : I<opcode, OL, asmstr, itin> {
89 let Pattern = pattern;
96 class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
98 : I<opcode, OL, asmstr, itin> {
103 let Pattern = pattern;
110 class DForm_2<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
112 : DForm_base<opcode, OL, asmstr, itin, pattern>;
114 class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
116 : I<opcode, OL, asmstr, itin> {
120 let Pattern = pattern;
127 class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
129 : I<opcode, OL, asmstr, itin> {
134 let Pattern = pattern;
141 class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
143 : DForm_1<opcode, OL, asmstr, itin, pattern> {
149 class DForm_5<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
150 : I<opcode, OL, asmstr, itin> {
159 let Inst{11-15} = RA;
163 class DForm_5_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
164 : DForm_5<opcode, OL, asmstr, itin> {
168 class DForm_6<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
169 : DForm_5<opcode, OL, asmstr, itin>;
171 class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
172 : DForm_6<opcode, OL, asmstr, itin> {
178 class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
179 InstrItinClass itin, list<dag> pattern>
180 : I<opcode, OL, asmstr, itin> {
185 let Pattern = pattern;
187 let Inst{6-10} = RST;
188 let Inst{11-15} = RA;
189 let Inst{16-29} = DS;
190 let Inst{30-31} = xo;
194 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
195 InstrItinClass itin, list<dag> pattern>
196 : I<opcode, OL, asmstr, itin> {
201 let Pattern = pattern;
203 bit RC = 0; // set by isDOT
205 let Inst{6-10} = RST;
208 let Inst{21-30} = xo;
212 // This is the same as XForm_base_r3xo, but the first two operands are swapped
213 // when code is emitted.
214 class XForm_base_r3xo_swapped
215 <bits<6> opcode, bits<10> xo, dag OL, string asmstr,
217 : I<opcode, OL, asmstr, itin> {
222 bit RC = 0; // set by isDOT
224 let Inst{6-10} = RST;
227 let Inst{21-30} = xo;
232 class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
233 InstrItinClass itin, list<dag> pattern>
234 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>;
236 class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
237 InstrItinClass itin, list<dag> pattern>
238 : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> {
239 let Pattern = pattern;
242 class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
243 InstrItinClass itin, list<dag> pattern>
244 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>;
246 class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
247 InstrItinClass itin, list<dag> pattern>
248 : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> {
249 let Pattern = pattern;
252 class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
253 InstrItinClass itin, list<dag> pattern>
254 : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> {
256 let Pattern = pattern;
259 class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
261 : I<opcode, OL, asmstr, itin> {
270 let Inst{11-15} = RA;
271 let Inst{16-20} = RB;
272 let Inst{21-30} = xo;
276 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
278 : XForm_16<opcode, xo, OL, asmstr, itin> {
282 class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
284 : I<opcode, OL, asmstr, itin> {
291 let Inst{11-15} = FRA;
292 let Inst{16-20} = FRB;
293 let Inst{21-30} = xo;
297 class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
298 InstrItinClass itin, list<dag> pattern>
299 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
302 class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
303 InstrItinClass itin, list<dag> pattern>
304 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
308 class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
313 // DCB_Form - Form X instruction, used for dcb* instructions.
314 class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr,
315 InstrItinClass itin, list<dag> pattern>
316 : I<31, OL, asmstr, itin> {
320 let Pattern = pattern;
322 let Inst{6-10} = immfield;
325 let Inst{21-30} = xo;
330 // DSS_Form - Form X instruction, used for altivec dss* instructions.
331 class DSS_Form<bits<10> xo, dag OL, string asmstr,
332 InstrItinClass itin, list<dag> pattern>
333 : I<31, OL, asmstr, itin> {
339 let Pattern = pattern;
343 let Inst{9-10} = STRM;
346 let Inst{21-30} = xo;
351 class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
353 : I<opcode, OL, asmstr, itin> {
362 let Inst{9-10} = CRDb;
363 let Inst{11-13} = CRA;
364 let Inst{14-15} = CRAb;
365 let Inst{16-18} = CRB;
366 let Inst{19-20} = CRBb;
367 let Inst{21-30} = xo;
371 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr,
372 InstrItinClass itin, list<dag> pattern>
373 : I<opcode, OL, asmstr, itin> {
378 let Pattern = pattern;
381 let Inst{11-15} = BI;
383 let Inst{19-20} = BH;
384 let Inst{21-30} = xo;
388 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
389 dag OL, string asmstr, InstrItinClass itin, list<dag> pattern>
390 : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> {
391 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
395 let BI{0-1} = BIBO{0-1};
401 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
402 dag OL, string asmstr, InstrItinClass itin, list<dag> pattern>
403 : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> {
409 class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
411 : I<opcode, OL, asmstr, itin> {
417 let Inst{11-13} = BFA;
420 let Inst{21-30} = xo;
425 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
427 : I<opcode, OL, asmstr, itin> {
432 let Inst{11} = SPR{4};
433 let Inst{12} = SPR{3};
434 let Inst{13} = SPR{2};
435 let Inst{14} = SPR{1};
436 let Inst{15} = SPR{0};
437 let Inst{16} = SPR{9};
438 let Inst{17} = SPR{8};
439 let Inst{18} = SPR{7};
440 let Inst{19} = SPR{6};
441 let Inst{20} = SPR{5};
442 let Inst{21-30} = xo;
446 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
447 dag OL, string asmstr, InstrItinClass itin>
448 : XFXForm_1<opcode, xo, OL, asmstr, itin> {
452 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
454 : I<opcode, OL, asmstr, itin> {
459 let Inst{21-30} = xo;
463 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
465 : I<opcode, OL, asmstr, itin> {
471 let Inst{12-19} = FXM;
473 let Inst{21-30} = xo;
477 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
479 : I<opcode, OL, asmstr, itin> {
485 let Inst{12-19} = FXM;
487 let Inst{21-30} = xo;
491 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
493 : XFXForm_1<opcode, xo, OL, asmstr, itin>;
495 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
496 dag OL, string asmstr, InstrItinClass itin>
497 : XFXForm_7<opcode, xo, OL, asmstr, itin> {
501 // 1.7.10 XS-Form - SRADI.
502 class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr,
503 InstrItinClass itin, list<dag> pattern>
504 : I<opcode, OL, asmstr, itin> {
509 bit RC = 0; // set by isDOT
510 let Pattern = pattern;
514 let Inst{16-20} = SH{4,3,2,1,0};
515 let Inst{21-29} = xo;
516 let Inst{30} = SH{5};
521 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr,
522 InstrItinClass itin, list<dag> pattern>
523 : I<opcode, OL, asmstr, itin> {
528 let Pattern = pattern;
530 bit RC = 0; // set by isDOT
533 let Inst{11-15} = RA;
534 let Inst{16-20} = RB;
536 let Inst{22-30} = xo;
540 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
541 dag OL, string asmstr, InstrItinClass itin, list<dag> pattern>
542 : XOForm_1<opcode, xo, oe, OL, asmstr, itin, pattern> {
547 class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
548 InstrItinClass itin, list<dag> pattern>
549 : I<opcode, OL, asmstr, itin> {
555 let Pattern = pattern;
557 bit RC = 0; // set by isDOT
559 let Inst{6-10} = FRT;
560 let Inst{11-15} = FRA;
561 let Inst{16-20} = FRB;
562 let Inst{21-25} = FRC;
563 let Inst{26-30} = xo;
567 class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
568 InstrItinClass itin, list<dag> pattern>
569 : AForm_1<opcode, xo, OL, asmstr, itin, pattern> {
573 class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
574 InstrItinClass itin, list<dag> pattern>
575 : AForm_1<opcode, xo, OL, asmstr, itin, pattern> {
580 class MForm_1<bits<6> opcode, dag OL, string asmstr,
581 InstrItinClass itin, list<dag> pattern>
582 : I<opcode, OL, asmstr, itin> {
589 let Pattern = pattern;
591 bit RC = 0; // set by isDOT
594 let Inst{11-15} = RA;
595 let Inst{16-20} = RB;
596 let Inst{21-25} = MB;
597 let Inst{26-30} = ME;
601 class MForm_2<bits<6> opcode, dag OL, string asmstr,
602 InstrItinClass itin, list<dag> pattern>
603 : MForm_1<opcode, OL, asmstr, itin, pattern> {
607 class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
608 InstrItinClass itin, list<dag> pattern>
609 : I<opcode, OL, asmstr, itin> {
615 let Pattern = pattern;
617 bit RC = 0; // set by isDOT
620 let Inst{11-15} = RA;
621 let Inst{16-20} = SH{4,3,2,1,0};
622 let Inst{21-26} = MBE{4,3,2,1,0,5};
623 let Inst{27-29} = xo;
624 let Inst{30} = SH{5};
632 // VAForm_1 - DACB ordering.
633 class VAForm_1<bits<6> xo, dag OL, string asmstr,
634 InstrItinClass itin, list<dag> pattern>
635 : I<4, OL, asmstr, itin> {
641 let Pattern = pattern;
644 let Inst{11-15} = VA;
645 let Inst{16-20} = VB;
646 let Inst{21-25} = VC;
647 let Inst{26-31} = xo;
650 // VAForm_1a - DABC ordering.
651 class VAForm_1a<bits<6> xo, dag OL, string asmstr,
652 InstrItinClass itin, list<dag> pattern>
653 : I<4, OL, asmstr, itin> {
659 let Pattern = pattern;
662 let Inst{11-15} = VA;
663 let Inst{16-20} = VB;
664 let Inst{21-25} = VC;
665 let Inst{26-31} = xo;
668 class VAForm_2<bits<6> xo, dag OL, string asmstr,
669 InstrItinClass itin, list<dag> pattern>
670 : I<4, OL, asmstr, itin> {
676 let Pattern = pattern;
679 let Inst{11-15} = VA;
680 let Inst{16-20} = VB;
682 let Inst{22-25} = SH;
683 let Inst{26-31} = xo;
687 class VXForm_1<bits<11> xo, dag OL, string asmstr,
688 InstrItinClass itin, list<dag> pattern>
689 : I<4, OL, asmstr, itin> {
694 let Pattern = pattern;
697 let Inst{11-15} = VA;
698 let Inst{16-20} = VB;
699 let Inst{21-31} = xo;
702 class VXForm_setzero<bits<11> xo, dag OL, string asmstr,
703 InstrItinClass itin, list<dag> pattern>
704 : VXForm_1<xo, OL, asmstr, itin, pattern> {
710 class VXForm_2<bits<11> xo, dag OL, string asmstr,
711 InstrItinClass itin, list<dag> pattern>
712 : I<4, OL, asmstr, itin> {
716 let Pattern = pattern;
720 let Inst{16-20} = VB;
721 let Inst{21-31} = xo;
724 class VXForm_3<bits<11> xo, dag OL, string asmstr,
725 InstrItinClass itin, list<dag> pattern>
726 : I<4, OL, asmstr, itin> {
730 let Pattern = pattern;
733 let Inst{11-15} = IMM;
735 let Inst{21-31} = xo;
738 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
739 class VXForm_4<bits<11> xo, dag OL, string asmstr,
740 InstrItinClass itin, list<dag> pattern>
741 : I<4, OL, asmstr, itin> {
744 let Pattern = pattern;
749 let Inst{21-31} = xo;
752 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
753 class VXForm_5<bits<11> xo, dag OL, string asmstr,
754 InstrItinClass itin, list<dag> pattern>
755 : I<4, OL, asmstr, itin> {
758 let Pattern = pattern;
762 let Inst{16-20} = VB;
763 let Inst{21-31} = xo;
767 class VXRForm_1<bits<10> xo, dag OL, string asmstr,
768 InstrItinClass itin, list<dag> pattern>
769 : I<4, OL, asmstr, itin> {
775 let Pattern = pattern;
778 let Inst{11-15} = VA;
779 let Inst{16-20} = VB;
781 let Inst{22-31} = xo;
784 //===----------------------------------------------------------------------===//
785 class Pseudo<dag OL, string asmstr, list<dag> pattern>
786 : I<0, OL, asmstr, NoItinerary> {
788 let Pattern = pattern;