1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
167 class SCForm<bits<6> opcode, bits<1> xo,
168 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
170 : I<opcode, OOL, IOL, asmstr, itin> {
173 let Pattern = pattern;
175 let Inst{20-26} = LEV;
180 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
181 InstrItinClass itin, list<dag> pattern>
182 : I<opcode, OOL, IOL, asmstr, itin> {
187 let Pattern = pattern;
194 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
195 InstrItinClass itin, list<dag> pattern>
196 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
203 let Inst{11-15} = Addr{20-16}; // Base Reg
204 let Inst{16-31} = Addr{15-0}; // Displacement
207 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
214 let Pattern = pattern;
222 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
223 InstrItinClass itin, list<dag> pattern>
224 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
226 // Even though ADDICo does not really have an RC bit, provide
227 // the declaration of one here so that isDOT has something to set.
231 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
232 InstrItinClass itin, list<dag> pattern>
233 : I<opcode, OOL, IOL, asmstr, itin> {
237 let Pattern = pattern;
244 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
251 let Pattern = pattern;
258 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
259 InstrItinClass itin, list<dag> pattern>
260 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
265 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
266 string asmstr, InstrItinClass itin,
268 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
274 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
275 dag OOL, dag IOL, string asmstr,
276 InstrItinClass itin, list<dag> pattern>
277 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
281 let Pattern = pattern;
289 let Inst{43-47} = Addr{20-16}; // Base Reg
290 let Inst{48-63} = Addr{15-0}; // Displacement
293 // This is used to emit BL8+NOP.
294 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
295 dag OOL, dag IOL, string asmstr,
296 InstrItinClass itin, list<dag> pattern>
297 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
298 OOL, IOL, asmstr, itin, pattern> {
303 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
305 : I<opcode, OOL, IOL, asmstr, itin> {
314 let Inst{11-15} = RA;
318 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
320 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
324 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
326 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
328 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
330 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
336 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
337 InstrItinClass itin, list<dag> pattern>
338 : I<opcode, OOL, IOL, asmstr, itin> {
342 let Pattern = pattern;
344 let Inst{6-10} = RST;
345 let Inst{11-15} = DS_RA{18-14}; // Register #
346 let Inst{16-29} = DS_RA{13-0}; // Displacement.
347 let Inst{30-31} = xo;
350 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
351 InstrItinClass itin, list<dag> pattern>
352 : I<opcode, OOL, IOL, asmstr, itin> {
357 let Pattern = pattern;
359 let Inst{6-10} = RST;
360 let Inst{11-15} = RA;
361 let Inst{16-29} = DS;
362 let Inst{30-31} = xo;
366 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
367 InstrItinClass itin, list<dag> pattern>
368 : I<opcode, OOL, IOL, asmstr, itin> {
373 let Pattern = pattern;
375 bit RC = 0; // set by isDOT
377 let Inst{6-10} = RST;
380 let Inst{21-30} = xo;
384 // This is the same as XForm_base_r3xo, but the first two operands are swapped
385 // when code is emitted.
386 class XForm_base_r3xo_swapped
387 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
389 : I<opcode, OOL, IOL, asmstr, itin> {
394 bit RC = 0; // set by isDOT
396 let Inst{6-10} = RST;
399 let Inst{21-30} = xo;
404 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
405 InstrItinClass itin, list<dag> pattern>
406 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
408 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
409 InstrItinClass itin, list<dag> pattern>
410 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
414 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
415 InstrItinClass itin, list<dag> pattern>
416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
421 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
422 InstrItinClass itin, list<dag> pattern>
423 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
424 let Pattern = pattern;
427 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
428 InstrItinClass itin, list<dag> pattern>
429 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
431 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
432 InstrItinClass itin, list<dag> pattern>
433 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
434 let Pattern = pattern;
437 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
438 InstrItinClass itin, list<dag> pattern>
439 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
441 let Pattern = pattern;
444 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
446 : I<opcode, OOL, IOL, asmstr, itin> {
455 let Inst{11-15} = RA;
456 let Inst{16-20} = RB;
457 let Inst{21-30} = xo;
461 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
463 : I<opcode, OOL, IOL, asmstr, itin> {
469 let Inst{21-30} = xo;
472 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
474 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
478 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
480 : I<opcode, OOL, IOL, asmstr, itin> {
487 let Inst{11-15} = FRA;
488 let Inst{16-20} = FRB;
489 let Inst{21-30} = xo;
493 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
494 InstrItinClass itin, list<dag> pattern>
495 : I<opcode, OOL, IOL, asmstr, itin> {
496 let Pattern = pattern;
500 let Inst{21-30} = xo;
504 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
505 string asmstr, InstrItinClass itin, list<dag> pattern>
506 : I<opcode, OOL, IOL, asmstr, itin> {
509 let Pattern = pattern;
514 let Inst{21-30} = xo;
518 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
519 string asmstr, InstrItinClass itin, list<dag> pattern>
520 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
524 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
525 InstrItinClass itin, list<dag> pattern>
526 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
529 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
530 InstrItinClass itin, list<dag> pattern>
531 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
535 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
536 InstrItinClass itin, list<dag> pattern>
537 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
540 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
541 // numbers presumably relates to some document, but I haven't found it.
542 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
543 InstrItinClass itin, list<dag> pattern>
544 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
545 let Pattern = pattern;
547 bit RC = 0; // set by isDOT
549 let Inst{6-10} = RST;
551 let Inst{21-30} = xo;
554 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
555 InstrItinClass itin, list<dag> pattern>
556 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
557 let Pattern = pattern;
560 bit RC = 0; // set by isDOT
564 let Inst{21-30} = xo;
568 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
569 InstrItinClass itin, list<dag> pattern>
570 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
576 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
577 InstrItinClass itin, list<dag> pattern>
578 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
583 // DCB_Form - Form X instruction, used for dcb* instructions.
584 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
585 InstrItinClass itin, list<dag> pattern>
586 : I<31, OOL, IOL, asmstr, itin> {
590 let Pattern = pattern;
592 let Inst{6-10} = immfield;
595 let Inst{21-30} = xo;
600 // DSS_Form - Form X instruction, used for altivec dss* instructions.
601 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
602 InstrItinClass itin, list<dag> pattern>
603 : I<31, OOL, IOL, asmstr, itin> {
609 let Pattern = pattern;
613 let Inst{9-10} = STRM;
616 let Inst{21-30} = xo;
621 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
622 InstrItinClass itin, list<dag> pattern>
623 : I<opcode, OOL, IOL, asmstr, itin> {
628 let Pattern = pattern;
630 let Inst{6-10} = CRD;
631 let Inst{11-15} = CRA;
632 let Inst{16-20} = CRB;
633 let Inst{21-30} = xo;
637 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
638 InstrItinClass itin, list<dag> pattern>
639 : I<opcode, OOL, IOL, asmstr, itin> {
642 let Pattern = pattern;
644 let Inst{6-10} = CRD;
645 let Inst{11-15} = CRD;
646 let Inst{16-20} = CRD;
647 let Inst{21-30} = xo;
651 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
652 InstrItinClass itin, list<dag> pattern>
653 : I<opcode, OOL, IOL, asmstr, itin> {
658 let Pattern = pattern;
661 let Inst{11-15} = BI;
663 let Inst{19-20} = BH;
664 let Inst{21-30} = xo;
668 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
669 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
670 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
671 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
675 let BI{0-1} = BIBO{5-6};
676 let BI{2-4} = CR{0-2};
681 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
682 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
683 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
689 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
691 : I<opcode, OOL, IOL, asmstr, itin> {
697 let Inst{11-13} = BFA;
700 let Inst{21-30} = xo;
705 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
707 : I<opcode, OOL, IOL, asmstr, itin> {
712 let Inst{11} = SPR{4};
713 let Inst{12} = SPR{3};
714 let Inst{13} = SPR{2};
715 let Inst{14} = SPR{1};
716 let Inst{15} = SPR{0};
717 let Inst{16} = SPR{9};
718 let Inst{17} = SPR{8};
719 let Inst{18} = SPR{7};
720 let Inst{19} = SPR{6};
721 let Inst{20} = SPR{5};
722 let Inst{21-30} = xo;
726 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
727 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
728 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
732 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
734 : I<opcode, OOL, IOL, asmstr, itin> {
739 let Inst{21-30} = xo;
743 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
745 : I<opcode, OOL, IOL, asmstr, itin> {
751 let Inst{12-19} = FXM;
753 let Inst{21-30} = xo;
757 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
759 : I<opcode, OOL, IOL, asmstr, itin> {
765 let Inst{12-19} = FXM;
767 let Inst{21-30} = xo;
771 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
773 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
775 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
776 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
777 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
782 // This is probably 1.7.9, but I don't have the reference that uses this
783 // numbering scheme...
784 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
785 InstrItinClass itin, list<dag>pattern>
786 : I<opcode, OOL, IOL, asmstr, itin> {
790 bit RC = 0; // set by isDOT
791 let Pattern = pattern;
796 let Inst{16-20} = rT;
797 let Inst{21-30} = xo;
801 // 1.7.10 XS-Form - SRADI.
802 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
803 InstrItinClass itin, list<dag> pattern>
804 : I<opcode, OOL, IOL, asmstr, itin> {
809 bit RC = 0; // set by isDOT
810 let Pattern = pattern;
814 let Inst{16-20} = SH{4,3,2,1,0};
815 let Inst{21-29} = xo;
816 let Inst{30} = SH{5};
821 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
822 InstrItinClass itin, list<dag> pattern>
823 : I<opcode, OOL, IOL, asmstr, itin> {
828 let Pattern = pattern;
830 bit RC = 0; // set by isDOT
833 let Inst{11-15} = RA;
834 let Inst{16-20} = RB;
836 let Inst{22-30} = xo;
840 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
841 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
842 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
847 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
848 InstrItinClass itin, list<dag> pattern>
849 : I<opcode, OOL, IOL, asmstr, itin> {
855 let Pattern = pattern;
857 bit RC = 0; // set by isDOT
859 let Inst{6-10} = FRT;
860 let Inst{11-15} = FRA;
861 let Inst{16-20} = FRB;
862 let Inst{21-25} = FRC;
863 let Inst{26-30} = xo;
867 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
868 InstrItinClass itin, list<dag> pattern>
869 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
873 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
874 InstrItinClass itin, list<dag> pattern>
875 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
879 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
880 InstrItinClass itin, list<dag> pattern>
881 : I<opcode, OOL, IOL, asmstr, itin> {
887 let Pattern = pattern;
890 let Inst{11-15} = RA;
891 let Inst{16-20} = RB;
892 let Inst{21-25} = COND;
893 let Inst{26-30} = xo;
898 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
899 InstrItinClass itin, list<dag> pattern>
900 : I<opcode, OOL, IOL, asmstr, itin> {
907 let Pattern = pattern;
909 bit RC = 0; // set by isDOT
912 let Inst{11-15} = RA;
913 let Inst{16-20} = RB;
914 let Inst{21-25} = MB;
915 let Inst{26-30} = ME;
919 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
920 InstrItinClass itin, list<dag> pattern>
921 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
925 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
926 InstrItinClass itin, list<dag> pattern>
927 : I<opcode, OOL, IOL, asmstr, itin> {
933 let Pattern = pattern;
935 bit RC = 0; // set by isDOT
938 let Inst{11-15} = RA;
939 let Inst{16-20} = SH{4,3,2,1,0};
940 let Inst{21-26} = MBE{4,3,2,1,0,5};
941 let Inst{27-29} = xo;
942 let Inst{30} = SH{5};
946 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
947 InstrItinClass itin, list<dag> pattern>
948 : I<opcode, OOL, IOL, asmstr, itin> {
954 let Pattern = pattern;
956 bit RC = 0; // set by isDOT
959 let Inst{11-15} = RA;
960 let Inst{16-20} = RB;
961 let Inst{21-26} = MBE{4,3,2,1,0,5};
962 let Inst{27-30} = xo;
969 // VAForm_1 - DACB ordering.
970 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
971 InstrItinClass itin, list<dag> pattern>
972 : I<4, OOL, IOL, asmstr, itin> {
978 let Pattern = pattern;
981 let Inst{11-15} = VA;
982 let Inst{16-20} = VB;
983 let Inst{21-25} = VC;
984 let Inst{26-31} = xo;
987 // VAForm_1a - DABC ordering.
988 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
989 InstrItinClass itin, list<dag> pattern>
990 : I<4, OOL, IOL, asmstr, itin> {
996 let Pattern = pattern;
999 let Inst{11-15} = VA;
1000 let Inst{16-20} = VB;
1001 let Inst{21-25} = VC;
1002 let Inst{26-31} = xo;
1005 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1006 InstrItinClass itin, list<dag> pattern>
1007 : I<4, OOL, IOL, asmstr, itin> {
1013 let Pattern = pattern;
1015 let Inst{6-10} = VD;
1016 let Inst{11-15} = VA;
1017 let Inst{16-20} = VB;
1019 let Inst{22-25} = SH;
1020 let Inst{26-31} = xo;
1024 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1025 InstrItinClass itin, list<dag> pattern>
1026 : I<4, OOL, IOL, asmstr, itin> {
1031 let Pattern = pattern;
1033 let Inst{6-10} = VD;
1034 let Inst{11-15} = VA;
1035 let Inst{16-20} = VB;
1036 let Inst{21-31} = xo;
1039 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1040 InstrItinClass itin, list<dag> pattern>
1041 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1047 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1048 InstrItinClass itin, list<dag> pattern>
1049 : I<4, OOL, IOL, asmstr, itin> {
1053 let Pattern = pattern;
1055 let Inst{6-10} = VD;
1056 let Inst{11-15} = 0;
1057 let Inst{16-20} = VB;
1058 let Inst{21-31} = xo;
1061 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1062 InstrItinClass itin, list<dag> pattern>
1063 : I<4, OOL, IOL, asmstr, itin> {
1067 let Pattern = pattern;
1069 let Inst{6-10} = VD;
1070 let Inst{11-15} = IMM;
1071 let Inst{16-20} = 0;
1072 let Inst{21-31} = xo;
1075 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1076 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1077 InstrItinClass itin, list<dag> pattern>
1078 : I<4, OOL, IOL, asmstr, itin> {
1081 let Pattern = pattern;
1083 let Inst{6-10} = VD;
1084 let Inst{11-15} = 0;
1085 let Inst{16-20} = 0;
1086 let Inst{21-31} = xo;
1089 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1090 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1091 InstrItinClass itin, list<dag> pattern>
1092 : I<4, OOL, IOL, asmstr, itin> {
1095 let Pattern = pattern;
1098 let Inst{11-15} = 0;
1099 let Inst{16-20} = VB;
1100 let Inst{21-31} = xo;
1104 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1105 InstrItinClass itin, list<dag> pattern>
1106 : I<4, OOL, IOL, asmstr, itin> {
1112 let Pattern = pattern;
1114 let Inst{6-10} = VD;
1115 let Inst{11-15} = VA;
1116 let Inst{16-20} = VB;
1118 let Inst{22-31} = xo;
1121 //===----------------------------------------------------------------------===//
1122 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1123 : I<0, OOL, IOL, asmstr, NoItinerary> {
1124 let isCodeGenOnly = 1;
1126 let Pattern = pattern;