1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
388 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
390 : I<opcode, OOL, IOL, asmstr, itin> {
391 let Inst{21-30} = xo;
394 // This is the same as XForm_base_r3xo, but the first two operands are swapped
395 // when code is emitted.
396 class XForm_base_r3xo_swapped
397 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
399 : I<opcode, OOL, IOL, asmstr, itin> {
404 bit RC = 0; // set by isDOT
406 let Inst{6-10} = RST;
409 let Inst{21-30} = xo;
414 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
415 InstrItinClass itin, list<dag> pattern>
416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
418 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
419 InstrItinClass itin, list<dag> pattern>
420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
424 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
425 InstrItinClass itin, list<dag> pattern>
426 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
431 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
432 InstrItinClass itin, list<dag> pattern>
433 : I<opcode, OOL, IOL, asmstr, itin> {
438 let Pattern = pattern;
440 let Inst{6-10} = RST;
443 let Inst{21-30} = xo;
447 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
448 InstrItinClass itin, list<dag> pattern>
449 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
450 let Pattern = pattern;
453 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
454 InstrItinClass itin, list<dag> pattern>
455 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
457 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
458 InstrItinClass itin, list<dag> pattern>
459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
460 let Pattern = pattern;
463 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
464 InstrItinClass itin, list<dag> pattern>
465 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
467 let Pattern = pattern;
470 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
472 : I<opcode, OOL, IOL, asmstr, itin> {
481 let Inst{11-15} = RA;
482 let Inst{16-20} = RB;
483 let Inst{21-30} = xo;
487 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
489 : I<opcode, OOL, IOL, asmstr, itin> {
496 let Inst{11-15} = RA;
497 let Inst{16-20} = RB;
498 let Inst{21-30} = xo;
502 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
504 : I<opcode, OOL, IOL, asmstr, itin> {
509 let Inst{12-15} = SR;
510 let Inst{21-30} = xo;
513 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
515 : I<opcode, OOL, IOL, asmstr, itin> {
519 let Inst{21-30} = xo;
522 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
524 : I<opcode, OOL, IOL, asmstr, itin> {
529 let Inst{16-20} = RB;
530 let Inst{21-30} = xo;
533 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
535 : I<opcode, OOL, IOL, asmstr, itin> {
541 let Inst{21-30} = xo;
544 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
546 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
550 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
552 : I<opcode, OOL, IOL, asmstr, itin> {
559 let Inst{11-15} = FRA;
560 let Inst{16-20} = FRB;
561 let Inst{21-30} = xo;
566 class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
567 InstrItinClass itin, list<dag> pattern>
568 : I<opcode, OOL, IOL, asmstr, itin> {
573 let Pattern = pattern;
575 let Inst{6-10} = FRT;
576 let Inst{11-15} = FRA;
577 let Inst{16-20} = FRB;
578 let Inst{21-30} = xo;
582 class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
583 InstrItinClass itin, list<dag> pattern>
584 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
588 class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
589 InstrItinClass itin, list<dag> pattern>
590 : I<opcode, OOL, IOL, asmstr, itin> {
596 let Pattern = pattern;
598 let Inst{6-10} = FRT;
599 let Inst{11-15} = FRA;
600 let Inst{16-20} = FRB;
601 let Inst{21-24} = tttt;
602 let Inst{25-30} = xo;
606 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
607 InstrItinClass itin, list<dag> pattern>
608 : I<opcode, OOL, IOL, asmstr, itin> {
609 let Pattern = pattern;
613 let Inst{21-30} = xo;
617 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
618 string asmstr, InstrItinClass itin, list<dag> pattern>
619 : I<opcode, OOL, IOL, asmstr, itin> {
622 let Pattern = pattern;
627 let Inst{21-30} = xo;
631 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
632 string asmstr, InstrItinClass itin, list<dag> pattern>
633 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
637 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
638 InstrItinClass itin, list<dag> pattern>
639 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
642 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
643 InstrItinClass itin, list<dag> pattern>
644 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
648 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
649 InstrItinClass itin, list<dag> pattern>
650 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
653 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
654 // numbers presumably relates to some document, but I haven't found it.
655 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
656 InstrItinClass itin, list<dag> pattern>
657 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
658 let Pattern = pattern;
660 bit RC = 0; // set by isDOT
662 let Inst{6-10} = RST;
664 let Inst{21-30} = xo;
667 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
668 InstrItinClass itin, list<dag> pattern>
669 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
670 let Pattern = pattern;
673 bit RC = 0; // set by isDOT
677 let Inst{21-30} = xo;
681 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
682 InstrItinClass itin, list<dag> pattern>
683 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
689 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
690 InstrItinClass itin, list<dag> pattern>
691 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
697 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
698 InstrItinClass itin, list<dag> pattern>
699 : I<opcode, OOL, IOL, asmstr, itin> {
704 let Pattern = pattern;
706 let Inst{6-10} = XT{4-0};
709 let Inst{21-30} = xo;
710 let Inst{31} = XT{5};
713 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
714 InstrItinClass itin, list<dag> pattern>
715 : I<opcode, OOL, IOL, asmstr, itin> {
719 let Pattern = pattern;
721 let Inst{6-10} = XT{4-0};
723 let Inst{16-20} = XB{4-0};
724 let Inst{21-29} = xo;
725 let Inst{30} = XB{5};
726 let Inst{31} = XT{5};
729 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
730 InstrItinClass itin, list<dag> pattern>
731 : I<opcode, OOL, IOL, asmstr, itin> {
735 let Pattern = pattern;
739 let Inst{16-20} = XB{4-0};
740 let Inst{21-29} = xo;
741 let Inst{30} = XB{5};
745 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
746 InstrItinClass itin, list<dag> pattern>
747 : I<opcode, OOL, IOL, asmstr, itin> {
752 let Pattern = pattern;
754 let Inst{6-10} = XT{4-0};
757 let Inst{16-20} = XB{4-0};
758 let Inst{21-29} = xo;
759 let Inst{30} = XB{5};
760 let Inst{31} = XT{5};
763 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
764 InstrItinClass itin, list<dag> pattern>
765 : I<opcode, OOL, IOL, asmstr, itin> {
770 let Pattern = pattern;
772 let Inst{6-10} = XT{4-0};
773 let Inst{11-15} = XA{4-0};
774 let Inst{16-20} = XB{4-0};
775 let Inst{21-28} = xo;
776 let Inst{29} = XA{5};
777 let Inst{30} = XB{5};
778 let Inst{31} = XT{5};
781 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
782 InstrItinClass itin, list<dag> pattern>
783 : I<opcode, OOL, IOL, asmstr, itin> {
788 let Pattern = pattern;
792 let Inst{11-15} = XA{4-0};
793 let Inst{16-20} = XB{4-0};
794 let Inst{21-28} = xo;
795 let Inst{29} = XA{5};
796 let Inst{30} = XB{5};
800 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
801 InstrItinClass itin, list<dag> pattern>
802 : I<opcode, OOL, IOL, asmstr, itin> {
808 let Pattern = pattern;
810 let Inst{6-10} = XT{4-0};
811 let Inst{11-15} = XA{4-0};
812 let Inst{16-20} = XB{4-0};
815 let Inst{24-28} = xo;
816 let Inst{29} = XA{5};
817 let Inst{30} = XB{5};
818 let Inst{31} = XT{5};
821 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
822 InstrItinClass itin, list<dag> pattern>
823 : I<opcode, OOL, IOL, asmstr, itin> {
828 let Pattern = pattern;
830 bit RC = 0; // set by isDOT
832 let Inst{6-10} = XT{4-0};
833 let Inst{11-15} = XA{4-0};
834 let Inst{16-20} = XB{4-0};
836 let Inst{22-28} = xo;
837 let Inst{29} = XA{5};
838 let Inst{30} = XB{5};
839 let Inst{31} = XT{5};
842 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
843 InstrItinClass itin, list<dag> pattern>
844 : I<opcode, OOL, IOL, asmstr, itin> {
850 let Pattern = pattern;
852 let Inst{6-10} = XT{4-0};
853 let Inst{11-15} = XA{4-0};
854 let Inst{16-20} = XB{4-0};
855 let Inst{21-25} = XC{4-0};
856 let Inst{26-27} = xo;
857 let Inst{28} = XC{5};
858 let Inst{29} = XA{5};
859 let Inst{30} = XB{5};
860 let Inst{31} = XT{5};
863 // DCB_Form - Form X instruction, used for dcb* instructions.
864 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
865 InstrItinClass itin, list<dag> pattern>
866 : I<31, OOL, IOL, asmstr, itin> {
870 let Pattern = pattern;
872 let Inst{6-10} = immfield;
875 let Inst{21-30} = xo;
880 // DSS_Form - Form X instruction, used for altivec dss* instructions.
881 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
882 InstrItinClass itin, list<dag> pattern>
883 : I<31, OOL, IOL, asmstr, itin> {
888 let Pattern = pattern;
892 let Inst{9-10} = STRM;
895 let Inst{21-30} = xo;
900 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
901 InstrItinClass itin, list<dag> pattern>
902 : I<opcode, OOL, IOL, asmstr, itin> {
907 let Pattern = pattern;
909 let Inst{6-10} = CRD;
910 let Inst{11-15} = CRA;
911 let Inst{16-20} = CRB;
912 let Inst{21-30} = xo;
916 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
917 InstrItinClass itin, list<dag> pattern>
918 : I<opcode, OOL, IOL, asmstr, itin> {
921 let Pattern = pattern;
923 let Inst{6-10} = CRD;
924 let Inst{11-15} = CRD;
925 let Inst{16-20} = CRD;
926 let Inst{21-30} = xo;
930 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
931 InstrItinClass itin, list<dag> pattern>
932 : I<opcode, OOL, IOL, asmstr, itin> {
937 let Pattern = pattern;
940 let Inst{11-15} = BI;
942 let Inst{19-20} = BH;
943 let Inst{21-30} = xo;
947 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
948 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
949 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
950 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
954 let BI{0-1} = BIBO{5-6};
955 let BI{2-4} = CR{0-2};
959 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
960 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
961 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
966 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
967 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
968 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
974 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
976 : I<opcode, OOL, IOL, asmstr, itin> {
982 let Inst{11-13} = BFA;
985 let Inst{21-30} = xo;
989 class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
991 : I<opcode, OOL, IOL, asmstr, itin> {
1000 let Inst{11-14} = 0;
1002 let Inst{16-19} = U;
1004 let Inst{21-30} = xo;
1008 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1009 bits<6> opcode2, bits<2> xo2,
1010 dag OOL, dag IOL, string asmstr,
1011 InstrItinClass itin, list<dag> pattern>
1012 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1020 let Pattern = pattern;
1022 let Inst{6-10} = BO;
1023 let Inst{11-15} = BI;
1024 let Inst{16-18} = 0;
1025 let Inst{19-20} = BH;
1026 let Inst{21-30} = xo1;
1029 let Inst{38-42} = RST;
1030 let Inst{43-47} = DS_RA{18-14}; // Register #
1031 let Inst{48-61} = DS_RA{13-0}; // Displacement.
1032 let Inst{62-63} = xo2;
1035 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1036 bits<5> bo, bits<5> bi, bit lk,
1037 bits<6> opcode2, bits<2> xo2,
1038 dag OOL, dag IOL, string asmstr,
1039 InstrItinClass itin, list<dag> pattern>
1040 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1041 OOL, IOL, asmstr, itin, pattern> {
1048 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1049 InstrItinClass itin>
1050 : I<opcode, OOL, IOL, asmstr, itin> {
1054 let Inst{6-10} = RT;
1055 let Inst{11} = SPR{4};
1056 let Inst{12} = SPR{3};
1057 let Inst{13} = SPR{2};
1058 let Inst{14} = SPR{1};
1059 let Inst{15} = SPR{0};
1060 let Inst{16} = SPR{9};
1061 let Inst{17} = SPR{8};
1062 let Inst{18} = SPR{7};
1063 let Inst{19} = SPR{6};
1064 let Inst{20} = SPR{5};
1065 let Inst{21-30} = xo;
1069 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1070 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1071 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
1075 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1076 InstrItinClass itin>
1077 : I<opcode, OOL, IOL, asmstr, itin> {
1080 let Inst{6-10} = RT;
1081 let Inst{11-20} = 0;
1082 let Inst{21-30} = xo;
1086 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1087 InstrItinClass itin>
1088 : I<opcode, OOL, IOL, asmstr, itin> {
1092 let Inst{6-10} = rS;
1094 let Inst{12-19} = FXM;
1096 let Inst{21-30} = xo;
1100 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1101 InstrItinClass itin>
1102 : I<opcode, OOL, IOL, asmstr, itin> {
1106 let Inst{6-10} = ST;
1108 let Inst{12-19} = FXM;
1110 let Inst{21-30} = xo;
1114 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1115 InstrItinClass itin>
1116 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1118 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1119 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1120 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1125 // This is probably 1.7.9, but I don't have the reference that uses this
1126 // numbering scheme...
1127 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1128 InstrItinClass itin, list<dag>pattern>
1129 : I<opcode, OOL, IOL, asmstr, itin> {
1133 bit RC = 0; // set by isDOT
1134 let Pattern = pattern;
1137 let Inst{7-14} = FM;
1139 let Inst{16-20} = rT;
1140 let Inst{21-30} = xo;
1144 class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1145 InstrItinClass itin, list<dag>pattern>
1146 : I<opcode, OOL, IOL, asmstr, itin> {
1152 bit RC = 0; // set by isDOT
1153 let Pattern = pattern;
1156 let Inst{7-14} = FLM;
1158 let Inst{16-20} = FRB;
1159 let Inst{21-30} = xo;
1163 // 1.7.10 XS-Form - SRADI.
1164 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1165 InstrItinClass itin, list<dag> pattern>
1166 : I<opcode, OOL, IOL, asmstr, itin> {
1171 bit RC = 0; // set by isDOT
1172 let Pattern = pattern;
1174 let Inst{6-10} = RS;
1175 let Inst{11-15} = A;
1176 let Inst{16-20} = SH{4,3,2,1,0};
1177 let Inst{21-29} = xo;
1178 let Inst{30} = SH{5};
1183 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1184 InstrItinClass itin, list<dag> pattern>
1185 : I<opcode, OOL, IOL, asmstr, itin> {
1190 let Pattern = pattern;
1192 bit RC = 0; // set by isDOT
1194 let Inst{6-10} = RT;
1195 let Inst{11-15} = RA;
1196 let Inst{16-20} = RB;
1198 let Inst{22-30} = xo;
1202 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1203 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1204 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1209 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1210 InstrItinClass itin, list<dag> pattern>
1211 : I<opcode, OOL, IOL, asmstr, itin> {
1217 let Pattern = pattern;
1219 bit RC = 0; // set by isDOT
1221 let Inst{6-10} = FRT;
1222 let Inst{11-15} = FRA;
1223 let Inst{16-20} = FRB;
1224 let Inst{21-25} = FRC;
1225 let Inst{26-30} = xo;
1229 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1230 InstrItinClass itin, list<dag> pattern>
1231 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1235 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1236 InstrItinClass itin, list<dag> pattern>
1237 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1241 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1242 InstrItinClass itin, list<dag> pattern>
1243 : I<opcode, OOL, IOL, asmstr, itin> {
1249 let Pattern = pattern;
1251 let Inst{6-10} = RT;
1252 let Inst{11-15} = RA;
1253 let Inst{16-20} = RB;
1254 let Inst{21-25} = COND;
1255 let Inst{26-30} = xo;
1260 class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1261 InstrItinClass itin, list<dag> pattern>
1262 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1268 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1269 InstrItinClass itin, list<dag> pattern>
1270 : I<opcode, OOL, IOL, asmstr, itin> {
1277 let Pattern = pattern;
1279 bit RC = 0; // set by isDOT
1281 let Inst{6-10} = RS;
1282 let Inst{11-15} = RA;
1283 let Inst{16-20} = RB;
1284 let Inst{21-25} = MB;
1285 let Inst{26-30} = ME;
1289 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1290 InstrItinClass itin, list<dag> pattern>
1291 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1295 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1296 InstrItinClass itin, list<dag> pattern>
1297 : I<opcode, OOL, IOL, asmstr, itin> {
1303 let Pattern = pattern;
1305 bit RC = 0; // set by isDOT
1307 let Inst{6-10} = RS;
1308 let Inst{11-15} = RA;
1309 let Inst{16-20} = SH{4,3,2,1,0};
1310 let Inst{21-26} = MBE{4,3,2,1,0,5};
1311 let Inst{27-29} = xo;
1312 let Inst{30} = SH{5};
1316 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1317 InstrItinClass itin, list<dag> pattern>
1318 : I<opcode, OOL, IOL, asmstr, itin> {
1324 let Pattern = pattern;
1326 bit RC = 0; // set by isDOT
1328 let Inst{6-10} = RS;
1329 let Inst{11-15} = RA;
1330 let Inst{16-20} = RB;
1331 let Inst{21-26} = MBE{4,3,2,1,0,5};
1332 let Inst{27-30} = xo;
1339 // VAForm_1 - DACB ordering.
1340 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1341 InstrItinClass itin, list<dag> pattern>
1342 : I<4, OOL, IOL, asmstr, itin> {
1348 let Pattern = pattern;
1350 let Inst{6-10} = VD;
1351 let Inst{11-15} = VA;
1352 let Inst{16-20} = VB;
1353 let Inst{21-25} = VC;
1354 let Inst{26-31} = xo;
1357 // VAForm_1a - DABC ordering.
1358 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1359 InstrItinClass itin, list<dag> pattern>
1360 : I<4, OOL, IOL, asmstr, itin> {
1366 let Pattern = pattern;
1368 let Inst{6-10} = VD;
1369 let Inst{11-15} = VA;
1370 let Inst{16-20} = VB;
1371 let Inst{21-25} = VC;
1372 let Inst{26-31} = xo;
1375 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1376 InstrItinClass itin, list<dag> pattern>
1377 : I<4, OOL, IOL, asmstr, itin> {
1383 let Pattern = pattern;
1385 let Inst{6-10} = VD;
1386 let Inst{11-15} = VA;
1387 let Inst{16-20} = VB;
1389 let Inst{22-25} = SH;
1390 let Inst{26-31} = xo;
1394 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1395 InstrItinClass itin, list<dag> pattern>
1396 : I<4, OOL, IOL, asmstr, itin> {
1401 let Pattern = pattern;
1403 let Inst{6-10} = VD;
1404 let Inst{11-15} = VA;
1405 let Inst{16-20} = VB;
1406 let Inst{21-31} = xo;
1409 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1410 InstrItinClass itin, list<dag> pattern>
1411 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1417 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1418 InstrItinClass itin, list<dag> pattern>
1419 : I<4, OOL, IOL, asmstr, itin> {
1423 let Pattern = pattern;
1425 let Inst{6-10} = VD;
1426 let Inst{11-15} = 0;
1427 let Inst{16-20} = VB;
1428 let Inst{21-31} = xo;
1431 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1432 InstrItinClass itin, list<dag> pattern>
1433 : I<4, OOL, IOL, asmstr, itin> {
1437 let Pattern = pattern;
1439 let Inst{6-10} = VD;
1440 let Inst{11-15} = IMM;
1441 let Inst{16-20} = 0;
1442 let Inst{21-31} = xo;
1445 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1446 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1447 InstrItinClass itin, list<dag> pattern>
1448 : I<4, OOL, IOL, asmstr, itin> {
1451 let Pattern = pattern;
1453 let Inst{6-10} = VD;
1454 let Inst{11-15} = 0;
1455 let Inst{16-20} = 0;
1456 let Inst{21-31} = xo;
1459 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1460 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1461 InstrItinClass itin, list<dag> pattern>
1462 : I<4, OOL, IOL, asmstr, itin> {
1465 let Pattern = pattern;
1468 let Inst{11-15} = 0;
1469 let Inst{16-20} = VB;
1470 let Inst{21-31} = xo;
1474 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1475 InstrItinClass itin, list<dag> pattern>
1476 : I<4, OOL, IOL, asmstr, itin> {
1482 let Pattern = pattern;
1484 let Inst{6-10} = VD;
1485 let Inst{11-15} = VA;
1486 let Inst{16-20} = VB;
1488 let Inst{22-31} = xo;
1491 // Z23-Form (used by QPX)
1492 class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1493 InstrItinClass itin, list<dag> pattern>
1494 : I<opcode, OOL, IOL, asmstr, itin> {
1500 let Pattern = pattern;
1502 bit RC = 0; // set by isDOT
1504 let Inst{6-10} = FRT;
1505 let Inst{11-15} = FRA;
1506 let Inst{16-20} = FRB;
1507 let Inst{21-22} = idx;
1508 let Inst{23-30} = xo;
1512 class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1513 InstrItinClass itin, list<dag> pattern>
1514 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1518 class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1519 InstrItinClass itin, list<dag> pattern>
1520 : I<opcode, OOL, IOL, asmstr, itin> {
1524 let Pattern = pattern;
1526 bit RC = 0; // set by isDOT
1528 let Inst{6-10} = FRT;
1529 let Inst{11-22} = idx;
1530 let Inst{23-30} = xo;
1534 //===----------------------------------------------------------------------===//
1535 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1536 : I<0, OOL, IOL, asmstr, NoItinerary> {
1537 let isCodeGenOnly = 1;
1539 let Pattern = pattern;