1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/TargetRegistry.h"
33 #include "llvm/Support/raw_ostream.h"
35 #define GET_INSTRMAP_INFO
36 #define GET_INSTRINFO_CTOR
37 #include "PPCGenInstrInfo.inc"
42 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
43 cl::desc("Disable analysis for CTR loops"));
45 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
46 cl::desc("Disable compare instruction optimization"), cl::Hidden);
48 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
49 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
50 TM(tm), RI(*TM.getSubtargetImpl()) {}
52 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
53 /// this target when scheduling the DAG.
54 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
55 const TargetMachine *TM,
56 const ScheduleDAG *DAG) const {
57 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
58 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
59 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
60 const InstrItineraryData *II = TM->getInstrItineraryData();
61 return new PPCScoreboardHazardRecognizer(II, DAG);
64 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
67 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
68 /// to use for this target when scheduling the DAG.
69 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
70 const InstrItineraryData *II,
71 const ScheduleDAG *DAG) const {
72 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
74 // Most subtargets use a PPC970 recognizer.
75 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
76 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
77 assert(TM.getInstrInfo() && "No InstrInfo?");
79 return new PPCHazardRecognizer970(TM);
82 return new PPCScoreboardHazardRecognizer(II, DAG);
85 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
86 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
87 unsigned &SrcReg, unsigned &DstReg,
88 unsigned &SubIdx) const {
89 switch (MI.getOpcode()) {
90 default: return false;
92 case PPC::EXTSW_32_64:
93 SrcReg = MI.getOperand(1).getReg();
94 DstReg = MI.getOperand(0).getReg();
100 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const {
102 // Note: This list must be kept consistent with LoadRegFromStackSlot.
103 switch (MI->getOpcode()) {
109 case PPC::RESTORE_CR:
111 case PPC::RESTORE_VRSAVE:
112 // Check for the operands added by addFrameReference (the immediate is the
113 // offset which defaults to 0).
114 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
115 MI->getOperand(2).isFI()) {
116 FrameIndex = MI->getOperand(2).getIndex();
117 return MI->getOperand(0).getReg();
124 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
125 int &FrameIndex) const {
126 // Note: This list must be kept consistent with StoreRegToStackSlot.
127 switch (MI->getOpcode()) {
135 case PPC::SPILL_VRSAVE:
136 // Check for the operands added by addFrameReference (the immediate is the
137 // offset which defaults to 0).
138 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
139 MI->getOperand(2).isFI()) {
140 FrameIndex = MI->getOperand(2).getIndex();
141 return MI->getOperand(0).getReg();
148 // commuteInstruction - We can commute rlwimi instructions, but only if the
149 // rotate amt is zero. We also have to munge the immediates a bit.
151 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
152 MachineFunction &MF = *MI->getParent()->getParent();
154 // Normal instructions can be commuted the obvious way.
155 if (MI->getOpcode() != PPC::RLWIMI &&
156 MI->getOpcode() != PPC::RLWIMIo)
157 return TargetInstrInfo::commuteInstruction(MI, NewMI);
159 // Cannot commute if it has a non-zero rotate count.
160 if (MI->getOperand(3).getImm() != 0)
163 // If we have a zero rotate count, we have:
165 // Op0 = (Op1 & ~M) | (Op2 & M)
167 // M = mask((ME+1)&31, (MB-1)&31)
168 // Op0 = (Op2 & ~M) | (Op1 & M)
171 unsigned Reg0 = MI->getOperand(0).getReg();
172 unsigned Reg1 = MI->getOperand(1).getReg();
173 unsigned Reg2 = MI->getOperand(2).getReg();
174 bool Reg1IsKill = MI->getOperand(1).isKill();
175 bool Reg2IsKill = MI->getOperand(2).isKill();
176 bool ChangeReg0 = false;
177 // If machine instrs are no longer in two-address forms, update
178 // destination register as well.
180 // Must be two address instruction!
181 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
182 "Expecting a two-address instruction!");
188 unsigned MB = MI->getOperand(4).getImm();
189 unsigned ME = MI->getOperand(5).getImm();
192 // Create a new instruction.
193 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
194 bool Reg0IsDead = MI->getOperand(0).isDead();
195 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
196 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
197 .addReg(Reg2, getKillRegState(Reg2IsKill))
198 .addReg(Reg1, getKillRegState(Reg1IsKill))
200 .addImm((MB-1) & 31);
204 MI->getOperand(0).setReg(Reg2);
205 MI->getOperand(2).setReg(Reg1);
206 MI->getOperand(1).setReg(Reg2);
207 MI->getOperand(2).setIsKill(Reg1IsKill);
208 MI->getOperand(1).setIsKill(Reg2IsKill);
210 // Swap the mask around.
211 MI->getOperand(4).setImm((ME+1) & 31);
212 MI->getOperand(5).setImm((MB-1) & 31);
216 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
217 MachineBasicBlock::iterator MI) const {
219 BuildMI(MBB, MI, DL, get(PPC::NOP));
224 // Note: If the condition register is set to CTR or CTR8 then this is a
225 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
226 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
227 MachineBasicBlock *&FBB,
228 SmallVectorImpl<MachineOperand> &Cond,
229 bool AllowModify) const {
230 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
232 // If the block has no terminators, it just falls into the block after it.
233 MachineBasicBlock::iterator I = MBB.end();
234 if (I == MBB.begin())
237 while (I->isDebugValue()) {
238 if (I == MBB.begin())
242 if (!isUnpredicatedTerminator(I))
245 // Get the last instruction in the block.
246 MachineInstr *LastInst = I;
248 // If there is only one terminator instruction, process it.
249 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
250 if (LastInst->getOpcode() == PPC::B) {
251 if (!LastInst->getOperand(0).isMBB())
253 TBB = LastInst->getOperand(0).getMBB();
255 } else if (LastInst->getOpcode() == PPC::BCC) {
256 if (!LastInst->getOperand(2).isMBB())
258 // Block ends with fall-through condbranch.
259 TBB = LastInst->getOperand(2).getMBB();
260 Cond.push_back(LastInst->getOperand(0));
261 Cond.push_back(LastInst->getOperand(1));
263 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
264 LastInst->getOpcode() == PPC::BDNZ) {
265 if (!LastInst->getOperand(0).isMBB())
267 if (DisableCTRLoopAnal)
269 TBB = LastInst->getOperand(0).getMBB();
270 Cond.push_back(MachineOperand::CreateImm(1));
271 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
274 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
275 LastInst->getOpcode() == PPC::BDZ) {
276 if (!LastInst->getOperand(0).isMBB())
278 if (DisableCTRLoopAnal)
280 TBB = LastInst->getOperand(0).getMBB();
281 Cond.push_back(MachineOperand::CreateImm(0));
282 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
287 // Otherwise, don't know what this is.
291 // Get the instruction before it if it's a terminator.
292 MachineInstr *SecondLastInst = I;
294 // If there are three terminators, we don't know what sort of block this is.
295 if (SecondLastInst && I != MBB.begin() &&
296 isUnpredicatedTerminator(--I))
299 // If the block ends with PPC::B and PPC:BCC, handle it.
300 if (SecondLastInst->getOpcode() == PPC::BCC &&
301 LastInst->getOpcode() == PPC::B) {
302 if (!SecondLastInst->getOperand(2).isMBB() ||
303 !LastInst->getOperand(0).isMBB())
305 TBB = SecondLastInst->getOperand(2).getMBB();
306 Cond.push_back(SecondLastInst->getOperand(0));
307 Cond.push_back(SecondLastInst->getOperand(1));
308 FBB = LastInst->getOperand(0).getMBB();
310 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
311 SecondLastInst->getOpcode() == PPC::BDNZ) &&
312 LastInst->getOpcode() == PPC::B) {
313 if (!SecondLastInst->getOperand(0).isMBB() ||
314 !LastInst->getOperand(0).isMBB())
316 if (DisableCTRLoopAnal)
318 TBB = SecondLastInst->getOperand(0).getMBB();
319 Cond.push_back(MachineOperand::CreateImm(1));
320 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
322 FBB = LastInst->getOperand(0).getMBB();
324 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
325 SecondLastInst->getOpcode() == PPC::BDZ) &&
326 LastInst->getOpcode() == PPC::B) {
327 if (!SecondLastInst->getOperand(0).isMBB() ||
328 !LastInst->getOperand(0).isMBB())
330 if (DisableCTRLoopAnal)
332 TBB = SecondLastInst->getOperand(0).getMBB();
333 Cond.push_back(MachineOperand::CreateImm(0));
334 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
336 FBB = LastInst->getOperand(0).getMBB();
340 // If the block ends with two PPC:Bs, handle it. The second one is not
341 // executed, so remove it.
342 if (SecondLastInst->getOpcode() == PPC::B &&
343 LastInst->getOpcode() == PPC::B) {
344 if (!SecondLastInst->getOperand(0).isMBB())
346 TBB = SecondLastInst->getOperand(0).getMBB();
349 I->eraseFromParent();
353 // Otherwise, can't handle this.
357 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
358 MachineBasicBlock::iterator I = MBB.end();
359 if (I == MBB.begin()) return 0;
361 while (I->isDebugValue()) {
362 if (I == MBB.begin())
366 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
367 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
368 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
371 // Remove the branch.
372 I->eraseFromParent();
376 if (I == MBB.begin()) return 1;
378 if (I->getOpcode() != PPC::BCC &&
379 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
380 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
383 // Remove the branch.
384 I->eraseFromParent();
389 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
390 MachineBasicBlock *FBB,
391 const SmallVectorImpl<MachineOperand> &Cond,
393 // Shouldn't be a fall through.
394 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
395 assert((Cond.size() == 2 || Cond.size() == 0) &&
396 "PPC branch conditions have two components!");
398 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
402 if (Cond.empty()) // Unconditional branch
403 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
404 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
405 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
406 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
407 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
408 else // Conditional branch
409 BuildMI(&MBB, DL, get(PPC::BCC))
410 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
414 // Two-way Conditional Branch.
415 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
416 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
417 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
418 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
420 BuildMI(&MBB, DL, get(PPC::BCC))
421 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
422 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
427 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
428 const SmallVectorImpl<MachineOperand> &Cond,
429 unsigned TrueReg, unsigned FalseReg,
430 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
431 if (!TM.getSubtargetImpl()->hasISEL())
434 if (Cond.size() != 2)
437 // If this is really a bdnz-like condition, then it cannot be turned into a
439 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
442 // Check register classes.
443 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
444 const TargetRegisterClass *RC =
445 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
449 // isel is for regular integer GPRs only.
450 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
451 !PPC::G8RCRegClass.hasSubClassEq(RC))
454 // FIXME: These numbers are for the A2, how well they work for other cores is
455 // an open question. On the A2, the isel instruction has a 2-cycle latency
456 // but single-cycle throughput. These numbers are used in combination with
457 // the MispredictPenalty setting from the active SchedMachineModel.
465 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
466 MachineBasicBlock::iterator MI, DebugLoc dl,
468 const SmallVectorImpl<MachineOperand> &Cond,
469 unsigned TrueReg, unsigned FalseReg) const {
470 assert(Cond.size() == 2 &&
471 "PPC branch conditions have two components!");
473 assert(TM.getSubtargetImpl()->hasISEL() &&
474 "Cannot insert select on target without ISEL support");
476 // Get the register classes.
477 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
478 const TargetRegisterClass *RC =
479 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
480 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
481 assert((PPC::GPRCRegClass.hasSubClassEq(RC) ||
482 PPC::G8RCRegClass.hasSubClassEq(RC)) &&
483 "isel is for regular integer GPRs only");
486 PPC::GPRCRegClass.hasSubClassEq(RC) ? PPC::ISEL : PPC::ISEL8;
487 unsigned SelectPred = Cond[0].getImm();
491 switch (SelectPred) {
492 default: llvm_unreachable("invalid predicate for isel");
493 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
494 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
495 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
496 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
497 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
498 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
499 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
500 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
503 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
504 SecondReg = SwapOps ? TrueReg : FalseReg;
506 // The first input register of isel cannot be r0. If it is a member
507 // of a register class that can be r0, then copy it first (the
508 // register allocator should eliminate the copy).
509 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
510 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
511 const TargetRegisterClass *FirstRC =
512 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
513 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
514 unsigned OldFirstReg = FirstReg;
515 FirstReg = MRI.createVirtualRegister(FirstRC);
516 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
517 .addReg(OldFirstReg);
520 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
521 .addReg(FirstReg).addReg(SecondReg)
522 .addReg(Cond[1].getReg(), 0, SubIdx);
525 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
526 MachineBasicBlock::iterator I, DebugLoc DL,
527 unsigned DestReg, unsigned SrcReg,
528 bool KillSrc) const {
530 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
532 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
534 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
536 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
538 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
540 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
543 llvm_unreachable("Impossible reg-to-reg copy");
545 const MCInstrDesc &MCID = get(Opc);
546 if (MCID.getNumOperands() == 3)
547 BuildMI(MBB, I, DL, MCID, DestReg)
548 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
550 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
553 // This function returns true if a CR spill is necessary and false otherwise.
555 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
556 unsigned SrcReg, bool isKill,
558 const TargetRegisterClass *RC,
559 SmallVectorImpl<MachineInstr*> &NewMIs,
560 bool &NonRI, bool &SpillsVRS) const{
561 // Note: If additional store instructions are added here,
562 // update isStoreToStackSlot.
565 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
566 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
568 getKillRegState(isKill)),
570 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
571 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
573 getKillRegState(isKill)),
575 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
576 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
578 getKillRegState(isKill)),
580 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
581 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
583 getKillRegState(isKill)),
585 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
586 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
588 getKillRegState(isKill)),
591 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
592 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
593 // backend currently only uses CR1EQ as an individual bit, this should
594 // not cause any bug. If we need other uses of CR bits, the following
595 // code may be invalid.
597 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
598 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
600 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
601 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
603 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
604 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
606 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
607 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
609 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
610 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
612 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
613 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
615 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
616 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
618 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
619 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
622 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
623 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
625 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
626 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
628 getKillRegState(isKill)),
631 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
632 assert(TM.getSubtargetImpl()->isDarwin() &&
633 "VRSAVE only needs spill/restore on Darwin");
634 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
636 getKillRegState(isKill)),
640 llvm_unreachable("Unknown regclass!");
647 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
648 MachineBasicBlock::iterator MI,
649 unsigned SrcReg, bool isKill, int FrameIdx,
650 const TargetRegisterClass *RC,
651 const TargetRegisterInfo *TRI) const {
652 MachineFunction &MF = *MBB.getParent();
653 SmallVector<MachineInstr*, 4> NewMIs;
655 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
656 FuncInfo->setHasSpills();
658 bool NonRI = false, SpillsVRS = false;
659 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
661 FuncInfo->setSpillsCR();
664 FuncInfo->setSpillsVRSAVE();
667 FuncInfo->setHasNonRISpills();
669 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
670 MBB.insert(MI, NewMIs[i]);
672 const MachineFrameInfo &MFI = *MF.getFrameInfo();
673 MachineMemOperand *MMO =
674 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
675 MachineMemOperand::MOStore,
676 MFI.getObjectSize(FrameIdx),
677 MFI.getObjectAlignment(FrameIdx));
678 NewMIs.back()->addMemOperand(MF, MMO);
682 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
683 unsigned DestReg, int FrameIdx,
684 const TargetRegisterClass *RC,
685 SmallVectorImpl<MachineInstr*> &NewMIs,
686 bool &NonRI, bool &SpillsVRS) const{
687 // Note: If additional load instructions are added here,
688 // update isLoadFromStackSlot.
690 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
691 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
692 DestReg), FrameIdx));
693 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
694 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
696 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
697 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
699 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
700 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
702 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
703 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
704 get(PPC::RESTORE_CR), DestReg),
707 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
710 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
711 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
713 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
714 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
716 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
717 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
719 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
720 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
722 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
723 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
725 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
726 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
728 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
729 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
731 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
732 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
735 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
736 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
738 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
739 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
742 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
743 assert(TM.getSubtargetImpl()->isDarwin() &&
744 "VRSAVE only needs spill/restore on Darwin");
745 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
746 get(PPC::RESTORE_VRSAVE),
751 llvm_unreachable("Unknown regclass!");
758 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
759 MachineBasicBlock::iterator MI,
760 unsigned DestReg, int FrameIdx,
761 const TargetRegisterClass *RC,
762 const TargetRegisterInfo *TRI) const {
763 MachineFunction &MF = *MBB.getParent();
764 SmallVector<MachineInstr*, 4> NewMIs;
766 if (MI != MBB.end()) DL = MI->getDebugLoc();
768 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
769 FuncInfo->setHasSpills();
771 bool NonRI = false, SpillsVRS = false;
772 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
774 FuncInfo->setSpillsCR();
777 FuncInfo->setSpillsVRSAVE();
780 FuncInfo->setHasNonRISpills();
782 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
783 MBB.insert(MI, NewMIs[i]);
785 const MachineFrameInfo &MFI = *MF.getFrameInfo();
786 MachineMemOperand *MMO =
787 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
788 MachineMemOperand::MOLoad,
789 MFI.getObjectSize(FrameIdx),
790 MFI.getObjectAlignment(FrameIdx));
791 NewMIs.back()->addMemOperand(MF, MMO);
795 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
796 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
797 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
798 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
800 // Leave the CR# the same, but invert the condition.
801 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
805 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
806 unsigned Reg, MachineRegisterInfo *MRI) const {
807 // For some instructions, it is legal to fold ZERO into the RA register field.
808 // A zero immediate should always be loaded with a single li.
809 unsigned DefOpc = DefMI->getOpcode();
810 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
812 if (!DefMI->getOperand(1).isImm())
814 if (DefMI->getOperand(1).getImm() != 0)
817 // Note that we cannot here invert the arguments of an isel in order to fold
818 // a ZERO into what is presented as the second argument. All we have here
819 // is the condition bit, and that might come from a CR-logical bit operation.
821 const MCInstrDesc &UseMCID = UseMI->getDesc();
823 // Only fold into real machine instructions.
824 if (UseMCID.isPseudo())
828 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
829 if (UseMI->getOperand(UseIdx).isReg() &&
830 UseMI->getOperand(UseIdx).getReg() == Reg)
833 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
834 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
836 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
838 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
839 // register (which might also be specified as a pointer class kind).
840 if (UseInfo->isLookupPtrRegClass()) {
841 if (UseInfo->RegClass /* Kind */ != 1)
844 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
845 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
849 // Make sure this is not tied to an output register (or otherwise
850 // constrained). This is true for ST?UX registers, for example, which
851 // are tied to their output registers.
852 if (UseInfo->Constraints != 0)
856 if (UseInfo->isLookupPtrRegClass()) {
857 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
858 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
860 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
861 PPC::ZERO8 : PPC::ZERO;
864 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
865 UseMI->getOperand(UseIdx).setReg(ZeroReg);
868 DefMI->eraseFromParent();
873 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
874 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
876 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
881 // We should make sure that, if we're going to predicate both sides of a
882 // condition (a diamond), that both sides don't define the counter register. We
883 // can predicate counter-decrement-based branches, but while that predicates
884 // the branching, it does not predicate the counter decrement. If we tried to
885 // merge the triangle into one predicated block, we'd decrement the counter
887 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
888 unsigned NumT, unsigned ExtraT,
889 MachineBasicBlock &FMBB,
890 unsigned NumF, unsigned ExtraF,
891 const BranchProbability &Probability) const {
892 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
896 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
897 // The predicated branches are identified by their type, not really by the
898 // explicit presence of a predicate. Furthermore, some of them can be
899 // predicated more than once. Because if conversion won't try to predicate
900 // any instruction which already claims to be predicated (by returning true
901 // here), always return false. In doing so, we let isPredicable() be the
902 // final word on whether not the instruction can be (further) predicated.
907 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
908 if (!MI->isTerminator())
911 // Conditional branch is a special case.
912 if (MI->isBranch() && !MI->isBarrier())
915 return !isPredicated(MI);
918 bool PPCInstrInfo::PredicateInstruction(
920 const SmallVectorImpl<MachineOperand> &Pred) const {
921 unsigned OpC = MI->getOpcode();
922 if (OpC == PPC::BLR) {
923 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
924 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
925 MI->setDesc(get(Pred[0].getImm() ?
926 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
927 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
929 MI->setDesc(get(PPC::BCLR));
930 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
931 .addImm(Pred[0].getImm())
932 .addReg(Pred[1].getReg());
936 } else if (OpC == PPC::B) {
937 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
938 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
939 MI->setDesc(get(Pred[0].getImm() ?
940 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
941 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
943 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
944 MI->RemoveOperand(0);
946 MI->setDesc(get(PPC::BCC));
947 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
948 .addImm(Pred[0].getImm())
949 .addReg(Pred[1].getReg())
954 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
955 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
956 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
957 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
959 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
960 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
961 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
962 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
963 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
964 .addImm(Pred[0].getImm())
965 .addReg(Pred[1].getReg());
972 bool PPCInstrInfo::SubsumesPredicate(
973 const SmallVectorImpl<MachineOperand> &Pred1,
974 const SmallVectorImpl<MachineOperand> &Pred2) const {
975 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
976 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
978 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
980 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
983 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
984 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
989 // Does P1 subsume P2, e.g. GE subsumes GT.
990 if (P1 == PPC::PRED_LE &&
991 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
993 if (P1 == PPC::PRED_GE &&
994 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1000 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1001 std::vector<MachineOperand> &Pred) const {
1002 // Note: At the present time, the contents of Pred from this function is
1003 // unused by IfConversion. This implementation follows ARM by pushing the
1004 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1005 // predicate, instructions defining CTR or CTR8 are also included as
1006 // predicate-defining instructions.
1008 const TargetRegisterClass *RCs[] =
1009 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1010 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1013 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1014 const MachineOperand &MO = MI->getOperand(i);
1015 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1016 const TargetRegisterClass *RC = RCs[c];
1018 if (MO.isDef() && RC->contains(MO.getReg())) {
1022 } else if (MO.isRegMask()) {
1023 for (TargetRegisterClass::iterator I = RC->begin(),
1024 IE = RC->end(); I != IE; ++I)
1025 if (MO.clobbersPhysReg(*I)) {
1036 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1037 unsigned OpC = MI->getOpcode();
1051 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1052 unsigned &SrcReg, unsigned &SrcReg2,
1053 int &Mask, int &Value) const {
1054 unsigned Opc = MI->getOpcode();
1057 default: return false;
1062 SrcReg = MI->getOperand(1).getReg();
1064 Value = MI->getOperand(2).getImm();
1073 SrcReg = MI->getOperand(1).getReg();
1074 SrcReg2 = MI->getOperand(2).getReg();
1079 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1080 unsigned SrcReg, unsigned SrcReg2,
1081 int Mask, int Value,
1082 const MachineRegisterInfo *MRI) const {
1086 int OpC = CmpInstr->getOpcode();
1087 unsigned CRReg = CmpInstr->getOperand(0).getReg();
1089 // FP record forms set CR1 based on the execption status bits, not a
1090 // comparison with zero.
1091 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1094 // The record forms set the condition register based on a signed comparison
1095 // with zero (so says the ISA manual). This is not as straightforward as it
1096 // seems, however, because this is always a 64-bit comparison on PPC64, even
1097 // for instructions that are 32-bit in nature (like slw for example).
1098 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1099 // for equality checks (as those don't depend on the sign). On PPC64,
1100 // we are restricted to equality for unsigned 64-bit comparisons and for
1101 // signed 32-bit comparisons the applicability is more restricted.
1102 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1103 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1104 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1105 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1107 // Get the unique definition of SrcReg.
1108 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1109 if (!MI) return false;
1110 int MIOpC = MI->getOpcode();
1112 bool equalityOnly = false;
1115 if (is32BitSignedCompare) {
1116 // We can perform this optimization only if MI is sign-extending.
1117 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1118 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1119 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1120 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1121 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1125 } else if (is32BitUnsignedCompare) {
1126 // We can perform this optimization, equality only, if MI is
1128 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1129 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1130 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1132 equalityOnly = true;
1136 equalityOnly = is64BitUnsignedCompare;
1138 equalityOnly = is32BitUnsignedCompare;
1141 // We need to check the uses of the condition register in order to reject
1142 // non-equality comparisons.
1143 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg),
1144 IE = MRI->use_end(); I != IE; ++I) {
1145 MachineInstr *UseMI = &*I;
1146 if (UseMI->getOpcode() == PPC::BCC) {
1147 unsigned Pred = UseMI->getOperand(0).getImm();
1148 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1150 } else if (UseMI->getOpcode() == PPC::ISEL ||
1151 UseMI->getOpcode() == PPC::ISEL8) {
1152 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1153 if (SubIdx != PPC::sub_eq)
1160 MachineBasicBlock::iterator I = CmpInstr;
1162 // Scan forward to find the first use of the compare.
1163 for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1165 bool FoundUse = false;
1166 for (MachineRegisterInfo::use_iterator J = MRI->use_begin(CRReg),
1167 JE = MRI->use_end(); J != JE; ++J)
1177 // There are two possible candidates which can be changed to set CR[01].
1178 // One is MI, the other is a SUB instruction.
1179 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1180 MachineInstr *Sub = NULL;
1182 // MI is not a candidate for CMPrr.
1184 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1185 // same BB as the comparison. This is to allow the check below to avoid calls
1186 // (and other explicit clobbers); instead we should really check for these
1187 // more explicitly (in at least a few predecessors).
1188 else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1189 // PPC does not have a record-form SUBri.
1194 const TargetRegisterInfo *TRI = &getRegisterInfo();
1197 // Get ready to iterate backward from CmpInstr.
1198 MachineBasicBlock::iterator E = MI,
1199 B = CmpInstr->getParent()->begin();
1201 for (; I != E && !noSub; --I) {
1202 const MachineInstr &Instr = *I;
1203 unsigned IOpC = Instr.getOpcode();
1205 if (&*I != CmpInstr && (
1206 Instr.modifiesRegister(PPC::CR0, TRI) ||
1207 Instr.readsRegister(PPC::CR0, TRI)))
1208 // This instruction modifies or uses the record condition register after
1209 // the one we want to change. While we could do this transformation, it
1210 // would likely not be profitable. This transformation removes one
1211 // instruction, and so even forcing RA to generate one move probably
1212 // makes it unprofitable.
1215 // Check whether CmpInstr can be made redundant by the current instruction.
1216 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1217 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1218 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1219 ((Instr.getOperand(1).getReg() == SrcReg &&
1220 Instr.getOperand(2).getReg() == SrcReg2) ||
1221 (Instr.getOperand(1).getReg() == SrcReg2 &&
1222 Instr.getOperand(2).getReg() == SrcReg))) {
1228 // The 'and' is below the comparison instruction.
1232 // Return false if no candidates exist.
1236 // The single candidate is called MI.
1240 MIOpC = MI->getOpcode();
1241 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1244 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1245 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1249 // FIXME: On the non-embedded POWER architectures, only some of the record
1250 // forms are fast, and we should use only the fast ones.
1252 // The defining instruction has a record form (or is already a record
1253 // form). It is possible, however, that we'll need to reverse the condition
1254 // code of the users.
1258 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1259 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1261 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1262 // needs to be updated to be based on SUB. Push the condition code
1263 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1264 // condition code of these operands will be modified.
1265 bool ShouldSwap = false;
1267 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1268 Sub->getOperand(2).getReg() == SrcReg;
1270 // The operands to subf are the opposite of sub, so only in the fixed-point
1271 // case, invert the order.
1272 ShouldSwap = !ShouldSwap;
1276 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg),
1277 IE = MRI->use_end(); I != IE; ++I) {
1278 MachineInstr *UseMI = &*I;
1279 if (UseMI->getOpcode() == PPC::BCC) {
1280 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1281 assert((!equalityOnly ||
1282 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1283 "Invalid predicate for equality-only optimization");
1284 PredsToUpdate.push_back(std::make_pair(&((*I).getOperand(0)),
1285 PPC::getSwappedPredicate(Pred)));
1286 } else if (UseMI->getOpcode() == PPC::ISEL ||
1287 UseMI->getOpcode() == PPC::ISEL8) {
1288 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1289 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1290 "Invalid CR bit for equality-only optimization");
1292 if (NewSubReg == PPC::sub_lt)
1293 NewSubReg = PPC::sub_gt;
1294 else if (NewSubReg == PPC::sub_gt)
1295 NewSubReg = PPC::sub_lt;
1297 SubRegsToUpdate.push_back(std::make_pair(&((*I).getOperand(3)),
1299 } else // We need to abort on a user we don't understand.
1303 // Create a new virtual register to hold the value of the CR set by the
1304 // record-form instruction. If the instruction was not previously in
1305 // record form, then set the kill flag on the CR.
1306 CmpInstr->eraseFromParent();
1308 MachineBasicBlock::iterator MII = MI;
1309 BuildMI(*MI->getParent(), llvm::next(MII), MI->getDebugLoc(),
1310 get(TargetOpcode::COPY), CRReg)
1311 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1313 if (MIOpC != NewOpC) {
1314 // We need to be careful here: we're replacing one instruction with
1315 // another, and we need to make sure that we get all of the right
1316 // implicit uses and defs. On the other hand, the caller may be holding
1317 // an iterator to this instruction, and so we can't delete it (this is
1318 // specifically the case if this is the instruction directly after the
1321 const MCInstrDesc &NewDesc = get(NewOpC);
1322 MI->setDesc(NewDesc);
1324 if (NewDesc.ImplicitDefs)
1325 for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1326 *ImpDefs; ++ImpDefs)
1327 if (!MI->definesRegister(*ImpDefs))
1328 MI->addOperand(*MI->getParent()->getParent(),
1329 MachineOperand::CreateReg(*ImpDefs, true, true));
1330 if (NewDesc.ImplicitUses)
1331 for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1332 *ImpUses; ++ImpUses)
1333 if (!MI->readsRegister(*ImpUses))
1334 MI->addOperand(*MI->getParent()->getParent(),
1335 MachineOperand::CreateReg(*ImpUses, false, true));
1338 // Modify the condition code of operands in OperandsToUpdate.
1339 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1340 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1341 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1342 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1344 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1345 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1350 /// GetInstSize - Return the number of bytes of code the specified
1351 /// instruction may be. This returns the maximum number of bytes.
1353 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1354 switch (MI->getOpcode()) {
1355 case PPC::INLINEASM: { // Inline Asm: Variable size.
1356 const MachineFunction *MF = MI->getParent()->getParent();
1357 const char *AsmStr = MI->getOperand(0).getSymbolName();
1358 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1360 case PPC::PROLOG_LABEL:
1363 case PPC::DBG_VALUE:
1369 return 4; // PowerPC instructions are all 4 bytes
1374 #define DEBUG_TYPE "ppc-early-ret"
1375 STATISTIC(NumBCLR, "Number of early conditional returns");
1376 STATISTIC(NumBLR, "Number of early returns");
1379 void initializePPCEarlyReturnPass(PassRegistry&);
1383 // PPCEarlyReturn pass - For simple functions without epilogue code, move
1384 // returns up, and create conditional returns, to avoid unnecessary
1385 // branch-to-blr sequences.
1386 struct PPCEarlyReturn : public MachineFunctionPass {
1388 PPCEarlyReturn() : MachineFunctionPass(ID) {
1389 initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry());
1392 const PPCTargetMachine *TM;
1393 const PPCInstrInfo *TII;
1396 bool processBlock(MachineBasicBlock &ReturnMBB) {
1397 bool Changed = false;
1399 MachineBasicBlock::iterator I = ReturnMBB.begin();
1400 I = ReturnMBB.SkipPHIsAndLabels(I);
1402 // The block must be essentially empty except for the blr.
1403 if (I == ReturnMBB.end() || I->getOpcode() != PPC::BLR ||
1404 I != ReturnMBB.getLastNonDebugInstr())
1407 SmallVector<MachineBasicBlock*, 8> PredToRemove;
1408 for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(),
1409 PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) {
1410 bool OtherReference = false, BlockChanged = false;
1411 for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) {
1412 if (J->getOpcode() == PPC::B) {
1413 if (J->getOperand(0).getMBB() == &ReturnMBB) {
1414 // This is an unconditional branch to the return. Replace the
1415 // branch with a blr.
1416 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BLR));
1417 MachineBasicBlock::iterator K = J--;
1418 K->eraseFromParent();
1419 BlockChanged = true;
1423 } else if (J->getOpcode() == PPC::BCC) {
1424 if (J->getOperand(2).getMBB() == &ReturnMBB) {
1425 // This is a conditional branch to the return. Replace the branch
1427 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCLR))
1428 .addImm(J->getOperand(0).getImm())
1429 .addReg(J->getOperand(1).getReg());
1430 MachineBasicBlock::iterator K = J--;
1431 K->eraseFromParent();
1432 BlockChanged = true;
1436 } else if (J->isBranch()) {
1437 if (J->isIndirectBranch()) {
1438 if (ReturnMBB.hasAddressTaken())
1439 OtherReference = true;
1441 for (unsigned i = 0; i < J->getNumOperands(); ++i)
1442 if (J->getOperand(i).isMBB() &&
1443 J->getOperand(i).getMBB() == &ReturnMBB)
1444 OtherReference = true;
1445 } else if (!J->isTerminator() && !J->isDebugValue())
1448 if (J == (*PI)->begin())
1454 if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB))
1455 OtherReference = true;
1457 // Predecessors are stored in a vector and can't be removed here.
1458 if (!OtherReference && BlockChanged) {
1459 PredToRemove.push_back(*PI);
1466 for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
1467 PredToRemove[i]->removeSuccessor(&ReturnMBB);
1469 if (Changed && !ReturnMBB.hasAddressTaken()) {
1470 // We now might be able to merge this blr-only block into its
1471 // by-layout predecessor.
1472 if (ReturnMBB.pred_size() == 1 &&
1473 (*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) {
1474 // Move the blr into the preceding block.
1475 MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin();
1476 PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I);
1477 PrevMBB.removeSuccessor(&ReturnMBB);
1480 if (ReturnMBB.pred_empty())
1481 ReturnMBB.eraseFromParent();
1488 virtual bool runOnMachineFunction(MachineFunction &MF) {
1489 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
1490 TII = TM->getInstrInfo();
1492 bool Changed = false;
1494 // If the function does not have at least two blocks, then there is
1499 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
1500 MachineBasicBlock &B = *I++;
1501 if (processBlock(B))
1508 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1509 MachineFunctionPass::getAnalysisUsage(AU);
1514 INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
1515 "PowerPC Early-Return Creation", false, false)
1517 char PPCEarlyReturn::ID = 0;
1519 llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }