1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCPredicates.h"
16 #include "PPCGenInstrInfo.inc"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
23 : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm),
24 RI(*TM.getSubtargetImpl(), *this) {}
26 /// getPointerRegClass - Return the register class to use to hold pointers.
27 /// This is used for addressing modes.
28 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
29 if (TM.getSubtargetImpl()->isPPC64())
30 return &PPC::G8RCRegClass;
32 return &PPC::GPRCRegClass;
36 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
38 unsigned& destReg) const {
39 MachineOpCode oc = MI.getOpcode();
40 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
41 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
42 assert(MI.getNumOperands() == 3 &&
43 MI.getOperand(0).isRegister() &&
44 MI.getOperand(1).isRegister() &&
45 MI.getOperand(2).isRegister() &&
46 "invalid PPC OR instruction!");
47 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
48 sourceReg = MI.getOperand(1).getReg();
49 destReg = MI.getOperand(0).getReg();
52 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
53 assert(MI.getNumOperands() == 3 &&
54 MI.getOperand(0).isRegister() &&
55 MI.getOperand(2).isImmediate() &&
56 "invalid PPC ADDI instruction!");
57 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
58 sourceReg = MI.getOperand(1).getReg();
59 destReg = MI.getOperand(0).getReg();
62 } else if (oc == PPC::ORI) { // ori r1, r2, 0
63 assert(MI.getNumOperands() == 3 &&
64 MI.getOperand(0).isRegister() &&
65 MI.getOperand(1).isRegister() &&
66 MI.getOperand(2).isImmediate() &&
67 "invalid PPC ORI instruction!");
68 if (MI.getOperand(2).getImmedValue()==0) {
69 sourceReg = MI.getOperand(1).getReg();
70 destReg = MI.getOperand(0).getReg();
73 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
74 oc == PPC::FMRSD) { // fmr r1, r2
75 assert(MI.getNumOperands() == 2 &&
76 MI.getOperand(0).isRegister() &&
77 MI.getOperand(1).isRegister() &&
78 "invalid PPC FMR instruction");
79 sourceReg = MI.getOperand(1).getReg();
80 destReg = MI.getOperand(0).getReg();
82 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
83 assert(MI.getNumOperands() == 2 &&
84 MI.getOperand(0).isRegister() &&
85 MI.getOperand(1).isRegister() &&
86 "invalid PPC MCRF instruction");
87 sourceReg = MI.getOperand(1).getReg();
88 destReg = MI.getOperand(0).getReg();
94 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
95 int &FrameIndex) const {
96 switch (MI->getOpcode()) {
102 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
103 MI->getOperand(2).isFrameIndex()) {
104 FrameIndex = MI->getOperand(2).getFrameIndex();
105 return MI->getOperand(0).getReg();
112 unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
113 int &FrameIndex) const {
114 switch (MI->getOpcode()) {
120 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
121 MI->getOperand(2).isFrameIndex()) {
122 FrameIndex = MI->getOperand(2).getFrameIndex();
123 return MI->getOperand(0).getReg();
130 // commuteInstruction - We can commute rlwimi instructions, but only if the
131 // rotate amt is zero. We also have to munge the immediates a bit.
132 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
133 // Normal instructions can be commuted the obvious way.
134 if (MI->getOpcode() != PPC::RLWIMI)
135 return TargetInstrInfo::commuteInstruction(MI);
137 // Cannot commute if it has a non-zero rotate count.
138 if (MI->getOperand(3).getImmedValue() != 0)
141 // If we have a zero rotate count, we have:
143 // Op0 = (Op1 & ~M) | (Op2 & M)
145 // M = mask((ME+1)&31, (MB-1)&31)
146 // Op0 = (Op2 & ~M) | (Op1 & M)
149 unsigned Reg1 = MI->getOperand(1).getReg();
150 unsigned Reg2 = MI->getOperand(2).getReg();
151 bool Reg1IsKill = MI->getOperand(1).isKill();
152 bool Reg2IsKill = MI->getOperand(2).isKill();
153 MI->getOperand(2).setReg(Reg1);
154 MI->getOperand(1).setReg(Reg2);
156 MI->getOperand(2).setIsKill();
158 MI->getOperand(2).unsetIsKill();
160 MI->getOperand(1).setIsKill();
162 MI->getOperand(1).unsetIsKill();
164 // Swap the mask around.
165 unsigned MB = MI->getOperand(4).getImmedValue();
166 unsigned ME = MI->getOperand(5).getImmedValue();
167 MI->getOperand(4).setImmedValue((ME+1) & 31);
168 MI->getOperand(5).setImmedValue((MB-1) & 31);
172 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
173 MachineBasicBlock::iterator MI) const {
174 BuildMI(MBB, MI, PPC::NOP, 0);
179 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
180 MachineBasicBlock *&FBB,
181 std::vector<MachineOperand> &Cond) const {
182 // If the block has no terminators, it just falls into the block after it.
183 MachineBasicBlock::iterator I = MBB.end();
184 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
187 // Get the last instruction in the block.
188 MachineInstr *LastInst = I;
190 // If there is only one terminator instruction, process it.
191 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
192 if (LastInst->getOpcode() == PPC::B) {
193 TBB = LastInst->getOperand(0).getMachineBasicBlock();
195 } else if (LastInst->getOpcode() == PPC::BCC) {
196 // Block ends with fall-through condbranch.
197 TBB = LastInst->getOperand(2).getMachineBasicBlock();
198 Cond.push_back(LastInst->getOperand(0));
199 Cond.push_back(LastInst->getOperand(1));
202 // Otherwise, don't know what this is.
206 // Get the instruction before it if it's a terminator.
207 MachineInstr *SecondLastInst = I;
209 // If there are three terminators, we don't know what sort of block this is.
210 if (SecondLastInst && I != MBB.begin() &&
211 isTerminatorInstr((--I)->getOpcode()))
214 // If the block ends with PPC::B and PPC:BCC, handle it.
215 if (SecondLastInst->getOpcode() == PPC::BCC &&
216 LastInst->getOpcode() == PPC::B) {
217 TBB = SecondLastInst->getOperand(2).getMachineBasicBlock();
218 Cond.push_back(SecondLastInst->getOperand(0));
219 Cond.push_back(SecondLastInst->getOperand(1));
220 FBB = LastInst->getOperand(0).getMachineBasicBlock();
224 // Otherwise, can't handle this.
228 void PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
229 MachineBasicBlock::iterator I = MBB.end();
230 if (I == MBB.begin()) return;
232 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
235 // Remove the branch.
236 I->eraseFromParent();
240 if (I == MBB.begin()) return;
242 if (I->getOpcode() != PPC::BCC)
245 // Remove the branch.
246 I->eraseFromParent();
249 void PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
250 MachineBasicBlock *FBB,
251 const std::vector<MachineOperand> &Cond) const {
252 // Shouldn't be a fall through.
253 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
254 assert((Cond.size() == 2 || Cond.size() == 0) &&
255 "PPC branch conditions have two components!");
259 if (Cond.empty()) // Unconditional branch
260 BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
261 else // Conditional branch
262 BuildMI(&MBB, PPC::BCC, 3)
263 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
267 // Two-way Conditional Branch.
268 BuildMI(&MBB, PPC::BCC, 3)
269 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
270 BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
273 bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
274 if (MBB.empty()) return false;
276 switch (MBB.back().getOpcode()) {
277 case PPC::B: // Uncond branch.
278 case PPC::BCTR: // Indirect branch.
280 default: return false;
285 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
286 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
287 // Leave the CR# the same, but invert the condition.
288 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));