1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCHazardRecognizers.h"
20 #include "MCTargetDesc/PPCPredicates.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/STLExtras.h"
33 #define GET_INSTRINFO_CTOR
34 #include "PPCGenInstrInfo.inc"
37 extern cl::opt<bool> DisablePPC32RS;
38 extern cl::opt<bool> DisablePPC64RS;
44 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
45 cl::desc("Disable analysis for CTR loops"));
47 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
48 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
49 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
51 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
52 /// this target when scheduling the DAG.
53 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
54 const TargetMachine *TM,
55 const ScheduleDAG *DAG) const {
56 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
57 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2) {
58 const InstrItineraryData *II = TM->getInstrItineraryData();
59 return new PPCScoreboardHazardRecognizer(II, DAG);
62 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
65 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
66 /// to use for this target when scheduling the DAG.
67 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
68 const InstrItineraryData *II,
69 const ScheduleDAG *DAG) const {
70 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
72 // Most subtargets use a PPC970 recognizer.
73 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2) {
74 const TargetInstrInfo *TII = TM.getInstrInfo();
75 assert(TII && "No InstrInfo?");
77 return new PPCHazardRecognizer970(*TII);
80 return new PPCScoreboardHazardRecognizer(II, DAG);
83 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
84 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
85 unsigned &SrcReg, unsigned &DstReg,
86 unsigned &SubIdx) const {
87 switch (MI.getOpcode()) {
88 default: return false;
90 case PPC::EXTSW_32_64:
91 SrcReg = MI.getOperand(1).getReg();
92 DstReg = MI.getOperand(0).getReg();
98 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
99 int &FrameIndex) const {
100 switch (MI->getOpcode()) {
106 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
107 MI->getOperand(2).isFI()) {
108 FrameIndex = MI->getOperand(2).getIndex();
109 return MI->getOperand(0).getReg();
116 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
117 int &FrameIndex) const {
118 switch (MI->getOpcode()) {
124 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
125 MI->getOperand(2).isFI()) {
126 FrameIndex = MI->getOperand(2).getIndex();
127 return MI->getOperand(0).getReg();
134 // commuteInstruction - We can commute rlwimi instructions, but only if the
135 // rotate amt is zero. We also have to munge the immediates a bit.
137 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
138 MachineFunction &MF = *MI->getParent()->getParent();
140 // Normal instructions can be commuted the obvious way.
141 if (MI->getOpcode() != PPC::RLWIMI)
142 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
144 // Cannot commute if it has a non-zero rotate count.
145 if (MI->getOperand(3).getImm() != 0)
148 // If we have a zero rotate count, we have:
150 // Op0 = (Op1 & ~M) | (Op2 & M)
152 // M = mask((ME+1)&31, (MB-1)&31)
153 // Op0 = (Op2 & ~M) | (Op1 & M)
156 unsigned Reg0 = MI->getOperand(0).getReg();
157 unsigned Reg1 = MI->getOperand(1).getReg();
158 unsigned Reg2 = MI->getOperand(2).getReg();
159 bool Reg1IsKill = MI->getOperand(1).isKill();
160 bool Reg2IsKill = MI->getOperand(2).isKill();
161 bool ChangeReg0 = false;
162 // If machine instrs are no longer in two-address forms, update
163 // destination register as well.
165 // Must be two address instruction!
166 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
167 "Expecting a two-address instruction!");
173 unsigned MB = MI->getOperand(4).getImm();
174 unsigned ME = MI->getOperand(5).getImm();
177 // Create a new instruction.
178 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
179 bool Reg0IsDead = MI->getOperand(0).isDead();
180 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
181 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
182 .addReg(Reg2, getKillRegState(Reg2IsKill))
183 .addReg(Reg1, getKillRegState(Reg1IsKill))
185 .addImm((MB-1) & 31);
189 MI->getOperand(0).setReg(Reg2);
190 MI->getOperand(2).setReg(Reg1);
191 MI->getOperand(1).setReg(Reg2);
192 MI->getOperand(2).setIsKill(Reg1IsKill);
193 MI->getOperand(1).setIsKill(Reg2IsKill);
195 // Swap the mask around.
196 MI->getOperand(4).setImm((ME+1) & 31);
197 MI->getOperand(5).setImm((MB-1) & 31);
201 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator MI) const {
204 BuildMI(MBB, MI, DL, get(PPC::NOP));
209 // Note: If the condition register is set to CTR or CTR8 then this is a
210 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
211 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
212 MachineBasicBlock *&FBB,
213 SmallVectorImpl<MachineOperand> &Cond,
214 bool AllowModify) const {
215 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
217 // If the block has no terminators, it just falls into the block after it.
218 MachineBasicBlock::iterator I = MBB.end();
219 if (I == MBB.begin())
222 while (I->isDebugValue()) {
223 if (I == MBB.begin())
227 if (!isUnpredicatedTerminator(I))
230 // Get the last instruction in the block.
231 MachineInstr *LastInst = I;
233 // If there is only one terminator instruction, process it.
234 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
235 if (LastInst->getOpcode() == PPC::B) {
236 if (!LastInst->getOperand(0).isMBB())
238 TBB = LastInst->getOperand(0).getMBB();
240 } else if (LastInst->getOpcode() == PPC::BCC) {
241 if (!LastInst->getOperand(2).isMBB())
243 // Block ends with fall-through condbranch.
244 TBB = LastInst->getOperand(2).getMBB();
245 Cond.push_back(LastInst->getOperand(0));
246 Cond.push_back(LastInst->getOperand(1));
248 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
249 LastInst->getOpcode() == PPC::BDNZ) {
250 if (!LastInst->getOperand(0).isMBB())
252 if (DisableCTRLoopAnal)
254 TBB = LastInst->getOperand(0).getMBB();
255 Cond.push_back(MachineOperand::CreateImm(1));
256 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
259 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
260 LastInst->getOpcode() == PPC::BDZ) {
261 if (!LastInst->getOperand(0).isMBB())
263 if (DisableCTRLoopAnal)
265 TBB = LastInst->getOperand(0).getMBB();
266 Cond.push_back(MachineOperand::CreateImm(0));
267 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
272 // Otherwise, don't know what this is.
276 // Get the instruction before it if it's a terminator.
277 MachineInstr *SecondLastInst = I;
279 // If there are three terminators, we don't know what sort of block this is.
280 if (SecondLastInst && I != MBB.begin() &&
281 isUnpredicatedTerminator(--I))
284 // If the block ends with PPC::B and PPC:BCC, handle it.
285 if (SecondLastInst->getOpcode() == PPC::BCC &&
286 LastInst->getOpcode() == PPC::B) {
287 if (!SecondLastInst->getOperand(2).isMBB() ||
288 !LastInst->getOperand(0).isMBB())
290 TBB = SecondLastInst->getOperand(2).getMBB();
291 Cond.push_back(SecondLastInst->getOperand(0));
292 Cond.push_back(SecondLastInst->getOperand(1));
293 FBB = LastInst->getOperand(0).getMBB();
295 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
296 SecondLastInst->getOpcode() == PPC::BDNZ) &&
297 LastInst->getOpcode() == PPC::B) {
298 if (!SecondLastInst->getOperand(0).isMBB() ||
299 !LastInst->getOperand(0).isMBB())
301 if (DisableCTRLoopAnal)
303 TBB = SecondLastInst->getOperand(0).getMBB();
304 Cond.push_back(MachineOperand::CreateImm(1));
305 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
307 FBB = LastInst->getOperand(0).getMBB();
309 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
310 SecondLastInst->getOpcode() == PPC::BDZ) &&
311 LastInst->getOpcode() == PPC::B) {
312 if (!SecondLastInst->getOperand(0).isMBB() ||
313 !LastInst->getOperand(0).isMBB())
315 if (DisableCTRLoopAnal)
317 TBB = SecondLastInst->getOperand(0).getMBB();
318 Cond.push_back(MachineOperand::CreateImm(0));
319 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
321 FBB = LastInst->getOperand(0).getMBB();
325 // If the block ends with two PPC:Bs, handle it. The second one is not
326 // executed, so remove it.
327 if (SecondLastInst->getOpcode() == PPC::B &&
328 LastInst->getOpcode() == PPC::B) {
329 if (!SecondLastInst->getOperand(0).isMBB())
331 TBB = SecondLastInst->getOperand(0).getMBB();
334 I->eraseFromParent();
338 // Otherwise, can't handle this.
342 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
343 MachineBasicBlock::iterator I = MBB.end();
344 if (I == MBB.begin()) return 0;
346 while (I->isDebugValue()) {
347 if (I == MBB.begin())
351 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
352 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
353 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
356 // Remove the branch.
357 I->eraseFromParent();
361 if (I == MBB.begin()) return 1;
363 if (I->getOpcode() != PPC::BCC &&
364 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
365 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
368 // Remove the branch.
369 I->eraseFromParent();
374 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
375 MachineBasicBlock *FBB,
376 const SmallVectorImpl<MachineOperand> &Cond,
378 // Shouldn't be a fall through.
379 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
380 assert((Cond.size() == 2 || Cond.size() == 0) &&
381 "PPC branch conditions have two components!");
383 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
387 if (Cond.empty()) // Unconditional branch
388 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
389 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
390 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
391 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
392 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
393 else // Conditional branch
394 BuildMI(&MBB, DL, get(PPC::BCC))
395 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
399 // Two-way Conditional Branch.
400 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
401 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
402 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
403 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
405 BuildMI(&MBB, DL, get(PPC::BCC))
406 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
407 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
411 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator I, DebugLoc DL,
413 unsigned DestReg, unsigned SrcReg,
414 bool KillSrc) const {
416 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
418 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
420 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
422 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
424 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
426 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
429 llvm_unreachable("Impossible reg-to-reg copy");
431 const MCInstrDesc &MCID = get(Opc);
432 if (MCID.getNumOperands() == 3)
433 BuildMI(MBB, I, DL, MCID, DestReg)
434 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
436 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
439 // This function returns true if a CR spill is necessary and false otherwise.
441 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
442 unsigned SrcReg, bool isKill,
444 const TargetRegisterClass *RC,
445 SmallVectorImpl<MachineInstr*> &NewMIs) const{
447 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
448 if (SrcReg != PPC::LR) {
449 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
451 getKillRegState(isKill)),
454 // FIXME: this spills LR immediately to memory in one step. To do this,
455 // we use R11, which we know cannot be used in the prolog/epilog. This is
457 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
458 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
460 getKillRegState(isKill)),
463 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
464 if (SrcReg != PPC::LR8) {
465 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
467 getKillRegState(isKill)),
470 // FIXME: this spills LR immediately to memory in one step. To do this,
471 // we use X11, which we know cannot be used in the prolog/epilog. This is
473 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
474 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
476 getKillRegState(isKill)),
479 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
480 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
482 getKillRegState(isKill)),
484 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
485 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
487 getKillRegState(isKill)),
489 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
490 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
491 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
492 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
494 getKillRegState(isKill)),
498 // FIXME: We need a scatch reg here. The trouble with using R0 is that
499 // it's possible for the stack frame to be so big the save location is
500 // out of range of immediate offsets, necessitating another register.
501 // We hack this on Darwin by reserving R2. It's probably broken on Linux
504 bool is64Bit = TM.getSubtargetImpl()->isPPC64();
505 // We need to store the CR in the low 4-bits of the saved value. First,
506 // issue a MFCR to save all of the CRBits.
507 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
508 (is64Bit ? PPC::X2 : PPC::R2) :
509 (is64Bit ? PPC::X0 : PPC::R0);
510 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud :
511 PPC::MFCRpseud), ScratchReg)
512 .addReg(SrcReg, getKillRegState(isKill)));
514 // If the saved register wasn't CR0, shift the bits left so that they are
516 if (SrcReg != PPC::CR0) {
517 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
518 // rlwinm scratch, scratch, ShiftBits, 0, 31.
519 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 :
520 PPC::RLWINM), ScratchReg)
521 .addReg(ScratchReg).addImm(ShiftBits)
522 .addImm(0).addImm(31));
525 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ?
526 PPC::STW8 : PPC::STW))
528 getKillRegState(isKill)),
531 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
532 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
533 // backend currently only uses CR1EQ as an individual bit, this should
534 // not cause any bug. If we need other uses of CR bits, the following
535 // code may be invalid.
537 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
538 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
540 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
541 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
543 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
544 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
546 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
547 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
549 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
550 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
552 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
553 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
555 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
556 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
558 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
559 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
562 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
563 &PPC::CRRCRegClass, NewMIs);
565 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
566 // We don't have indexed addressing for vector loads. Emit:
570 // FIXME: We use R0 here, because it isn't available for RA.
571 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
573 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
574 .addReg(SrcReg, getKillRegState(isKill))
578 llvm_unreachable("Unknown regclass!");
585 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
586 MachineBasicBlock::iterator MI,
587 unsigned SrcReg, bool isKill, int FrameIdx,
588 const TargetRegisterClass *RC,
589 const TargetRegisterInfo *TRI) const {
590 MachineFunction &MF = *MBB.getParent();
591 SmallVector<MachineInstr*, 4> NewMIs;
593 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
594 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
595 FuncInfo->setSpillsCR();
598 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
599 MBB.insert(MI, NewMIs[i]);
601 const MachineFrameInfo &MFI = *MF.getFrameInfo();
602 MachineMemOperand *MMO =
603 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
604 MachineMemOperand::MOStore,
605 MFI.getObjectSize(FrameIdx),
606 MFI.getObjectAlignment(FrameIdx));
607 NewMIs.back()->addMemOperand(MF, MMO);
611 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
612 unsigned DestReg, int FrameIdx,
613 const TargetRegisterClass *RC,
614 SmallVectorImpl<MachineInstr*> &NewMIs)const{
615 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
616 if (DestReg != PPC::LR) {
617 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
618 DestReg), FrameIdx));
620 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
621 PPC::R11), FrameIdx));
622 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
624 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
625 if (DestReg != PPC::LR8) {
626 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
629 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
630 PPC::X11), FrameIdx));
631 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
633 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
634 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
636 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
637 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
639 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
640 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
641 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
642 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
643 get(PPC::RESTORE_CR), DestReg)
647 // FIXME: We need a scatch reg here. The trouble with using R0 is that
648 // it's possible for the stack frame to be so big the save location is
649 // out of range of immediate offsets, necessitating another register.
650 // We hack this on Darwin by reserving R2. It's probably broken on Linux
652 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
654 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
655 ScratchReg), FrameIdx));
657 // If the reloaded register isn't CR0, shift the bits right so that they are
658 // in the right CR's slot.
659 if (DestReg != PPC::CR0) {
660 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
661 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
662 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
663 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
667 NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ?
668 PPC::MTCRF8 : PPC::MTCRF), DestReg)
669 .addReg(ScratchReg));
671 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
674 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
675 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
677 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
678 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
680 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
681 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
683 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
684 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
686 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
687 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
689 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
690 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
692 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
693 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
695 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
696 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
699 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
700 &PPC::CRRCRegClass, NewMIs);
702 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
703 // We don't have indexed addressing for vector loads. Emit:
707 // FIXME: We use R0 here, because it isn't available for RA.
708 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
710 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
713 llvm_unreachable("Unknown regclass!");
720 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
721 MachineBasicBlock::iterator MI,
722 unsigned DestReg, int FrameIdx,
723 const TargetRegisterClass *RC,
724 const TargetRegisterInfo *TRI) const {
725 MachineFunction &MF = *MBB.getParent();
726 SmallVector<MachineInstr*, 4> NewMIs;
728 if (MI != MBB.end()) DL = MI->getDebugLoc();
729 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) {
730 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
731 FuncInfo->setSpillsCR();
733 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
734 MBB.insert(MI, NewMIs[i]);
736 const MachineFrameInfo &MFI = *MF.getFrameInfo();
737 MachineMemOperand *MMO =
738 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
739 MachineMemOperand::MOLoad,
740 MFI.getObjectSize(FrameIdx),
741 MFI.getObjectAlignment(FrameIdx));
742 NewMIs.back()->addMemOperand(MF, MMO);
746 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
747 int FrameIx, uint64_t Offset,
750 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
751 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
756 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
757 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
758 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
759 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
761 // Leave the CR# the same, but invert the condition.
762 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
766 /// GetInstSize - Return the number of bytes of code the specified
767 /// instruction may be. This returns the maximum number of bytes.
769 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
770 switch (MI->getOpcode()) {
771 case PPC::INLINEASM: { // Inline Asm: Variable size.
772 const MachineFunction *MF = MI->getParent()->getParent();
773 const char *AsmStr = MI->getOperand(0).getSymbolName();
774 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
776 case PPC::PROLOG_LABEL:
781 case PPC::BL8_NOP_ELF:
782 case PPC::BLA8_NOP_ELF:
785 return 4; // PowerPC instructions are all 4 bytes