1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCHazardRecognizers.h"
20 #include "MCTargetDesc/PPCPredicates.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/ADT/STLExtras.h"
32 #define GET_INSTRINFO_CTOR
33 #include "PPCGenInstrInfo.inc"
36 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
37 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
42 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
43 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
44 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
46 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
47 /// this target when scheduling the DAG.
48 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
49 const TargetMachine *TM,
50 const ScheduleDAG *DAG) const {
51 // Should use subtarget info to pick the right hazard recognizer. For
52 // now, always return a PPC970 recognizer.
53 const TargetInstrInfo *TII = TM->getInstrInfo();
55 assert(TII && "No InstrInfo?");
57 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
58 if (Directive == PPC::DIR_440) {
59 // Disable the hazard recognizer for now, as it doesn't support
60 // bottom-up scheduling.
61 //const InstrItineraryData *II = TM->getInstrItineraryData();
62 //return new PPCHazardRecognizer440(II, DAG);
63 return new ScheduleHazardRecognizer();
66 // Disable the hazard recognizer for now, as it doesn't support
67 // bottom-up scheduling.
68 //return new PPCHazardRecognizer970(*TII);
69 return new ScheduleHazardRecognizer();
73 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
74 int &FrameIndex) const {
75 switch (MI->getOpcode()) {
81 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
82 MI->getOperand(2).isFI()) {
83 FrameIndex = MI->getOperand(2).getIndex();
84 return MI->getOperand(0).getReg();
91 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
92 int &FrameIndex) const {
93 switch (MI->getOpcode()) {
99 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
100 MI->getOperand(2).isFI()) {
101 FrameIndex = MI->getOperand(2).getIndex();
102 return MI->getOperand(0).getReg();
109 // commuteInstruction - We can commute rlwimi instructions, but only if the
110 // rotate amt is zero. We also have to munge the immediates a bit.
112 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
113 MachineFunction &MF = *MI->getParent()->getParent();
115 // Normal instructions can be commuted the obvious way.
116 if (MI->getOpcode() != PPC::RLWIMI)
117 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
119 // Cannot commute if it has a non-zero rotate count.
120 if (MI->getOperand(3).getImm() != 0)
123 // If we have a zero rotate count, we have:
125 // Op0 = (Op1 & ~M) | (Op2 & M)
127 // M = mask((ME+1)&31, (MB-1)&31)
128 // Op0 = (Op2 & ~M) | (Op1 & M)
131 unsigned Reg0 = MI->getOperand(0).getReg();
132 unsigned Reg1 = MI->getOperand(1).getReg();
133 unsigned Reg2 = MI->getOperand(2).getReg();
134 bool Reg1IsKill = MI->getOperand(1).isKill();
135 bool Reg2IsKill = MI->getOperand(2).isKill();
136 bool ChangeReg0 = false;
137 // If machine instrs are no longer in two-address forms, update
138 // destination register as well.
140 // Must be two address instruction!
141 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
142 "Expecting a two-address instruction!");
148 unsigned MB = MI->getOperand(4).getImm();
149 unsigned ME = MI->getOperand(5).getImm();
152 // Create a new instruction.
153 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
154 bool Reg0IsDead = MI->getOperand(0).isDead();
155 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
156 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
157 .addReg(Reg2, getKillRegState(Reg2IsKill))
158 .addReg(Reg1, getKillRegState(Reg1IsKill))
160 .addImm((MB-1) & 31);
164 MI->getOperand(0).setReg(Reg2);
165 MI->getOperand(2).setReg(Reg1);
166 MI->getOperand(1).setReg(Reg2);
167 MI->getOperand(2).setIsKill(Reg1IsKill);
168 MI->getOperand(1).setIsKill(Reg2IsKill);
170 // Swap the mask around.
171 MI->getOperand(4).setImm((ME+1) & 31);
172 MI->getOperand(5).setImm((MB-1) & 31);
176 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
177 MachineBasicBlock::iterator MI) const {
179 BuildMI(MBB, MI, DL, get(PPC::NOP));
184 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
185 MachineBasicBlock *&FBB,
186 SmallVectorImpl<MachineOperand> &Cond,
187 bool AllowModify) const {
188 // If the block has no terminators, it just falls into the block after it.
189 MachineBasicBlock::iterator I = MBB.end();
190 if (I == MBB.begin())
193 while (I->isDebugValue()) {
194 if (I == MBB.begin())
198 if (!isUnpredicatedTerminator(I))
201 // Get the last instruction in the block.
202 MachineInstr *LastInst = I;
204 // If there is only one terminator instruction, process it.
205 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
206 if (LastInst->getOpcode() == PPC::B) {
207 if (!LastInst->getOperand(0).isMBB())
209 TBB = LastInst->getOperand(0).getMBB();
211 } else if (LastInst->getOpcode() == PPC::BCC) {
212 if (!LastInst->getOperand(2).isMBB())
214 // Block ends with fall-through condbranch.
215 TBB = LastInst->getOperand(2).getMBB();
216 Cond.push_back(LastInst->getOperand(0));
217 Cond.push_back(LastInst->getOperand(1));
220 // Otherwise, don't know what this is.
224 // Get the instruction before it if it's a terminator.
225 MachineInstr *SecondLastInst = I;
227 // If there are three terminators, we don't know what sort of block this is.
228 if (SecondLastInst && I != MBB.begin() &&
229 isUnpredicatedTerminator(--I))
232 // If the block ends with PPC::B and PPC:BCC, handle it.
233 if (SecondLastInst->getOpcode() == PPC::BCC &&
234 LastInst->getOpcode() == PPC::B) {
235 if (!SecondLastInst->getOperand(2).isMBB() ||
236 !LastInst->getOperand(0).isMBB())
238 TBB = SecondLastInst->getOperand(2).getMBB();
239 Cond.push_back(SecondLastInst->getOperand(0));
240 Cond.push_back(SecondLastInst->getOperand(1));
241 FBB = LastInst->getOperand(0).getMBB();
245 // If the block ends with two PPC:Bs, handle it. The second one is not
246 // executed, so remove it.
247 if (SecondLastInst->getOpcode() == PPC::B &&
248 LastInst->getOpcode() == PPC::B) {
249 if (!SecondLastInst->getOperand(0).isMBB())
251 TBB = SecondLastInst->getOperand(0).getMBB();
254 I->eraseFromParent();
258 // Otherwise, can't handle this.
262 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
263 MachineBasicBlock::iterator I = MBB.end();
264 if (I == MBB.begin()) return 0;
266 while (I->isDebugValue()) {
267 if (I == MBB.begin())
271 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
274 // Remove the branch.
275 I->eraseFromParent();
279 if (I == MBB.begin()) return 1;
281 if (I->getOpcode() != PPC::BCC)
284 // Remove the branch.
285 I->eraseFromParent();
290 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
291 MachineBasicBlock *FBB,
292 const SmallVectorImpl<MachineOperand> &Cond,
294 // Shouldn't be a fall through.
295 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
296 assert((Cond.size() == 2 || Cond.size() == 0) &&
297 "PPC branch conditions have two components!");
301 if (Cond.empty()) // Unconditional branch
302 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
303 else // Conditional branch
304 BuildMI(&MBB, DL, get(PPC::BCC))
305 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
309 // Two-way Conditional Branch.
310 BuildMI(&MBB, DL, get(PPC::BCC))
311 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
312 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
316 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
317 MachineBasicBlock::iterator I, DebugLoc DL,
318 unsigned DestReg, unsigned SrcReg,
319 bool KillSrc) const {
321 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
323 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
325 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
327 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
329 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
331 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
334 llvm_unreachable("Impossible reg-to-reg copy");
336 const MCInstrDesc &MCID = get(Opc);
337 if (MCID.getNumOperands() == 3)
338 BuildMI(MBB, I, DL, MCID, DestReg)
339 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
341 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
345 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
346 unsigned SrcReg, bool isKill,
348 const TargetRegisterClass *RC,
349 SmallVectorImpl<MachineInstr*> &NewMIs) const{
351 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
352 if (SrcReg != PPC::LR) {
353 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
355 getKillRegState(isKill)),
358 // FIXME: this spills LR immediately to memory in one step. To do this,
359 // we use R11, which we know cannot be used in the prolog/epilog. This is
361 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
362 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
364 getKillRegState(isKill)),
367 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
368 if (SrcReg != PPC::LR8) {
369 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
371 getKillRegState(isKill)),
374 // FIXME: this spills LR immediately to memory in one step. To do this,
375 // we use R11, which we know cannot be used in the prolog/epilog. This is
377 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
378 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
380 getKillRegState(isKill)),
383 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
384 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
386 getKillRegState(isKill)),
388 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
389 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
391 getKillRegState(isKill)),
393 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
394 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
395 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
396 // FIXME (64-bit): Enable
397 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
399 getKillRegState(isKill)),
403 // FIXME: We need a scatch reg here. The trouble with using R0 is that
404 // it's possible for the stack frame to be so big the save location is
405 // out of range of immediate offsets, necessitating another register.
406 // We hack this on Darwin by reserving R2. It's probably broken on Linux
409 // We need to store the CR in the low 4-bits of the saved value. First,
410 // issue a MFCR to save all of the CRBits.
411 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
413 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
414 .addReg(SrcReg, getKillRegState(isKill)));
416 // If the saved register wasn't CR0, shift the bits left so that they are
418 if (SrcReg != PPC::CR0) {
419 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
420 // rlwinm scratch, scratch, ShiftBits, 0, 31.
421 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
422 .addReg(ScratchReg).addImm(ShiftBits)
423 .addImm(0).addImm(31));
426 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
428 getKillRegState(isKill)),
431 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
432 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
433 // backend currently only uses CR1EQ as an individual bit, this should
434 // not cause any bug. If we need other uses of CR bits, the following
435 // code may be invalid.
437 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
438 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
440 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
441 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
443 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
444 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
446 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
447 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
449 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
450 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
452 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
453 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
455 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
456 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
458 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
459 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
462 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
463 PPC::CRRCRegisterClass, NewMIs);
465 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
466 // We don't have indexed addressing for vector loads. Emit:
470 // FIXME: We use R0 here, because it isn't available for RA.
471 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
473 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
474 .addReg(SrcReg, getKillRegState(isKill))
478 llvm_unreachable("Unknown regclass!");
485 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
486 MachineBasicBlock::iterator MI,
487 unsigned SrcReg, bool isKill, int FrameIdx,
488 const TargetRegisterClass *RC,
489 const TargetRegisterInfo *TRI) const {
490 MachineFunction &MF = *MBB.getParent();
491 SmallVector<MachineInstr*, 4> NewMIs;
493 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
494 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
495 FuncInfo->setSpillsCR();
498 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
499 MBB.insert(MI, NewMIs[i]);
501 const MachineFrameInfo &MFI = *MF.getFrameInfo();
502 MachineMemOperand *MMO =
503 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
504 MachineMemOperand::MOStore,
505 MFI.getObjectSize(FrameIdx),
506 MFI.getObjectAlignment(FrameIdx));
507 NewMIs.back()->addMemOperand(MF, MMO);
511 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
512 unsigned DestReg, int FrameIdx,
513 const TargetRegisterClass *RC,
514 SmallVectorImpl<MachineInstr*> &NewMIs)const{
515 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
516 if (DestReg != PPC::LR) {
517 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
518 DestReg), FrameIdx));
520 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
521 PPC::R11), FrameIdx));
522 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
524 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
525 if (DestReg != PPC::LR8) {
526 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
529 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
530 PPC::R11), FrameIdx));
531 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
533 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
534 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
536 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
537 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
539 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
540 // FIXME: We need a scatch reg here. The trouble with using R0 is that
541 // it's possible for the stack frame to be so big the save location is
542 // out of range of immediate offsets, necessitating another register.
543 // We hack this on Darwin by reserving R2. It's probably broken on Linux
545 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
547 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
548 ScratchReg), FrameIdx));
550 // If the reloaded register isn't CR0, shift the bits right so that they are
551 // in the right CR's slot.
552 if (DestReg != PPC::CR0) {
553 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
554 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
555 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
556 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
560 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
561 .addReg(ScratchReg));
562 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
565 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
566 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
568 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
569 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
571 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
572 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
574 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
575 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
577 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
578 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
580 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
581 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
583 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
584 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
586 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
587 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
590 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
591 PPC::CRRCRegisterClass, NewMIs);
593 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
594 // We don't have indexed addressing for vector loads. Emit:
598 // FIXME: We use R0 here, because it isn't available for RA.
599 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
601 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
604 llvm_unreachable("Unknown regclass!");
609 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
610 MachineBasicBlock::iterator MI,
611 unsigned DestReg, int FrameIdx,
612 const TargetRegisterClass *RC,
613 const TargetRegisterInfo *TRI) const {
614 MachineFunction &MF = *MBB.getParent();
615 SmallVector<MachineInstr*, 4> NewMIs;
617 if (MI != MBB.end()) DL = MI->getDebugLoc();
618 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
619 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
620 MBB.insert(MI, NewMIs[i]);
622 const MachineFrameInfo &MFI = *MF.getFrameInfo();
623 MachineMemOperand *MMO =
624 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
625 MachineMemOperand::MOLoad,
626 MFI.getObjectSize(FrameIdx),
627 MFI.getObjectAlignment(FrameIdx));
628 NewMIs.back()->addMemOperand(MF, MMO);
632 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
633 int FrameIx, uint64_t Offset,
636 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
637 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
642 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
643 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
644 // Leave the CR# the same, but invert the condition.
645 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
649 /// GetInstSize - Return the number of bytes of code the specified
650 /// instruction may be. This returns the maximum number of bytes.
652 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
653 switch (MI->getOpcode()) {
654 case PPC::INLINEASM: { // Inline Asm: Variable size.
655 const MachineFunction *MF = MI->getParent()->getParent();
656 const char *AsmStr = MI->getOperand(0).getSymbolName();
657 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
659 case PPC::PROLOG_LABEL:
665 return 4; // PowerPC instructions are all 4 bytes